Re: [PATCH 02/20] tcg: Add opcodes for vector nand, nor, eqv

On 12/18/21 20:42, Richard Henderson wrote: > We've had placeholders for these opcodes for a while, > and should have support on ppc, s390x and avx512 hosts. > > Signed-off-by: Richard Henderson > --- > include/tcg/tcg-opc.h| 3 +++ > include/tcg/tcg.h| 3 +++ > tcg/aarch64/tcg-tar

Re: [PATCH 01/20] tcg/optimize: Fix folding of vector ops

On 12/18/21 20:42, Richard Henderson wrote: > Bitwise operations are easy to fold, because the operation is > identical regardess of element size. But add and sub need Typo "regardless". > extra element size info that is not currently propagated. > > Fixes: 2f9f08ba43d > Signed-off-by: Richard

[PULL 01/16] configure: make $targetos lowercase, use windows instead of MINGW32

targetos is already mostly the same as Meson host_machine.system(), just in CamelCase. Adjust Windows, which is different, and switch to lowercase to match Meson. Reviewed-by: Richard Henderson Signed-off-by: Paolo Bonzini --- configure | 58

[PULL 03/16] configure: unify two case statements on $cpu

Reviewed-by: Richard Henderson Signed-off-by: Paolo Bonzini --- configure | 67 ++- 1 file changed, 32 insertions(+), 35 deletions(-) diff --git a/configure b/configure index f0a82dd8f5..77ccc15b73 100755 --- a/configure +++ b/configure @@ -63

[PULL 00/16] Misc patches for 2021-12-20

The following changes since commit 90978e15bc9a23c208b25bf7ea697a5d0925562b: Merge tag 'trivial-branch-for-7.0-pull-request' of https://gitlab.com/laurent_vivier/qemu into staging (2021-12-17 13:15:38 -0800) are available in the Git repository at: https://gitlab.com/bonzini/qemu.git tags/fo

[PULL 02/16] configure: move target detection before CPU detection

This makes more sense, since target detection can affect CPU detection on Solaris. Signed-off-by: Paolo Bonzini --- configure | 115 ++ 1 file changed, 55 insertions(+), 60 deletions(-) diff --git a/configure b/configure index e72e34b684..f0a8

[PULL 06/16] meson: rename "arch" variable

Avoid confusion between the ARCH variable of configure/config-host.mak and the same-named variable of meson.build. Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Signed-off-by: Paolo Bonzini --- meson.build | 12 ++-- 1 file changed, 6 insertions(+), 6 deletions(-)

[PULL 12/16] meson: add "check" argument to run_command

Meson is planning to change the default of the "check" argument to run_command (from false to true). Be explicit and include it in all invocations. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Paolo Bonzini --- docs/meson.build | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)

[PULL 05/16] configure: unify x86_64 and x32

The only difference between the two, as far as either configure or Meson are concerned, is in the multilib flags passed to the compiler. For QEMU, this fixes the handling of TYPE_OLDDEVT in include/exec/user/thunk.h and enables testing of dirty ring buffer, because both are using HOST_X86_64. For

[PULL 04/16] configure: unify ppc64 and ppc64le

The only difference between the two, as far as either configure or Meson are concerned, is the default endianness of the compiler. For tests/tcg, specify the endianness explicitly on the command line; for configure, do the same so that it is possible to have --cpu=ppc64le on a bigendian system or

[PULL 08/16] configure: remove unnecessary symlinks

Make pc-bios/meson.build use the files in the source tree as inputs to bzip2. Reviewed-by: Richard Henderson Signed-off-by: Paolo Bonzini --- configure | 1 - pc-bios/meson.build | 2 +- 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/configure b/configure index 6e06ac61

[PULL 07/16] configure, meson: move ARCH to meson.build

$ARCH and the HOST_* symbols are only used by the QEMU build; configure uses $cpu instead. Remove it from config-host.mak. Reviewed-by: Richard Henderson Signed-off-by: Paolo Bonzini --- configure | 21 - meson.build | 26 +- 2 files changed, 21 in

[PULL 14/16] hw/scsi/megasas: Fails command if SGL buffer overflows

From: Philippe Mathieu-Daudé If we detect an overflow on the SGL buffer, do not keep processing the command: discard it. TARGET_FAILURE sense code will be returned (MFI_STAT_SCSI_DONE_WITH_ERROR). Reported-by: Alexander Bulekov Resolves: https://gitlab.com/qemu-project/qemu/-/issues/521 Signed-

[PULL 11/16] cpu: remove unnecessary #ifdef CONFIG_TCG

"if (tcg_enabled())" allows elision of the code inside it; we only need the prototype to exist, so that the code compile even for the --disable-tcg case. Signed-off-by: Paolo Bonzini --- cpu.c | 5 - include/exec/cpu-all.h | 2 -- 2 files changed, 7 deletions(-) diff --git

[PULL 09/16] configure: remove DIRS

DIRS is used to create the directory in which the LINKS symbolic links reside, or to create directories for object files. The former can be done directly in the symlinking loop, while the latter is done by Meson already, so DIRS is not necessary. Reviewed-by: Peter Maydell Reviewed-by: Alex Benn

[PULL 10/16] meson: reenable test-fdmon-epoll

The test was disabled when CONFIG_EPOLL_CREATE1 was moved out of config-host.mak. Fix the condition. Signed-off-by: Paolo Bonzini --- tests/unit/meson.build | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/unit/meson.build b/tests/unit/meson.build index acac3622ed..90ac

[PULL 16/16] hw/i386/vmmouse: Require 'i8042' property to be set

From: Philippe Mathieu-Daudé If the 'i8042' property is not set, mouse events handled by vmmouse_mouse_event() end calling i8042_isa_mouse_fake_event() with a NULL argument, resulting in ps2_mouse_fake_event() being called with invalid PS2MouseState pointer. Fix by requiring the 'i8042' property

[PULL 13/16] hw/scsi: Fix scsi_bus_init_named() docstring

From: Philippe Mathieu-Daudé Commit 739e95f5741 ("scsi: Replace scsi_bus_new() with scsi_bus_init(), scsi_bus_init_named()") forgot to rename scsi_bus_init() in the function documentation string. Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20211122104744.1051554-1-f4...@amsat.org> Review

[PULL 15/16] tests/qtest/fuzz-megasas-test: Add test for GitLab issue #521

From: Philippe Mathieu-Daudé Without the previous commit, this test triggers: $ make check-qtest-x86_64 [...] Running test qtest-x86_64/fuzz-megasas-test qemu-system-x86_64: softmmu/physmem.c:3229: address_space_unmap: Assertion `mr != NULL' failed. Broken pipe ERROR qtest-x86_64/fu

[PATCH 1/3] linux-user: netlink: update IFLA entries

Add IFLA_PHYS_PORT_ID, IFLA_PARENT_DEV_NAME, IFLA_PARENT_DEV_BUS_NAME # QEMU_LOG=unimp ip a Unknown host QEMU_IFLA type: 56 Unknown host QEMU_IFLA type: 57 Unknown host QEMU_IFLA type: 34 Signed-off-by: Laurent Vivier --- linux-user/fd-trans.c | 6 ++ 1 file changed, 6 insertions(+)

[PATCH 3/3] linux-user: netlink: update IFLA_BRPORT entries

add IFLA_BRPORT_MCAST_EHT_HOSTS_LIMIT and IFLA_BRPORT_MCAST_EHT_HOSTS_CNT # QEMU_LOG=unimp ip a Unknown QEMU_IFLA_BRPORT type 37 Unknown QEMU_IFLA_BRPORT type 38 Signed-off-by: Laurent Vivier --- linux-user/fd-trans.c | 4 1 file changed, 4 insertions(+) diff --git a/linux-user/fd-t

[PATCH 2/3] linux-user: netlink: Add IFLA_VFINFO_LIST

# QEMU_LOG=unimp ip a Unknown host QEMU_IFLA type: 22 Signed-off-by: Laurent Vivier --- linux-user/fd-trans.c | 174 ++ 1 file changed, 174 insertions(+) diff --git a/linux-user/fd-trans.c b/linux-user/fd-trans.c index 14c19a90b2b0..36e4a4c2aae8 10064

Re: [PATCH] linux-user/signal: Map exit signals in SIGCHLD siginfo_t

CC'ing Alistair and Andreas that were involved in original fix 1c3dfb506ea3 ("linux-user/signal: Decode waitid si_code") Thanks, Laurent Le 23/10/2021 à 21:59, Matthias Schiffer a écrit : When converting a siginfo_t from waitid(), the interpretation of si_status depends on the value of si_code

Re: [PATCH] linux-user/hexagon: Use generic target_stat64 structure

Le 16/11/2021 à 22:09, Philippe Mathieu-Daudé a écrit : Linux Hexagon port doesn't define a specific 'struct stat' but uses the generic one (see Linux commit 6103ec56c65c [*] "asm-generic: add generic ABI headers" which predates the introduction of the Hexagon port). Remove the target specific t

Re: [PATCH v2] linux-user: Mark cpu_loop() with noreturn attribute

Le 15/12/2021 à 11:55, Philippe Mathieu-Daudé a écrit : Ping? (patch reviewed) On 11/6/21 12:39, Philippe Mathieu-Daudé wrote: cpu_loop() never exits, so mark it with QEMU_NORETURN. Reviewed-by: Richard Henderson Reviewed-By: Warner Losh Reviewed-by: Bin Meng Signed-off-by: Philippe Mathieu

Re: [PATCH 1/2] linux-user: add sched_getattr support

Le 11/12/2021 à 03:27, Tonis Tiigi a écrit : Signed-off-by: Tonis Tiigi --- linux-user/syscall.c | 55 +++ linux-user/syscall_defs.h | 15 +++ 2 files changed, 70 insertions(+) diff --git a/linux-user/syscall.c b/linux-user/syscall.c index f1

Re: [PATCH 2/2] linux-user: call set/getscheduler set/getparam directly

Le 11/12/2021 à 03:27, Tonis Tiigi a écrit : There seems to be difference in syscall and libc definition of these methods and therefore musl does not implement them (1e21e78bf7). Call syscall directly to ensure the behavior of the libc of user application, not the libc that was used to build QEMU

[PATCH] ui/gtk: Fix resolution change in fullscreen

When the guest resolution changes and the UI is in full screen, do not update the size hints. The gfx.scale_x and gfx.scale_y variables are still wrong as they will be only recomputed on gd_draw_event. Just keep the window in fullscreen mode instead. Signed-off-by: Jindřich Makovička --- ui/gtk

Re: [PATCH] linux-user/signal: Map exit signals in SIGCHLD siginfo_t

Well, the original fix 1c3dfb506ea3 did clearly improve things for me, but it wasn't complete yet. At some point I gave up on finding a minimal reproducer for my remaining problems (futex-related hangs in a complex python+bash app). So, this *may* be the missing piece. Will test, but that take

Re: [PATCH v2] audio: Add sndio backend

Hi Alexandre, sndio is the native API used by OpenBSD, although it has been ported to other *BSD's and Linux (packages for Ubuntu, Debian, Void, Arch, etc.). Signed-off-by: Brad Smith Signed-off-by: Alexandre Ratchov --- Thank you for the reviews and all the comments. Here's a second diff with

[PATCH] hw/nvram: at24 return 0xff if 1 byte address

The at24 eeproms are 2 byte devices that return 0xff when they are read from with a partial (1-byte) address written. This distinction was found comparing model behavior to real hardware testing. Tested: `i2ctransfer -f -y 45 w1@85 0 r1` returns 0xff instead of next byte Signed-off-by: Patrick V

[PATCH 1/2] net/colo-compare.c: Optimize compare order for performance

COLO-compare use the glib function g_queue_find_custom to dump another VM's networking packet to compare. But this function always start find from the queue->head(here is the newest packet), It will reduce the success rate of comparison. So this patch reversed the order of the queues for performanc

[PATCH 2/2] net/colo-compare.c: Update the default value comments

Make the comments consistent with the REGULAR_PACKET_CHECK_MS. Signed-off-by: Zhang Chen --- net/colo-compare.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/net/colo-compare.c b/net/colo-compare.c index 216de5a12b..62554b5b3c 100644 --- a/net/colo-compare.c +++ b/net/colo-

Re: [PATCH v2 1/5] hw/qdev: Cosmetic around documentation

On 2021/12/18 21:04, Philippe Mathieu-Daudé wrote: Add empty lines to have a clearer distinction between different functions declarations. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/qdev-core.h | 11 +++ 1 file changed, 11 insertions(+) Reviewed-by: Yanan Wang Thanks,

Re: [PATCH v2 2/5] hw/qdev: Correct qdev_init_gpio_out_named() documentation

On 2021/12/18 21:04, Philippe Mathieu-Daudé wrote: qdev_init_gpio_out_named() is described as qdev_init_gpio_out(), and referring to itself in an endless loop, which is confusing. Fix. Reported-by: Yanan Wang Signed-off-by: Philippe Mathieu-Daudé --- include/hw/qdev-core.h | 2 +- 1 file

Re: [PATCH v2 3/5] hw/qdev: Correct qdev_connect_gpio_out_named() documentation

On 2021/12/18 21:04, Philippe Mathieu-Daudé wrote: qdev_connect_gpio_out_named() is described as qdev_connect_gpio_out(), and referring to itself in an endless loop, which is confusing. Fix. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/qdev-core.h | 5 +++-- 1 file changed, 3 inser

Re: [PATCH v2 5/5] hw/input/pckbd: Open-code i8042_setup_a20_line() wrapper

On 2021/12/18 21:04, Philippe Mathieu-Daudé wrote: Since the named GPIO lines are a "public" interface to the device, we can directly call qdev_connect_gpio_out_named(), making it consistent with how the other A20 input source (port92) is wired. Suggested-by: Peter Maydell Signed-off-by: Phil

Re: [RFC] vhost-vdpa-net: add vhost-vdpa-net host device support

On Fri, Dec 17, 2021 at 4:35 PM Stefan Hajnoczi wrote: > > On Fri, Dec 17, 2021 at 12:26:53PM +0800, Jason Wang wrote: > > Dave: You created the VIRTIO vmstate infrastructure in QEMU. Please see > the bottom of this email about moving to a standard VIRTIO device > save/load format defined by the V

Re: [PATCH v2 5/9] target/riscv: Mark the Hypervisor extension as non experimental

On Thu, Dec 16, 2021 at 12:55 PM Alistair Francis wrote: > > From: Alistair Francis > > The Hypervisor spec is now frozen, so remove the experimental tag. > > Signed-off-by: Alistair Francis > --- > target/riscv/cpu.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > Reviewed-by: Bin M

Re: [PATCH v2 6/9] target/riscv: Enable the Hypervisor extension by default

On Thu, Dec 16, 2021 at 12:55 PM Alistair Francis wrote: > > From: Alistair Francis > > Let's enable the Hypervisor extension by default. This doesn't affect > named CPUs (such as lowrisc-ibex or sifive-u54) but does enable the > Hypervisor extensions by default for the virt machine. > > Signed-o

Virtio-GPU Xres and Yres seettings

Hi Team, I am working on a Virtio-GPU device (backend) for one of our customer projects - we are using the Virtio-GPU driver (frontend) to drive our device. Our device code has been written using Qemu virtio-gpu device code as a reference. Our device is setting the resolution to 1024x768 as a resp

Re: [PULL 00/16] Misc patches for 2021-12-20

On 12/19/21 6:16 AM, Paolo Bonzini wrote: The following changes since commit 90978e15bc9a23c208b25bf7ea697a5d0925562b: Merge tag 'trivial-branch-for-7.0-pull-request' of https://gitlab.com/laurent_vivier/qemu into staging (2021-12-17 13:15:38 -0800) are available in the Git repository at:

[PULL 00/88] riscv-to-apply queue

From: Alistair Francis The following changes since commit 212a33d3b0c65ae2583bb1d06cb140cd0890894c: Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging (2021-12-19 16:36:10 -0800) are available in the Git repository at: g...@github.com:alistair23/qemu.git tags/pull-ri

[PULL 01/88] target/riscv: zfh: half-precision load and store

From: Kito Cheng Signed-off-by: Kito Cheng Signed-off-by: Chih-Min Chao Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Message-id: 20211210074329.5775-2-frank.ch...@sifive.com Signed-off-by: Alistair Francis --- target/riscv/cpu.h| 1 + target/riscv/insn3

[PULL 05/88] target/riscv: zfh: half-precision floating-point classify

From: Kito Cheng Signed-off-by: Kito Cheng Signed-off-by: Chih-Min Chao Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-id: 20211210074329.5775-6-frank.ch...@sifive.com Signed-off-by: Alistair Francis --- target/riscv/helper.h

[PULL 02/88] target/riscv: zfh: half-precision computational

From: Kito Cheng Signed-off-by: Kito Cheng Signed-off-by: Chih-Min Chao Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-id: 20211210074329.5775-3-frank.ch...@sifive.com Signed-off-by: Alistair Francis --- target/riscv/helper.h

[PULL 06/88] target/riscv: zfh: add Zfh cpu property

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Alistair Francis Message-id: 20211210074329.5775-7-frank.ch...@sifive.com Signed-off-by: Alistair Francis --- target/riscv/cpu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index f8129981

[PULL 04/88] target/riscv: zfh: half-precision floating-point compare

From: Kito Cheng Signed-off-by: Kito Cheng Signed-off-by: Chih-Min Chao Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-id: 20211210074329.5775-5-frank.ch...@sifive.com Signed-off-by: Alistair Francis --- target/riscv/helper.h

[PULL 07/88] target/riscv: zfh: implement zfhmin extension

From: Frank Chang Zfhmin extension is a subset of Zfh extension, consisting only of data transfer and conversion instructions. If enabled, only the following instructions from Zfh extension are included: * flh, fsh, fmv.x.h, fmv.h.x, fcvt.s.h, fcvt.h.s * If D extension is present: fcvt.d.h,

[PULL 03/88] target/riscv: zfh: half-precision convert and move

From: Kito Cheng Signed-off-by: Kito Cheng Signed-off-by: Chih-Min Chao Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Acked-by: Alistair Francis Message-id: 20211210074329.5775-4-frank.ch...@sifive.com Signed-off-by: Alistair Francis --- target/riscv/helper.h

[PULL 09/88] target/riscv: drop vector 0.7.1 and add 1.0 support

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: Bin Meng Message-Id: <20211210075704.23951-2-frank.ch...@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 2 +- target/riscv/cpu.c | 16 ---

[PULL 10/88] target/riscv: Use FIELD_EX32() to extract wd field

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-Id: <20211210075704.23951-3-frank.ch...@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/vector_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff -

[PULL 14/88] target/riscv: rvv-1.0: introduce writable misa.v field

From: Frank Chang Implementations may have a writable misa.v field. Analogous to the way in which the floating-point unit is handled, the mstatus.vs field may exist even if misa.v is clear. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-Id: <20

[PULL 08/88] target/riscv: zfh: add Zfhmin cpu property

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Alistair Francis Message-id: 20211210074329.5775-9-frank.ch...@sifive.com Signed-off-by: Alistair Francis --- target/riscv/cpu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 0f808a5b

[PULL 12/88] target/riscv: rvv-1.0: set mstatus.SD bit if mstatus.VS is dirty

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-Id: <20211210075704.23951-5-frank.ch...@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/csr.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/csr.c

[PULL 11/88] target/riscv: rvv-1.0: add mstatus VS field

From: LIU Zhiwei Signed-off-by: LIU Zhiwei Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-Id: <20211210075704.23951-4-frank.ch...@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.h| 2 ++ target/riscv/cpu_bits.h |

[PULL 21/88] target/riscv: rvv-1.0: add fractional LMUL

From: Frank Chang Introduce the concepts of fractional LMUL for RVV 1.0. In RVV 1.0, LMUL bits are contiguous in vtype register. Also rearrange rvv bits in TB_FLAGS to skip MSTATUS_VS (0x600) and MSTATUS_FS (0x6000) bits. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by:

[PULL 17/88] target/riscv: rvv-1.0: add vcsr register

From: LIU Zhiwei Signed-off-by: LIU Zhiwei Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-Id: <20211210075704.23951-10-frank.ch...@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/cpu_bits.h | 7 +++ target/riscv/csr.c |

[PULL 27/88] target/riscv: rvv-1.0: configure instructions

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-Id: <20211210075704.23951-20-frank.ch...@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/vector_helper.c| 14 +- target/riscv/insn_trans/trans_rvv.c.

[PULL 13/88] target/riscv: rvv-1.0: add sstatus VS field

From: LIU Zhiwei Signed-off-by: LIU Zhiwei Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-Id: <20211210075704.23951-6-frank.ch...@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/cpu_bits.h | 1 + target/riscv/csr.c | 2 +- 2

[PULL 18/88] target/riscv: rvv-1.0: add vlenb register

From: Greentime Hu Signed-off-by: Greentime Hu Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-Id: <20211210075704.23951-11-frank.ch...@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/cpu_bits.h | 1 + target/riscv/csr.c | 7

[PULL 16/88] target/riscv: rvv-1.0: remove rvv related codes from fcsr registers

From: Frank Chang * Remove VXRM and VXSAT fields from FCSR register as they are only presented in VCSR register. * Remove RVV loose check in fs() predicate function. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-Id: <20211210075704.23951-9-f

[PULL 32/88] target/riscv: rvv-1.0: load/store whole register instructions

From: Frank Chang Add the following instructions: * vlre.v * vsr.v Signed-off-by: Frank Chang Reviewed-by: Alistair Francis Message-Id: <20211210075704.23951-25-frank.ch...@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/helper.h | 21 target/riscv/in

[PULL 25/88] target/riscv: rvv:1.0: add translation-time nan-box helper function

From: Frank Chang * Add fp16 nan-box check generator function, if a 16-bit input is not properly nanboxed, then the input is replaced with the default qnan. * Add do_nanbox() helper function to utilize gen_check_nanbox_X() to generate the NaN-boxed floating-point values based on SEW setting.

[PULL 19/88] target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr registers

From: Frank Chang If VS field is off, accessing vector csr registers should raise an illegal-instruction exception. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-Id: <20211210075704.23951-12-frank.ch...@sifive.com> Signed-off-by: Alistair Fran

[PULL 15/88] target/riscv: rvv-1.0: add translation-time vector context status

From: Frank Chang Signed-off-by: LIU Zhiwei Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-Id: <20211210075704.23951-8-frank.ch...@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 5 +- target/riscv/c

[PULL 26/88] target/riscv: rvv-1.0: remove amo operations instructions

From: Frank Chang Vector AMOs are removed from standard vector extensions. Will be added later as separate Zvamo extension, but will need a different encoding from earlier proposal. Signed-off-by: Frank Chang Reviewed-by: Alistair Francis Message-Id: <20211210075704.23951-19-frank.ch...@sifive

[PULL 23/88] target/riscv: rvv-1.0: update check functions

From: Frank Chang Update check functions with RVV 1.0 rules. Signed-off-by: Frank Chang Reviewed-by: Alistair Francis Message-Id: <20211210075704.23951-16-frank.ch...@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/insn_trans/trans_rvv.c.inc | 715 +--- 1 fil

[PULL 36/88] target/riscv: rvv-1.0: floating-point classify instructions

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-Id: <20211210075704.23951-29-frank.ch...@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/insn32.decode | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --

[PULL 20/88] target/riscv: rvv-1.0: remove MLEN calculations

From: Frank Chang As in RVV 1.0 design, MLEN is hardcoded with value 1 (Section 4.5). Thus, remove all MLEN related calculations. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-Id: <20211210075704.23951-13-frank.ch...@sifive.com> Signed-off-by:

[PULL 28/88] target/riscv: rvv-1.0: stride load and store instructions

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Alistair Francis Message-Id: <20211210075704.23951-21-frank.ch...@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/helper.h | 129 ++-- target/riscv/insn32.decode | 43 ++- target/riscv/v

[PULL 24/88] target/riscv: introduce more imm value modes in translator functions

From: Frank Chang Immediate value in translator function is extended not only zero-extended and sign-extended but with more modes to be applicable with multiple formats of vector instructions. * IMM_ZX: Zero-extended * IMM_SX: Sign-extended * IMM_TRUNC_SEW: Truncate to log(SEW)

[PULL 43/88] target/riscv: rvv-1.0: register gather instructions

From: Frank Chang * Add vrgatherei16.vv instruction. Signed-off-by: Frank Chang Reviewed-by: Alistair Francis Message-Id: <20211210075704.23951-36-frank.ch...@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/helper.h | 4 target/riscv/insn32.decode

[PULL 29/88] target/riscv: rvv-1.0: index load and store instructions

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Alistair Francis Message-Id: <20211210075704.23951-22-frank.ch...@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/helper.h | 67 +++ target/riscv/insn32.decode | 21 +++-- targe

[PULL 39/88] target/riscv: rvv-1.0: set-X-first mask bit instructions

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-Id: <20211210075704.23951-32-frank.ch...@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/insn32.decode | 6 +++--- target/riscv/vector_helper.c

[PULL 30/88] target/riscv: rvv-1.0: fix address index overflow bug of indexed load/store insns

From: Frank Chang Replace ETYPE from signed int to unsigned int to prevent index overflow issue, which would lead to wrong index address. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-Id: <20211210075704.23951-23-frank.ch...@sifive.com> Signed

[PULL 47/88] target/riscv: rvv-1.0: whole register move instructions

From: Frank Chang Add the following instructions: * vmv1r.v * vmv2r.v * vmv4r.v * vmv8r.v Signed-off-by: Frank Chang Acked-by: Alistair Francis Message-Id: <20211210075704.23951-40-frank.ch...@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/insn32.decode | 4

[PULL 44/88] target/riscv: rvv-1.0: integer scalar move instructions

From: Frank Chang * Remove "vmv.s.x: dothing if rs1 == 0" constraint. * Add vmv.x.s instruction. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Acked-by: Alistair Francis Message-Id: <20211210075704.23951-37-frank.ch...@sifive.com> Signed-off-by: Alistair Francis --- target/riscv

[PULL 34/88] target/riscv: rvv-1.0: take fractional LMUL into vector max elements calculation

From: Frank Chang Update vext_get_vlmax() and MAXSZ() to take fractional LMUL into calculation for RVV 1.0. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-Id: <20211210075704.23951-27-frank.ch...@sifive.com> Signed-off-by: Alistair Francis ---

[PULL 31/88] target/riscv: rvv-1.0: fault-only-first unit stride load

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-Id: <20211210075704.23951-24-frank.ch...@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/helper.h | 26 ++--- target/riscv/insn32.decode

[PULL 51/88] target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrow

From: Frank Chang * Only do carry-in or borrow-in if is masked (vm=0). * Remove clear function from helper functions as the tail elements are unchanged in RVV 1.0. Signed-off-by: Frank Chang Reviewed-by: Alistair Francis Message-Id: <20211210075704.23951-44-frank.ch...@sifive.com> Signed-off

[PULL 50/88] target/riscv: rvv-1.0: single-width bit shift instructions

From: Frank Chang Truncate vsll.vi, vsrl.vi, vsra.vi's immediate values to lg2(SEW) bits. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Message-Id: <20211210075704.23951-43-frank.ch...@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/insn_trans/trans_rvv.c.inc | 6 +++

[PULL 35/88] target/riscv: rvv-1.0: floating-point square-root instruction

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-Id: <20211210075704.23951-28-frank.ch...@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/insn32.decode | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --

[PULL 33/88] target/riscv: rvv-1.0: update vext_max_elems() for load/store insns

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Alistair Francis Message-Id: <20211210075704.23951-26-frank.ch...@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/vector_helper.c| 99 ++--- target/riscv/insn_trans/trans_rvv.c.inc | 32

[PULL 58/88] target/riscv: rvv-1.0: slide instructions

From: Frank Chang * Remove clear function from helper functions as the tail elements are unchanged in RVV 1.0. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Message-Id: <20211210075704.23951-51-frank.ch...@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/vector_help

[PULL 41/88] target/riscv: rvv-1.0: element index instruction

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-Id: <20211210075704.23951-34-frank.ch...@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/insn32.decode | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --

[PULL 37/88] target/riscv: rvv-1.0: count population in mask instruction

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-Id: <20211210075704.23951-30-frank.ch...@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/helper.h | 2 +- target/riscv/insn32.decode |

[PULL 53/88] target/riscv: rvv-1.0: widening integer multiply-add instructions

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Message-Id: <20211210075704.23951-46-frank.ch...@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/insn32.decode | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/target/riscv/insn32

[PULL 75/88] target/riscv: rvv-1.0: trigger illegal instruction exception if frm is not valid

From: Frank Chang If the frm field contains an invalid rounding mode (101-111), attempting to execute any vector floating-point instruction, even those that do not depend on the rounding mode, will raise an illegal instruction exception. Call gen_set_rm() with DYN rounding mode to check and trig

[PULL 46/88] target/riscv: rvv-1.0: floating-point scalar move instructions

From: Frank Chang NaN-boxed the scalar floating-point register based on RVV 1.0's rules. Signed-off-by: Frank Chang Acked-by: Alistair Francis Message-Id: <20211210075704.23951-39-frank.ch...@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/internals.h| 5 t

[PULL 38/88] target/riscv: rvv-1.0: find-first-set mask bit instruction

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-Id: <20211210075704.23951-31-frank.ch...@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/helper.h | 2 +- target/riscv/insn32.decode |

[PULL 76/88] target/riscv: gdb: support vector registers for rv64 & rv32

From: Hsiangkai Wang Signed-off-by: Hsiangkai Wang Signed-off-by: Greentime Hu Signed-off-by: Frank Chang Acked-by: Alistair Francis Message-Id: <20211210075704.23951-69-frank.ch...@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 1 + target/riscv/cpu.c | 2

[PULL 55/88] target/riscv: rvv-1.0: integer comparison instructions

From: Frank Chang * Sign-extend vmselu.vi and vmsgtu.vi immediate values. * Remove "set tail elements to zeros" as tail elements can be unchanged for either VTA to have undisturbed or agnostic setting. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Message-Id: <20211210075704.2395

[PULL 52/88] target/riscv: rvv-1.0: narrowing integer right shift instructions

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Message-Id: <20211210075704.23951-45-frank.ch...@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/helper.h | 24 +++--- target/riscv/insn32.decode | 12 +++ targe

[PULL 40/88] target/riscv: rvv-1.0: iota instruction

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-Id: <20211210075704.23951-33-frank.ch...@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/insn32.decode | 2 +- target/riscv/insn_trans/trans_rvv.c.inc

[PULL 78/88] target/riscv: rvv-1.0: floating-point reciprocal estimate instruction

From: Frank Chang Implement the floating-point reciprocal estimate to 7 bits instruction. Signed-off-by: Frank Chang Acked-by: Alistair Francis Message-Id: <20211210075704.23951-71-frank.ch...@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/helper.h | 4 + ta

[PULL 57/88] target/riscv: rvv-1.0: mask-register logical instructions

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Message-Id: <20211210075704.23951-50-frank.ch...@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/vector_helper.c| 4 target/riscv/insn_trans/trans_rvv.c.inc | 3 ++- 2 files changed, 2 in

[PULL 56/88] target/riscv: rvv-1.0: floating-point compare instructions

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Message-Id: <20211210075704.23951-49-frank.ch...@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/vector_helper.c | 9 - 1 file changed, 9 deletions(-) diff --git a/target/riscv/vector_helper.c b/

[PULL 42/88] target/riscv: rvv-1.0: allow load element with sign-extended

From: Frank Chang For some vector instructions (e.g. vmv.s.x), the element is loaded with sign-extended. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-Id: <20211210075704.23951-35-frank.ch...@sifive.com> Signed-off-by: Alistair Francis --- t

[PULL 80/88] target/riscv: rvv-1.0: add vsetivli instruction

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Alistair Francis Message-Id: <20211210075704.23951-73-frank.ch...@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/insn32.decode | 2 ++ target/riscv/insn_trans/trans_rvv.c.inc | 27 +

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