On 12/14/21 15:44, matheus.fe...@eldorado.org.br wrote:
From: Matheus Ferst
The non-signalling versions of VSX scalar convert to shorter/longer
precision insns doesn't silence SNaNs in the hardware. To better match
this behavior, use the non-arithmatic conversion of helper_todouble
instead of f
From: "Lucas Mateus Castro (alqotel)"
Added tests for the mtfsf to check if FI bit of FPSCR is being set
and if exception calls are being made correctly.
Reviewed-by: Richard Henderson
Signed-off-by: Lucas Mateus Castro (alqotel)
Message-Id: <20211201163808.440385-3-lucas.ara...@eldorado.org.b
From: Richard Henderson
PowerPC has this flag, and it's easier to compute it here
than after the fact.
Signed-off-by: Richard Henderson
Message-Id: <2029160502.17432-4-richard.hender...@linaro.org>
Signed-off-by: Cédric Le Goater
---
include/fpu/softfloat-types.h | 1 +
fpu/softfloat-pa
From: Matheus Ferst
Implement the following PowerISA v3.1 instructions:
mtvsrbm: Move to VSR Byte Mask
mtvsrhm: Move to VSR Halfword Mask
mtvsrwm: Move to VSR Word Mask
mtvsrdm: Move to VSR Doubleword Mask
mtvsrqm: Move to VSR Quadword Mask
mtvsrbmi: Move to VSR Byte Mask Immediate
Reviewed-by:
The following changes since commit 76b56fdfc9fa43ec6e5986aee33f108c6c6a511e:
Merge tag 'block-pull-request' of https://gitlab.com/stefanha/qemu into
staging (2021-12-14 12:46:18 -0800)
are available in the Git repository at:
https://github.com/legoater/qemu/ tags/pull-ppc-2021121
From: Richard Henderson
Now that vximz, vxisi, and vxsnan are computed directly by
softfloat, we don't need to recompute it. This replaces the
separate float{32,64}_maddsub_update_excp functions with a
single float_invalid_op_madd function.
Fix VSX_MADD by passing sfprf to float_invalid_op_madd
From: "Lucas Mateus Castro (alqotel)"
This commit fixes the difference reported in the bug in the reserved
bit 52, it does this by adding this bit to the mask of bits to not be
directly altered in the ppc_store_fpscr function (the hardware used to
compare to QEMU was a Power9).
The bits 0 to 27
From: Daniel Henrique Barboza
Put in a more accessible place the reasoning behind our decision
to officially drop KVM support in the powernv machine.
Signed-off-by: Daniel Henrique Barboza
Message-Id: <20211130133153.444601-3-danielhb...@gmail.com>
Signed-off-by: Cédric Le Goater
---
docs/sys
From: Leonardo Garcia
Signed-off-by: Leonardo Garcia
Reviewed-by: Daniel Henrique Barboza
Message-Id:
<7d3c8bad1ca76eb13d6ce2b16dd9a821edcdb27b.1638982486.git.lagar...@br.ibm.com>
Signed-off-by: Cédric Le Goater
---
docs/system/ppc/pseries.rst | 2 +-
1 file changed, 1 insertion(+), 1 deleti
From: Richard Henderson
Use float_flag_invalid_snan instead of recomputing
the snan-ness of the operand.
Signed-off-by: Richard Henderson
Message-Id: <2029160502.17432-26-richard.hender...@linaro.org>
Signed-off-by: Cédric Le Goater
---
target/ppc/fpu_helper.c | 15 +--
1 file
From: Leonardo Garcia
Signed-off-by: Leonardo Garcia
Reviewed-by: Daniel Henrique Barboza
Message-Id:
<7f13e40e05ddb411697b0777b0e37757f76905e9.1638982486.git.lagar...@br.ibm.com>
Signed-off-by: Cédric Le Goater
---
docs/specs/{ppc-spapr-hcalls.txt => ppc-spapr-hcalls.rst} | 0
1 file change
From: Peter Maydell
The mac.h header defines a MAX_CPUS macro. This is confusingly named,
because it suggests it's a generic setting, but in fact it's used
by only the g3beige and mac99 machines. It's also using a single
macro for two values which aren't inherently the same -- if one
of these two
From: Richard Henderson
Now that vxisi and vxsnan are computed directly by
softfloat, we don't need to recompute it via classes.
Signed-off-by: Richard Henderson
Message-Id: <2029160502.17432-9-richard.hender...@linaro.org>
Signed-off-by: Cédric Le Goater
---
target/ppc/fpu_helper.c | 38
From: Richard Henderson
Let float64_round_to_int detect and silence snans.
Signed-off-by: Richard Henderson
Message-Id: <2029160502.17432-18-richard.hender...@linaro.org>
Signed-off-by: Cédric Le Goater
---
target/ppc/fpu_helper.c | 24 +++-
1 file changed, 11 insertio
From: Daniel Henrique Barboza
Setting -uuid in the pnv machine does not work:
./qemu-system-ppc64 -machine powernv8,accel=tcg -uuid
7ff61ca1-a4a0-4bc1-944c-abd114a35e80
qemu-system-ppc64: error creating device tree: (fdt_property_string(fdt,
"system-id", buf)): FDT_ERR_BADSTATE
This happens
From: Leonardo Garcia
Signed-off-by: Leonardo Garcia
Reviewed-by: Daniel Henrique Barboza
[ clg: replaced lingua by terminology ]
Message-Id:
Signed-off-by: Cédric Le Goater
---
docs/specs/ppc-spapr-hcalls.txt | 92 -
1 file changed, 57 insertions(+), 35 dele
From: Richard Henderson
Use float64r32_mul. Fixes a double-rounding issue with performing
the compuation in float64 and then rounding afterward.
Signed-off-by: Richard Henderson
Message-Id: <2029160502.17432-32-richard.hender...@linaro.org>
Signed-off-by: Cédric Le Goater
---
target/ppc/
From: Richard Henderson
PowerPC has this flag, and it's easier to compute it here
than after the fact.
Signed-off-by: Richard Henderson
Message-Id: <2029160502.17432-3-richard.hender...@linaro.org>
Signed-off-by: Cédric Le Goater
---
include/fpu/softfloat-types.h | 1 +
fpu/softfloat-part
From: Richard Henderson
We will shortly have more than 8 bits of exceptions.
Repack the existing flags into low bits and reformat to hex.
Signed-off-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <2029160502.17432-2-richard.hender...@linaro.org>
Signed-off-by: Cédric
From: Richard Henderson
PowerPC has this flag, and it's easier to compute it here
than after the fact.
Signed-off-by: Richard Henderson
Message-Id: <2029160502.17432-8-richard.hender...@linaro.org>
Signed-off-by: Cédric Le Goater
---
include/fpu/softfloat-types.h | 1 +
fpu/softfloat.c
From: Leonardo Garcia
The purpose of this document is to substitute the content currently
available in the QEMU wiki at [0]. This initial version does contain
some additional content as well. Whenever this documentation gets
upstream and is reflected in [1], the QEMU wiki will be edited to point
From: Richard Henderson
In GEN_FLOAT_B, we called helper_reset_fpstatus immediately
before calling helper_fri*. Therefore get_float_exception_flags
is known to be zero, and this code can be simplified.
Signed-off-by: Richard Henderson
Message-Id: <2029160502.17432-17-richard.hender...@lina
From: Richard Henderson
Use float64r32_muladd. Fixes a double-rounding issue with performing
the compuation in float64 and then rounding afterward.
Signed-off-by: Richard Henderson
Message-Id: <2029160502.17432-29-richard.hender...@linaro.org>
Signed-off-by: Cédric Le Goater
---
target/p
From: Richard Henderson
PowerPC has this flag, and it's easier to compute it here
than after the fact.
Signed-off-by: Richard Henderson
Message-Id: <2029160502.17432-7-richard.hender...@linaro.org>
Signed-off-by: Cédric Le Goater
---
include/fpu/softfloat-types.h | 1 +
fpu/softfloat-par
From: Richard Henderson
Now that vxsnan is computed directly by softfloat,
we don't need to recompute it via classes.
Signed-off-by: Richard Henderson
Message-Id: <2029160502.17432-13-richard.hender...@linaro.org>
Signed-off-by: Cédric Le Goater
---
target/ppc/fpu_helper.c | 20 ++
From: Richard Henderson
PowerPC has these flags, and it's easier to compute them here
than after the fact.
Signed-off-by: Richard Henderson
Message-Id: <2029160502.17432-5-richard.hender...@linaro.org>
Signed-off-by: Cédric Le Goater
---
include/fpu/softfloat-types.h | 2 ++
fpu/softfloa
From: Fabiano Rosas
The 603e uses the same exception code as 603 so we don't need a
dedicated entry for it.
This is only a removal of redundant code, no functional change.
Signed-off-by: Fabiano Rosas
Reviewed-by: Richard Henderson
Reviewed-by: Cédric Le Goater
Message-Id: <20211208123029.20
From: Daniel Henrique Barboza
If one tries to use -machine powernv9,accel=kvm in a Power9 host, a
cryptic error will be shown:
qemu-system-ppc64: Register sync failed... If you're using kvm-hv.ko, only
"-cpu host" is possible
qemu-system-ppc64: kvm_init_vcpu: kvm_arch_init_vcpu failed (0): Inva
From: Richard Henderson
PowerPC has this flag, and it's easier to compute it here
than after the fact.
Signed-off-by: Richard Henderson
Message-Id: <2029160502.17432-6-richard.hender...@linaro.org>
Signed-off-by: Cédric Le Goater
---
include/fpu/softfloat-types.h | 1 +
fpu/softfloat-part
From: Richard Henderson
We were returning nanval for any instance of invalid being set,
but that is an incorrect for VXCVI. This failure can be seen
in the float_convs tests.
Signed-off-by: Richard Henderson
Message-Id: <2029160502.17432-14-richard.hender...@linaro.org>
Signed-off-by: Cédr
They have been there since 2007 without any board using them, most
were protected by a TODO define. Drop support.
Signed-off-by: Cédric Le Goater
Reviewed-by: Richard Henderson
Reviewed-by: David Gibson
Reviewed-by: Daniel Henrique Barboza
Message-Id: <20211202191108.1291515-1-...@kaod.org>
Si
From: Richard Henderson
We will process flags other than in valid in helper_float_check_status,
which is invoked after the writeback to FRT.
Fixes a bug in which FRT is not written when OE/UE/XE are enabled.
Signed-off-by: Richard Henderson
Message-Id: <2029160502.17432-21-richard.hender...
From: Richard Henderson
Now that vxsnan is computed directly by softfloat,
we don't need to recompute it.
Signed-off-by: Richard Henderson
Message-Id: <2029160502.17432-23-richard.hender...@linaro.org>
Signed-off-by: Cédric Le Goater
---
target/ppc/fpu_helper.c | 13 -
1 file
From: Richard Henderson
Now that vximz and vxsnan are computed directly by
softfloat, we don't need to recompute it via classes.
Signed-off-by: Richard Henderson
Message-Id: <2029160502.17432-10-richard.hender...@linaro.org>
Signed-off-by: Cédric Le Goater
---
target/ppc/fpu_helper.c | 26
From: Thomas Huth
The PPC 405 CPU is a system-on-a-chip, so all 405 machines are very similar,
except for some external periphery. However, the periphery of the 'taihu'
machine is hardly emulated at all (e.g. neither the LCD nor the USB part had
been implemented), so there is not much value added
From: Richard Henderson
These variants take a float64 as input, compute the result to
infinite precision (as we do with FloatParts), round the result
to the precision and dynamic range of float32, and then return
the result in the format of float64.
This is the operation PowerPC requires for its
From: Richard Henderson
This is the proper type for the enumeration.
Signed-off-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <2029160502.17432-16-richard.hender...@linaro.org>
Signed-off-by: Cédric Le Goater
---
target/ppc/fpu_helper.c | 2 +-
1 file changed, 1 i
From: Richard Henderson
Calling helper_frsp directly from other helpers generates
the incorrect retaddr. Split out a helper that takes the
retaddr as a parameter.
Signed-off-by: Richard Henderson
Message-Id: <2029160502.17432-22-richard.hender...@linaro.org>
Signed-off-by: Cédric Le Goater
I will be useful to rework the boot from Linux.
Signed-off-by: Cédric Le Goater
Message-Id: <20211206103712.1866296-7-...@kaod.org>
Signed-off-by: Cédric Le Goater
---
hw/ppc/ppc405.h| 2 +-
hw/ppc/ppc405_boards.c | 6 +-
hw/ppc/ppc405_uc.c | 4 ++--
3 files changed, 8 insertion
From: Richard Henderson
Use float_flag_invalid_snan instead of recomputing
the snan-ness of the operand.
Signed-off-by: Richard Henderson
Message-Id: <2029160502.17432-27-richard.hender...@linaro.org>
Signed-off-by: Cédric Le Goater
---
target/ppc/fpu_helper.c | 21 -
From: Richard Henderson
Now that vxidi, vxzdz, and vxsnan are computed directly by
softfloat, we don't need to recompute it via classes.
Signed-off-by: Richard Henderson
Message-Id: <2029160502.17432-11-richard.hender...@linaro.org>
Signed-off-by: Cédric Le Goater
---
target/ppc/fpu_helpe
From: Richard Henderson
Create a common function for all of the madd helpers.
Let the compiler tail call or inline as it chooses.
Signed-off-by: Richard Henderson
Message-Id: <2029160502.17432-20-richard.hender...@linaro.org>
Signed-off-by: Cédric Le Goater
---
target/ppc/fpu_helper.c | 3
It is currently impossible to find a "ppc405_rom.bin" firmware file or
a full flash image for the PPC405EP evalution board. Even if it should
be technically possible to recreate such an image, it's unlikely that
anyone will do it since the board is obsolete and support in QEMU has
been broken for a
From: Fabiano Rosas
The exception model id for 601v has been removed without mention
why. I assume it was inadvertent and restore it here.
Fixes: b632a148b6 ("target-ppc: Use QOM method dispatch for MMU fault handling")
Signed-off-by: Fabiano Rosas
Reviewed-by: Richard Henderson
Reviewed-by: C
From: Richard Henderson
Fixes a bug in which e.g XE enabled causes inexact to be raised
before the writeback to the architectural register.
All of the users of GEN_FLOAT_B either set set_fprf, or are one
of the convert-to-integer instructions that require this behaviour.
Split out the two gen_he
From: Richard Henderson
There is no double-rounding bug here, because the result is
merely an estimate to within 1 part in 256, but perform the
operation with float64r32_div for consistency.
Use float_flag_invalid_snan instead of recomputing the
snan-ness of the operand.
Signed-off-by: Richard
From: Victor Colombo
PPC instruction xsmaxcdp, xsmincdp, xsmaxjdp, and xsminjdp are using
vector registers when they should be using VSX ones. This happens
because the instructions are using GEN_VSX_HELPER_R3, which adds 32
to the register numbers, effectively making them vector registers.
This
From: Richard Henderson
There's no reason the callers can't tail call to one function.
Leave it up to the compiler either way.
Signed-off-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <2029160502.17432-15-richard.hender...@linaro.org>
Signed-off-by: Cédric Le Goater
Signed-off-by: Cédric Le Goater
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20211206103712.1866296-4-...@kaod.org>
Signed-off-by: Cédric Le Goater
---
hw/ppc/ppc.c| 2 ++
hw/ppc/trace-events | 3 +++
2 files changed, 5 insertions(+)
diff --git a/hw/ppc/ppc.c b/hw/ppc/ppc.c
index e
From: Fabiano Rosas
The e600 CPU is a successor of the 7448 and like all the 7450s CPUs,
it has an optional software TLB feature.
We have determined that there is no OS software support for the 7450
software TLB available these days. See the previous commit for more
information.
This patch disa
QEMU installs a custom U-Boot in-memory descriptor to share board
information with Linux, which means that the QEMU machine was
initially designed to support booting Linux directly without using the
loaded FW. But, it's not that simple because the CPU still starts at
address 0xfffc where nothin
From: Fabiano Rosas
The Floating-point Unavailable and Decrementer interrupts are being
registered at the same 0x900 address. The FPU should be at 0x800
instead.
Verified on MPC555, MPC860 and MPC885 user manuals.
Reported-by: BALATON Zoltan
Signed-off-by: Fabiano Rosas
Reviewed-by: Richard H
From: Richard Henderson
Now that vxsqrt and vxsnan are computed directly by softfloat,
we don't need to recompute it. Split out float_invalid_op_sqrt
to be used in several places. This fixes VSX_SQRT, which did
not order its tests correctly to eliminate NaN with sign set.
Signed-off-by: Richar
The machine can already boot with kernel and initrd U-boot images if a
firmware is loaded first. Adapt and improve the load sequence to let
the machine boot directly from a Linux kernel ELF image and a usual
initrd image if a firmware image is not provided. For that, install a
custom CPU reset hand
From: Richard Henderson
We only needed one ieee arithmetic operation to raise
exceptions. To convert back to register form, we can
use our simpler non-arithmetic function.
Signed-off-by: Richard Henderson
Message-Id: <2029160502.17432-24-richard.hender...@linaro.org>
Signed-off-by: Cédric
From: Richard Henderson
There is no double-rounding bug here, because the result is
merely an estimate to within 1 part in 32, but perform the
operation with float64r32_div for consistency.
Signed-off-by: Richard Henderson
Message-Id: <2029160502.17432-33-richard.hender...@linaro.org>
Signe
This routine is a small helper to cleanup the code. The update of the
flash fields were removed because there are not of any use when booting
from a Linux kernel image. It should be functionally equivalent.
Signed-off-by: Cédric Le Goater
Message-Id: <20211206103712.1866296-11-...@kaod.org>
Signe
From: Richard Henderson
Use float64r32_{add,sub,div}. Fixes a double-rounding issue with
performing the compuation in float64 and then rounding afterward.
Signed-off-by: Richard Henderson
Message-Id: <2029160502.17432-31-richard.hender...@linaro.org>
Signed-off-by: Cédric Le Goater
---
t
From: Daniel Henrique Barboza
This patch starts an IBM Power8+ compatible PMU implementation by adding
the representation of PMU events that we are going to sample,
PMUEventType. This enum represents a Perf event that is being sampled by
a specific counter 'sprn'. Events that aren't available (i.
It was introduced in commit b8d3f5d12642 ("Add flags to support
PowerPC 405 bootinfos variations.") but since its value has always
been set to '1'.
Signed-off-by: Cédric Le Goater
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20211206103712.1866296-6-...@kaod.org>
Signed-off-by: Cédric Le Goa
From: Richard Henderson
When computing the predicate "is this value currently formatted
for single precision", we do not want to round the value according
to the current rounding mode, nor perform a floating-point equality.
We want to see if the N bits that make up single-precision are the
only o
and one error message to a LOG_GUEST_ERROR.
Signed-off-by: Cédric Le Goater
Message-Id: <20211206103712.1866296-5-...@kaod.org>
Signed-off-by: Cédric Le Goater
---
hw/ppc/ppc405_uc.c | 159 +++-
hw/ppc/trace-events | 20 ++
2 files changed, 74 inser
These values are computed and updated by U-Boot at startup. Use them
as defaults to improve direct Linux boot.
Signed-off-by: Cédric Le Goater
Message-Id: <20211206103712.1866296-13-...@kaod.org>
Signed-off-by: Cédric Le Goater
---
hw/ppc/ppc405_uc.c | 6 +++---
1 file changed, 3 insertions(+),
From: Richard Henderson
Use float64r32_sqrt. Fixes a double-rounding issue with performing
the compuation in float64 and then rounding afterward.
Signed-off-by: Richard Henderson
Message-Id: <2029160502.17432-30-richard.hender...@linaro.org>
Signed-off-by: Cédric Le Goater
---
target/ppc
When -nodefaults is supported for PHB3 devices, the phbs array under
the chip will be empty. This will break the XICSFabric handlers, and
all interrupt delivery, and the 'info pic' HMP command.
Do a QOM loop on the chip children and look for PHB3 devices instead.
Signed-off-by: Cédric Le Goater
The maximum number of PHB3 devices per chip can be different depending
on the POWER8 processor model.
Signed-off-by: Cédric Le Goater
Reviewed-by: Daniel Henrique Barboza
Message-Id: <20211213132830.108372-4-...@kaod.org>
Signed-off-by: Cédric Le Goater
---
hw/pci-host/pnv_phb3.c | 2 +-
1 fil
The board information for the 405EP first appeared in commit 04f20795ac81
("Move PowerPC 405 specific definitions into a separate file ...")
An Ethernet address is a 6 byte number. Fix that.
Signed-off-by: Cédric Le Goater
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20211206103712.1866296-1
From: Fabiano Rosas
(Applies to 7441, 7445, 7450, 7451, 7455, 7457, 7447, 7447a and 7448)
The QEMU-side software TLB implementation for the 7450 family of CPUs
is being removed due to lack of known users in the real world. The
last users in the code were removed by the two previous commits.
A b
From: Daniel Henrique Barboza
MMCR1 determines the events to be sampled by the PMU. Updating the
counters at every MMCR1 write ensures that we're not sampling more
or less events by looking only at MMCR0 and the PMCs.
It is worth noticing that both the Book3S PowerPC PMU, and this IBM
Power8+ PM
Adapt the fields offset in the board information for Linux. Since
Linux relies on the CPU frequency value, I wonder how it ever worked.
Signed-off-by: Cédric Le Goater
Message-Id: <20211206103712.1866296-15-...@kaod.org>
Signed-off-by: Cédric Le Goater
---
hw/ppc/ppc405_uc.c | 9 +
1 fi
From: Fabiano Rosas
(Applies to 7441, 7445, 7450, 7451, 7455, 7457, 7447 and 7447a)*
We have since 2011 [1] been unable to run OpenBIOS in the 7450s and
have not heard of any other software that is used with those CPUs in
QEMU. A current discussion [2] shows that the 7450 software TLB is
unsuppo
The default addresses to load the kernel, fdt, initrd of AMCC boards
in U-Boot v2015.10 are :
"kernel_addr_r=100\0"
"fdt_addr_r=180\0"
"ramdisk_addr_r=190\0"
The taihu is one of these boards, the ref405ep is not but we don't
have much information on it and both
Add 6.2 machine types for arm/i440fx/q35/s390x/spapr.
Shameless copy of commit
52e64f5b1f2c81472b57dbad255ab9b00302f10d
from
Yanan Wang
Signed-off-by: Juan Quintela
---
include/hw/boards.h| 3 +++
include/hw/i386/pc.h | 3 +++
hw/arm/virt.c | 11 +++
From: Matheus Ferst
The non-signalling versions of VSX scalar convert to shorter/longer
precision insns doesn't silence SNaNs in the hardware. To better match
this behavior, use the non-arithmetic conversion of helper_todouble
instead of float32_to_float64. A test is added to prevent future
regre
Signed-off-by: Cédric Le Goater
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20211206103712.1866296-8-...@kaod.org>
Signed-off-by: Cédric Le Goater
---
hw/ppc/ppc405.h| 7 +++
hw/ppc/ppc405_boards.c | 16 +++-
2 files changed, 14 insertions(+), 9 deletions(-)
diff
From: Victor Colombo
Reviewed-by: Richard Henderson
Signed-off-by: Victor Colombo
Message-Id: <20211213120958.24443-3-victor.colo...@eldorado.org.br>
Signed-off-by: Cédric Le Goater
---
target/ppc/insn32.decode| 17 +---
target/ppc/translate/vsx-impl.c.inc | 30 +++
From: Matheus Ferst
Reviewed-by: Richard Henderson
Signed-off-by: Matheus Ferst
Message-Id: <20211213120958.24443-5-victor.colo...@eldorado.org.br>
Signed-off-by: Cédric Le Goater
---
target/ppc/helper.h | 2 +-
target/ppc/insn32.decode| 4
target/ppc/fpu_he
On 15/12/2021 13:53, Cédric Le Goater wrote:
On 12/14/21 15:44, matheus.fe...@eldorado.org.br wrote:
From: Matheus Ferst
The non-signalling versions of VSX scalar convert to shorter/longer
precision insns doesn't silence SNaNs in the hardware. To better match
this behavior, use the non-arithma
From: Fabiano Rosas
This reverts commit 336e91f85332dda0ede4c1d15b87a19a0fb898a2.
It breaks the --disable-tcg build:
../target/ppc/excp_helper.c:463:29: error: implicit declaration of
function ‘cpu_ldl_code’ [-Werror=implicit-function-declaration]
We should not have TCG code in powerpc_excp
From: Fabiano Rosas
When Altivec support was added to the e6500 kernel in 2012[1], the
QEMU code was not changed, so we don't register the VPU/VPUA
exceptions for the e6500:
qemu: fatal: Raised an exception without defined vector 73
Note that the error message says 73, instead of 32, which is
From: Matheus Ferst
This instruction has VRT and VRB fields instead of T/TX and B/BX.
Reviewed-by: Richard Henderson
Signed-off-by: Matheus Ferst
Message-Id: <20211213120958.24443-4-victor.colo...@eldorado.org.br>
Signed-off-by: Cédric Le Goater
---
target/ppc/translate/vsx-impl.c.inc | 5 ++
From: Daniel Henrique Barboza
Calling pmu_update_cycles() on every PMC read/write operation ensures
that the values being fetched are up to date with the current PMU state.
In theory we can get away by just trapping PMCs reads, but we're going
to trap PMC writes to deal with counter overflow log
From: Daniel Henrique Barboza
The PowerISA v3.1 defines that if the proper bits are set (MMCR0_PMC1CE
for PMC1 and MMCR0_PMCjCE for the remaining PMCs), counter negative
conditions are enabled. This means that if the counter value overflows
(i.e. exceeds 0x8000) a performance monitor alert wi
From: Daniel Henrique Barboza
The PMU is already counting cycles by calculating time elapsed in
nanoseconds. Counting instructions is a different matter and requires
another approach.
This patch adds the capability of counting completed instructions (Perf
event PM_INST_CMPL) by counting the amou
Cornelia Huck wrote:
> Add 7.0 machine types for arm/i440fx/q35/s390x/spapr.
>
> Signed-off-by: Cornelia Huck
Reviewed-by: Juan Quintela
I did a similar one with 6.3 by error, I think we should get a script to
do this everytime that we increase the version number O:-)
Later, Juan.
This change will help us providing support for user created PHB4
devices.
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Cédric Le Goater
Message-Id: <20211213132830.108372-14-...@kaod.org>
Signed-off-by: Cédric Le Goater
---
hw/pci-host/pnv_phb4_pec.c | 34 ++-
From: Daniel Henrique Barboza
PM_RUN_INST_CMPL, instructions completed with the run latch set, is
the architected PowerISA v3.1 event defined with PMC4SEL = 0xFA.
Implement it by checking for the CTRL RUN bit before incrementing the
counter. To make this work properly we also need to force a new
On 12/15/21 4:51 AM, WANG Xuerui wrote:
Signed-off-by: WANG Xuerui
---
.../host/loongarch64/safe-syscall.inc.S | 90 +++
1 file changed, 90 insertions(+)
create mode 100644 common-user/host/loongarch64/safe-syscall.inc.S
Reviewed-by: Richard Henderson
r~
It is never used.
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Frederic Barrat
Signed-off-by: Cédric Le Goater
Message-Id: <20211213132830.108372-5-...@kaod.org>
Signed-off-by: Cédric Le Goater
---
hw/ppc/pnv.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.
This change will help us providing support for user created PHB3
devices.
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Frederic Barrat
Signed-off-by: Cédric Le Goater
Message-Id: <20211213132830.108372-6-...@kaod.org>
Signed-off-by: Cédric Le Goater
---
hw/pci-host/pnv_phb3_pbcq.c | 11 +
This is not useful and will be in the way for support of user created
PHB4 devices.
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Frederic Barrat
Signed-off-by: Cédric Le Goater
Message-Id: <20211213132830.108372-13-...@kaod.org>
Signed-off-by: Cédric Le Goater
---
hw/pci-host/pnv_phb4_pe
It prepares ground for PHB5 which has different values.
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Frederic Barrat
Signed-off-by: Cédric Le Goater
Message-Id: <20211213132830.108372-9-...@kaod.org>
Signed-off-by: Cédric Le Goater
---
include/hw/pci-host/pnv_phb4.h | 2 ++
hw/pci-host/p
From: Daniel Henrique Barboza
This patch adds the barebones of the PMU logic by enabling cycle
counting. The overall logic goes as follows:
- MMCR0 reg initial value is set to 0x8000 (MMCR0_FC set) to avoid
having to spin the PMU right at system init;
- to retrieve the events that are being
When -nodefaults is supported for PHB4 devices, the pecs array under
the chip will be empty. This will break the 'info pic' HMP command.
Do a QOM loop on the chip children and look for PEC PHB4 devices
instead.
Signed-off-by: Cédric Le Goater
Reviewed-by: Daniel Henrique Barboza
Message-Id: <20
And check the PEC index using the chip class.
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Frederic Barrat
Signed-off-by: Cédric Le Goater
Message-Id: <20211213132830.108372-10-...@kaod.org>
Signed-off-by: Cédric Le Goater
---
include/hw/pci-host/pnv_phb4.h | 2 ++
hw/pci-host/pnv_phb4_p
POWER9 processor comes with 3 PHB4 PEC (PCI Express Controller) and
each PEC can have several PHBs :
* PEC0 provides 1 PHB (PHB0)
* PEC1 provides 2 PHBs (PHB1 and PHB2)
* PEC2 provides 3 PHBs (PHB3, PHB4 and PHB5)
A num_pecs class attribute represents better the logic units of the
POWER9 c
This change will help us move the mapping of XSCOM regions under the
PHB3 realize routine, which will be necessary for user created PHB3
devices.
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Frederic Barrat
Signed-off-by: Cédric Le Goater
Message-Id: <20211213132830.108372-3-...@kaod.org>
Use the num_stacks class attribute to compute the PHB index depending
on the PEC index :
* PEC0 provides 1 PHB (PHB0)
* PEC1 provides 2 PHBs (PHB1 and PHB2)
* PEC2 provides 3 PHBs (PHB3, PHB4 and PHB5)
The routine pnv_pec_phb_offset() is a bit complex but it also prepares
ground for PHB5 w
Peter Maydell wrote:
> On Wed, 15 Dec 2021 at 17:06, Juan Quintela wrote:
>>
>> Add 6.2 machine types for arm/i440fx/q35/s390x/spapr.
>>
>> Shameless copy of commit
>> 52e64f5b1f2c81472b57dbad255ab9b00302f10d
>> from
>> Yanan Wang
>
>> +DEFINE_VIRT_MACHINE_AS_LATEST(6, 3)
>
> The
From: Daniel Henrique Barboza
An Event-Based Branch (EBB) allows applications to change the NIA when a
event-based exception occurs. Event-based exceptions are enabled by
setting the Branch Event Status and Control Register (BESCR). If the
event-based exception is enabled when the exception occur
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