On 12/3/2021 9:26 AM, Rao, Lei wrote:
On 12/2/2021 5:54 PM, Vladimir Sementsov-Ogievskiy wrote:
02.12.2021 11:53, Daniel P. Berrangé wrote:
On Thu, Dec 02, 2021 at 01:14:47PM +0800, Rao, Lei wrote:
Sorry, resending with correct indentation and quoting.
On 12/1/2021 10:27 PM, Vladimir Sem
On Sun, Dec 12, 2021 at 10:16 PM Philippe Mathieu-Daudé wrote:
> On 12/11/21 20:11, Peter Maydell wrote:
> > Currently the ITS code that reads and writes DTEs uses open-coded
> > shift-and-mask to assemble the various fields into the 64-bit DTE
> > word. The names of the macros used for mask and
13.12.2021 11:02, Rao, Lei wrote:
On 12/3/2021 9:26 AM, Rao, Lei wrote:
On 12/2/2021 5:54 PM, Vladimir Sementsov-Ogievskiy wrote:
02.12.2021 11:53, Daniel P. Berrangé wrote:
On Thu, Dec 02, 2021 at 01:14:47PM +0800, Rao, Lei wrote:
Sorry, resending with correct indentation and quoting.
O
On 10/12/2021 13.10, Daniel P. Berrangé wrote:
On Thu, Dec 09, 2021 at 11:31:24AM +0100, Thomas Huth wrote:
Cirrus-CI provides KVM in their Linux containers, so we can also run
our VM-based NetBSD and OpenBSD build jobs there.
Since the VM installation might take a while, we only run the "help"
Peter Xu wrote:
> On Thu, Dec 02, 2021 at 06:38:27PM +0100, Juan Quintela wrote:
>> This needs to be improved to be compatible with old versions.
>
> Any plan to let new binary work with old binary?
Yes, but I was waiting for 7.0 to get out. Basically I need to do:
if (old)
run the old code
On 03/12/2021 15.27, Matthew Rosato wrote:
A collection of small fixes for s390x PCI (not urgent). The first 3 are
fixes related to always using the host-provided CLP value when provided
vs a hard-coded value. The last patch adds logic for QEMU to report a
proper DTSM clp response rather than j
On Sun, Dec 12, 2021 at 10:19:47AM +0530, Ani Sinha wrote:
> On Fri, Dec 10, 2021 at 10:35 PM Jean-Philippe Brucker
> wrote:
> >
> > Add ACPI support for virtio-iommu on the virt machine, by instantiating
> > a VIOT table. Also add the tests for the ACPI table.
> >
> > Since last posting [1], I re
On Thu, Dec 09, 2021 at 08:53:25AM -0800, Richard Henderson wrote:
> On 12/9/21 8:34 AM, Stefan Hajnoczi wrote:
> > > I'm not running the release cycle this time around, but: it's
> > > already rc4, pull requests by this point need a clear justification
> > > in the cover letter for why they're rea
On Mon, Dec 13, 2021 at 10:29:24AM +0530, Ani Sinha wrote:
> All work related to VIOT tables are being done by Jean. Adding him as the
> maintainer for acpi VIOT table code in qemu.
>
> Signed-off-by: Ani Sinha
Acked-by: Jean-Philippe Brucker
> ---
> MAINTAINERS | 7 +++
> 1 file changed,
Hi, Juan,
Sorry, forget to send to qemu-devel, resend it.
On 2021/11/24 18:05, Juan Quintela wrote:
> We will need to split it later in zero_num (number of zero pages) and
> normal_num (number of normal pages). This name is better.
>
> Signed-off-by: Juan Quintela
> ---
> migration/multifd.h
On Thu, Dec 09, 2021 at 07:51:02PM +0300, Vladimir Sementsov-Ogievskiy wrote:
> 09.12.2021 19:32, Stefan Hajnoczi wrote:
> > On Thu, Dec 09, 2021 at 04:45:13PM +0100, Hanna Reitz wrote:
> > > On 09.12.21 15:23, Stefan Hajnoczi wrote:
> > > > The BlockBackend root child can change during bdrv_draine
On 12/13/2021 4:38 PM, Vladimir Sementsov-Ogievskiy wrote:
13.12.2021 11:02, Rao, Lei wrote:
On 12/3/2021 9:26 AM, Rao, Lei wrote:
On 12/2/2021 5:54 PM, Vladimir Sementsov-Ogievskiy wrote:
02.12.2021 11:53, Daniel P. Berrangé wrote:
On Thu, Dec 02, 2021 at 01:14:47PM +0800, Rao, Lei wr
On Sun, 12 Dec 2021 at 20:43, Richard Henderson
wrote:
>
> On 12/11/21 11:11 AM, Peter Maydell wrote:
> >
> > if (dte_valid) {
> > -max_eventid = 1UL << (FIELD_EX64(dte, DTE, SIZE) + 1);
> > +max_eventid = 1ULL << (FIELD_EX64(dte, DTE, SIZE) + 1);
>
> Without changing the typ
Hi,
I'd like to do instruction traces with library+function name included.
From what I understand *in_asm* only shows instructions when they are
being JIT:ed.
If I call a function twice I only see the instructions once so it makes
sense.
As a workaround, I tried to do a plugin. I looked at t
On 12/6/21 23:45, Philippe Mathieu-Daudé wrote:
> Convert the open-coded vga_mmio_init() to a sysbus device.
> Philippe Mathieu-Daudé (4):
> hw/display: Rename VGA_ISA_MM -> VGA_MMIO
> hw/display/vga-mmio: Inline vga_mm_init()
> hw/display/vga-mmio: QOM'ify vga_mmio_init() as TYPE_VGA_MMIO
>
On 27/11/2021 08.29, Eric Auger wrote:
Introduce a qtest for the virtio-iommu device. The test
allowed to identify an endianess bug in the get_config().
We also remove the unneeded set_config() and fix the value
for domain_range.end field.
Best Regards
Eric
Thanks, I've queued the series now
On Mon, 13 Dec 2021 at 09:28, Jean-Philippe Brucker
wrote:
>
> On Sun, Dec 12, 2021 at 10:19:47AM +0530, Ani Sinha wrote:
> > On Fri, Dec 10, 2021 at 10:35 PM Jean-Philippe Brucker
> > wrote:
> > >
> > > Add ACPI support for virtio-iommu on the virt machine, by instantiating
> > > a VIOT table. A
On Fri, Dec 10, 2021 at 03:00:38PM +0100, Kevin Wolf wrote:
> Am 09.12.2021 um 15:23 hat Stefan Hajnoczi geschrieben:
> > The BlockBackend root child can change during bdrv_drained_begin() when
> > aio_poll() is invoked. In fact the BlockDriverState can reach refcnt 0
> > and blk_drain() is left wi
On 11/16/21 08:26, Simon Burge wrote:
> The cp0_count_ns value is calculated from the CP0_COUNT_RATE_DEFAULT
> constant in target/mips/cpu.c. The cycle counter resolution is defined
> per-CPU in target/mips/cpu-defs.c.inc; use this value for calculating
> cp0_count_ns. Fixings timing problems on
On 11/8/21 04:51, Warner Losh wrote:
> FreeBSD is dropping support for mips starting with FreeBSD 14. mips
> support has been removed from the bsd-user fork because updating it for
> new signal requirements will take too much time. Remove it here since it
> is a distraction.
>
> Signed-off-by: War
On 06/12/2021 23.45, Philippe Mathieu-Daudé wrote:
vga_mmio_init() is used only one time and not very helpful,
inline and remove it.
Reviewed-by: BALATON Zoltan
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/display/vga.h | 5 -
hw/display/vga-mmio.c| 19 ---
Since the previous commit 9ea89876f9d ("target/mips: Fix cycle
counter timing calculations"), MIPSCPU::cp0_count_rate is not
used anymore. We don't need it since it is already expressed
as mips_def_t::CCRes. Remove the duplicate and clean.
Signed-off-by: Philippe Mathieu-Daudé
---
Based-on: <2021
On 12/13/21 11:10, Philippe Mathieu-Daudé wrote:
> On 11/16/21 08:26, Simon Burge wrote:
>> The cp0_count_ns value is calculated from the CP0_COUNT_RATE_DEFAULT
>> constant in target/mips/cpu.c. The cycle counter resolution is defined
>> per-CPU in target/mips/cpu-defs.c.inc; use this value for ca
On Mon, Dec 13, 2021 at 08:43:55AM +0100, Thomas Huth wrote:
>
> Hi Michael, hi Igor,
>
> just FYI, a crash has been reported in the ACPI code ...
> by the way, do you have a gitlab account, so you could be put on CC: for
> such bugs there, too?
>
> Regards,
> Thomas
>
>
> Forward
Hello everyone,
As you know already, my current goal is to try to remove the AioContext lock
from the QEMU block layer.
Currently the AioContext is used pretty much throughout the whole block layer,
it is a little bit confusing to understand what it exactly protects, and I am
starting to think
Same as BDRV_POLL_WHILE, but uses AIO_WAIT_WHILE_UNLOCKED.
Signed-off-by: Emanuele Giuseppe Esposito
---
include/block/block-global-state.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/include/block/block-global-state.h
b/include/block/block-global-state.h
index 7a6b065101..818164a0
Same as the locked version, but use BDRV_POLL_UNLOCKED
Signed-off-by: Emanuele Giuseppe Esposito
---
block/io.c | 35 ++-
include/block/block-io.h | 2 ++
2 files changed, 28 insertions(+), 9 deletions(-)
diff --git a/block/io.c b/block/io.c
index
There are a couple of problems in this test when we add
subtree drains in bdrv_replace_child_noperm:
- First of all, inconsistency between block_job_create under
aiocontext lock that internally calls blk_insert_bs and therefore
bdrv_replace_child_noperm, and blk_insert_bs that is called two lines
Protect bdrv_replace_child_noperm, as it modifies the
graph by adding/removing elements to .children and .parents
list of a bs.
Signed-off-by: Emanuele Giuseppe Esposito
---
block.c | 24
1 file changed, 24 insertions(+)
diff --git a/block.c b/block.c
index 3c3c90704c..
Graph initialization functions like blk_new(), bdrv_new() and so on
should not run in a coroutine. In fact, they might invoke a drain
(for example blk_insert_bs eventually calls bdrv_replace_child_noperm)
that in turn can invoke callbacks like bdrv_do_drained_begin_quiesce(),
that asserts exactly t
Signed-off-by: Emanuele Giuseppe Esposito
---
block/io.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/block/io.c b/block/io.c
index a031691860..c2f1a494c4 100644
--- a/block/io.c
+++ b/block/io.c
@@ -759,6 +759,7 @@ void assert_bdrv_graph_writable(BlockDriverState *bs)
* Once the nec
On 06/12/2021 23.45, Philippe Mathieu-Daudé wrote:
Introduce TYPE_VGA_MMIO, a sysbus device.
While there is no change in the vga_mmio_init()
interface, this is a migration compatibility break
of the MIPS Acer Pica 61 Jazz machine (pica61).
It's unfortunate, but as far as I know, it would be pr
On 12/10/21 14:54, Markus Armbruster wrote:
Daniel P. Berrangé writes:
On Thu, Dec 02, 2021 at 07:57:38AM +0100, Markus Armbruster wrote:
= Motivation =
QEMU startup and initial configuration were designed many years ago for
a much, much simpler QEMU. They have since changed beyond recog
On Mon, Dec 13, 2021 at 10:04:57AM +, Peter Maydell wrote:
> On Mon, 13 Dec 2021 at 09:28, Jean-Philippe Brucker
> wrote:
> >
> > On Sun, Dec 12, 2021 at 10:19:47AM +0530, Ani Sinha wrote:
> > > On Fri, Dec 10, 2021 at 10:35 PM Jean-Philippe Brucker
> > > wrote:
> > > >
> > > > Add ACPI suppo
On Mon, 13 Dec 2021 at 09:48, Peter Maydell wrote:
>
> On Sun, 12 Dec 2021 at 20:43, Richard Henderson
> wrote:
> >
> > On 12/11/21 11:11 AM, Peter Maydell wrote:
> > >
> > > if (dte_valid) {
> > > -max_eventid = 1UL << (FIELD_EX64(dte, DTE, SIZE) + 1);
> > > +max_eventid =
On Mon, Dec 13, 2021 at 10:47:00AM +0800, Jason Wang wrote:
On Sun, Dec 12, 2021 at 5:30 PM Michael S. Tsirkin wrote:
On Sat, Dec 11, 2021 at 03:00:27AM +, Longpeng (Mike, Cloud Infrastructure
Service Product Dept.) wrote:
>
>
> > -Original Message-
> > From: Stefan Hajnoczi [mail
On 12/13/21 11:48, Thomas Huth wrote:
> On 06/12/2021 23.45, Philippe Mathieu-Daudé wrote:
>> Introduce TYPE_VGA_MMIO, a sysbus device.
>>
>> While there is no change in the vga_mmio_init()
>> interface, this is a migration compatibility break
>> of the MIPS Acer Pica 61 Jazz machine (pica61).
>
>
On Mon, 13 Dec 2021 at 10:56, Jean-Philippe Brucker
wrote:
>
> On Mon, Dec 13, 2021 at 10:04:57AM +, Peter Maydell wrote:
> > On Mon, 13 Dec 2021 at 09:28, Jean-Philippe Brucker
> > wrote:
> > >
> > > On Sun, Dec 12, 2021 at 10:19:47AM +0530, Ani Sinha wrote:
> > > > On Fri, Dec 10, 2021 at 1
On Sat, Dec 11, 2021 at 04:11:04AM +, Longpeng (Mike, Cloud Infrastructure
Service Product Dept.) wrote:
-Original Message-
From: Stefano Garzarella [mailto:sgarz...@redhat.com]
Sent: Thursday, December 9, 2021 11:55 PM
To: Longpeng (Mike, Cloud Infrastructure Service Product Dept
In case when the function fails to get parent device data,
the parent_dev_info variable will be initialized, but not freed.
Signed-off-by: Kostiantyn Kostiuk
Signed-off-by: Kostiantyn Kostiuk
---
qga/commands-win32.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/qga
Signed-off-by: Kostiantyn Kostiuk
Signed-off-by: Kostiantyn Kostiuk
---
qga/commands-win32.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/qga/commands-win32.c b/qga/commands-win32.c
index 4e84afd83b..3dd74fe225 100644
--- a/qga/commands-win32.c
+++ b/qga/commands-win
To prevent memory leaks, always try to free initialized variables.
Signed-off-by: Kostiantyn Kostiuk
Signed-off-by: Kostiantyn Kostiuk
---
qga/commands-win32.c | 25 -
1 file changed, 12 insertions(+), 13 deletions(-)
diff --git a/qga/commands-win32.c b/qga/commands-win
Signed-off-by: Kostiantyn Kostiuk
Signed-off-by: Kostiantyn Kostiuk
---
qga/commands-win32.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/qga/commands-win32.c b/qga/commands-win32.c
index 6bde5260e8..96737f33e1 100644
--- a/qga/commands-win32.c
+++ b/qga/commands-win
This set of patches fixes memory leaks in the get_pci_info function when it
fails
to get parent device data. In this case the parent_dev_info and the
parent_dev_id
variables will be initialized, but not freed.
Bug: https://bugzilla.redhat.com/show_bug.cgi?id=1958825
Kostiantyn Kostiuk (5):
gq
Microsoft suggests this solution in the documentation:
https://docs.microsoft.com/en-us/windows/win32/api/setupapi/nf-setupapi-setupdigetdeviceinterfacedetaila
Signed-off-by: Kostiantyn Kostiuk
Signed-off-by: Kostiantyn Kostiuk
---
qga/commands-win32.c | 30 --
1 fil
Peter Maydell writes:
> The checks in the ITS on the rdbase values in guest commands are
> off-by-one: they permit the guest to pass us a value equal to
> s->gicv3->num_cpu, but the valid values are 0...num_cpu-1. This
> meant the guest could cause us to index off the end of the
> s->gicv3->cp
Peter Maydell writes:
> The TableDesc struct defines properties of the in-guest-memory tables
> which the guest tells us about by writing to the GITS_BASER
> registers. This struct currently has a union 'maxids', but all the
> fields of the union have the same type (uint32_t) and do the same
>
Peter Maydell writes:
> In extract_table_params() we process each GITS_BASER register. If
> the register's Valid bit is not set, this means there is no
> in-guest-memory table and so we should not try to interpret the other
> fields in the register. This was incorrectly coded as a 'return'
>
Peter Maydell writes:
> The extract_table_params() decodes the fields in the GITS_BASER
> registers into TableDesc structs. Since the fields are the same for
> all the GITS_BASER registers, there is currently a lot of code
> duplication within the switch (type) statement. Refactor so that the
Peter Maydell writes:
> We set the TableDesc entry_sz field from the appropriate
> GITS_BASER.ENTRYSIZE field. That ID register field specifies the
> number of bytes per table entry minus one. However when we use
> td->entry_sz we assume it to be the number of bytes per table entry
> (for ins
* Rao, Lei (lei@intel.com) wrote:
> Signed-off-by: Lei Rao
You don't say why you want to move it - it's just a trace, what's the
advantage?
Dave
> ---
> migration/colo.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/migration/colo.c b/migration/colo.c
> in
Peter Maydell writes:
> The GITS_TYPE_PHYSICAL define is the value we set the
> GITS_TYPER.Physical field to -- this is 1 to indicate that we support
> physical LPIs. (Support for virtual LPIs is the GITS_TYPER.Virtual
> field.) We also use this define as the *value* that we write into an
> in
Peter Maydell writes:
> The MAPI command takes arguments DeviceID, EventID, ICID, and is
> defined to be equivalent to MAPTI DeviceID, EventID, EventID, ICID.
> (That is, where MAPTI takes an explicit pINTID, MAPI uses the EventID
> as the pINTID.)
>
> We didn't quite get this right. In partic
Peter Maydell writes:
> We currently define a bitmask for the GITS_CTLR ENABLED bit in
> two ways: as ITS_CTLR_ENABLED, and via the FIELD() macro as
> R_GITS_CTLR_ENABLED_MASK. Consistently use the FIELD macro version
> everywhere and remove the redundant ITS_CTLR_ENABLED define.
>
> Signed-off
Peter Maydell writes:
> Currently the ITS code that reads and writes DTEs uses open-coded
> shift-and-mask to assemble the various fields into the 64-bit DTE
> word. The names of the macros used for mask and shift values are
> also somewhat inconsistent, and don't follow our usual convention
>
Instructions xscvqpdp, xsmaxcdp, xsmincdp, xsmaxjdp, and xsminjdp are
using the wrong registers, which yields the wrong result when using
them.
This patch series fixes this issue by correcting the registers used.
It also takes the opportunity to move these instructions to decodetree.
v2:
- Change
Reviewed-by: Richard Henderson
Signed-off-by: Victor Colombo
---
target/ppc/insn32.decode| 17 +---
target/ppc/translate/vsx-impl.c.inc | 30 +
target/ppc/translate/vsx-ops.c.inc | 4
3 files changed, 40 insertions(+), 11 deletions(-)
d
From: Matheus Ferst
This instruction has VRT and VRB fields instead of T/TX and B/BX.
Reviewed-by: Richard Henderson
Signed-off-by: Matheus Ferst
---
target/ppc/translate/vsx-impl.c.inc | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/target/ppc/translate/vsx-impl.c.in
PPC instruction xsmaxcdp, xsmincdp, xsmaxjdp, and xsminjdp are using
vector registers when they should be using VSX ones. This happens
because the instructions are using GEN_VSX_HELPER_R3, which adds 32
to the register numbers, effectively making them vector registers.
This patch fixes it by chang
From: Matheus Ferst
Reviewed-by: Richard Henderson
Signed-off-by: Matheus Ferst
---
target/ppc/fpu_helper.c | 10 +++---
target/ppc/helper.h | 2 +-
target/ppc/insn32.decode| 4
target/ppc/translate/vsx-impl.c.inc | 24 +---
On 12/13/2021 7:45 PM, Dr. David Alan Gilbert wrote:
* Rao, Lei (lei@intel.com) wrote:
Signed-off-by: Lei Rao
You don't say why you want to move it - it's just a trace, what's the
advantage?
I think it's not necessary to put trace code in the critical section.
So, moving it behind qe
From: Matheus Ferst
The non-signalling versions of VSX scalar convert to shorter/longer
precision insns doesn't silence SNaNs in the hardware. We are currently
honoring this behavior in xscvdpspn, since helper_xscvdpspn handles the
conversion with extracts/deposits/etc. OTOH, xscvspdpn uses
float
Too late for 6.2 now, so Cc'ing qemu-trivial (series reviewed).
On 11/19/21 21:11, Philippe Mathieu-Daudé wrote:
> Fix issue #521 reported by Alex some months ago:
> https://gitlab.com/qemu-project/qemu/-/issues/521
>
> Philippe Mathieu-Daudé (2):
> hw/scsi/megasas: Fails command if SGL buffer
On 12/13/21 13:13, matheus.fe...@eldorado.org.br wrote:
> From: Matheus Ferst
>
> The non-signalling versions of VSX scalar convert to shorter/longer
> precision insns doesn't silence SNaNs in the hardware. We are currently
> honoring this behavior in xscvdpspn, since helper_xscvdpspn handles the
On 12/11/21 20:11, Peter Maydell wrote:
> In several places we have a local variable max_l2_entries which is
> the number of entries which will fit in a level 2 table. The
> calculations done on this value are correct; rename it to
> num_l2_entries to fit the convention we're using in this code.
>
On 12/11/21 20:11, Peter Maydell wrote:
> In process_its_cmd() and process_mapti() we must check the
> event ID against a limit defined by the size field in the DTE,
> which specifies the number of ID bits minus one. Convert
> this code to our num_foo convention, fixing the off-by-one error.
>
> S
On 12/11/21 20:11, Peter Maydell wrote:
> When an ITS detects an error in a command, it has an
> implementation-defined (CONSTRAINED UNPREDICTABLE) choice of whether
> to ignore the command, proceeding to the next one in the queue, or to
> stall the ITS command queue, processing nothing further. T
On 12/11/21 20:11, Peter Maydell wrote:
> process_its_cmd() returns a bool, like all the other process_ functions.
> However we were putting its return value into 'res', not 'result',
> which meant we would ignore it when deciding whether to continue
> or stall the command queue. Fix the typo.
>
>
Peter Maydell writes:
> The comment says that in our CTE format the RDBase field is 36 bits;
> in fact for us it is only 16 bits, because we use the RDBase format
> where it specifies a 16-bit CPU number. The code already uses
> RDBASE_PROCNUM_LENGTH (16) as the field width, so fix the comment
Peter Maydell writes:
> Use FIELD macros to handle CTEs, rather than ad-hoc mask-and-shift.
>
> Signed-off-by: Peter Maydell
> ---
> hw/intc/gicv3_internal.h | 3 ++-
> hw/intc/arm_gicv3_its.c | 7 ---
> 2 files changed, 6 insertions(+), 4 deletions(-)
>
> diff --git a/hw/intc/gicv3_inte
This change will help us move the mapping of XSCOM regions under the
PHB3 realize routine, which will be necessary for user created PHB3
devices.
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Frederic Barrat
Signed-off-by: Cédric Le Goater
---
include/hw/pci-host/pnv_phb3.h | 3 +++
hw/pci
Use the num_stacks class attribute to compute the PHB index depending
on the PEC index :
* PEC0 provides 1 PHB (PHB0)
* PEC1 provides 2 PHBs (PHB1 and PHB2)
* PEC2 provides 3 PHBs (PHB3, PHB4 and PHB5)
The routine pnv_pec_phb_offset() is a bit complex but it also prepares
ground for PHB5 w
It prepares ground for PHB5 which has different values.
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Frederic Barrat
Signed-off-by: Cédric Le Goater
---
include/hw/pci-host/pnv_phb4.h | 2 ++
hw/pci-host/pnv_phb4_pec.c | 2 ++
hw/ppc/pnv.c | 4 ++--
3 files changed,
Each PEC device of the POWER9 chip has a predefined number of stacks,
equivalent of a root port complex:
PEC0 -> 1 stack
PEC1 -> 2 stacks
PEC2 -> 3 stacks
Introduce a class attribute to hold these values and remove the
"num-stacks" property.
Reviewed-by: Daniel Henrique Barboza
Reviewed-b
The POWER8 processors with a NVLink logic unit have 4 PHB3 devices per
chip.
Signed-off-by: Cédric Le Goater
---
hw/ppc/pnv.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 44ae41a9cb6b..6359bce549ca 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pn
When -nodefaults is supported for PHB3 devices, the phbs array under
the chip will be empty. This will break the XICSFabric handlers, and
all interrupt delivery, and the 'info pic' HMP command.
Do a QOM loop on the chip children and look for PHB3 devices instead.
Signed-off-by: Cédric Le Goater
This change will help us providing support for user created PHB3
devices.
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Frederic Barrat
Signed-off-by: Cédric Le Goater
---
hw/pci-host/pnv_phb3_pbcq.c | 11 +++
hw/ppc/pnv.c| 12
2 files changed, 11 inser
PHB3 devices and PCI devices can now be added to the powernv8 machine
using :
-device pnv-phb3,chip-id=0,index=1 \
-device nec-usb-xhci,bus=pci.1,addr=0x0
The 'index' property identifies the PHB3 in the chip. In case of user
created devices, a lookup on 'chip-id' is required to assign the
own
This is not useful and will be in the way for support of user created
PHB4 devices.
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Frederic Barrat
Signed-off-by: Cédric Le Goater
---
hw/pci-host/pnv_phb4_pec.c | 6 +-
hw/ppc/pnv.c | 2 --
2 files changed, 1 insertion(+), 7
PHB3s ared SysBus devices and should be allowed to be dynamically
created.
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Cédric Le Goater
---
hw/pci-host/pnv_phb3.c | 9 +
hw/ppc/pnv.c | 2 ++
2 files changed, 11 insertions(+)
diff --git a/hw/pci-host/pnv_phb3.c b/hw/pc
Hello,
On the POWER8 processor, powernv8 machine, PHB3 devices can simply be
created with :
-device pnv-phb3,chip-id=0,index=1
with a maximum of 3 PHB3s per chip, each PHB3 adding a new PCIe bus.
On the POWER9 processor, powernv9 machine, the logic is different. The
the chip comes with 3 PH
The maximum number of PHB3 devices per chip can be different depending
on the POWER8 processor model.
Signed-off-by: Cédric Le Goater
---
hw/pci-host/pnv_phb3.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/pci-host/pnv_phb3.c b/hw/pci-host/pnv_phb3.c
index 3aa42ef9d4b9.
POWER9 processor comes with 3 PHB4 PEC (PCI Express Controller) and
each PEC can have several PHBs :
* PEC0 provides 1 PHB (PHB0)
* PEC1 provides 2 PHBs (PHB1 and PHB2)
* PEC2 provides 3 PHBs (PHB3, PHB4 and PHB5)
A num_pecs class attribute represents better the logic units of the
POWER9 c
PHB4 devices and PCI devices can now be added to the powernv9 machine
using:
-device pnv-phb4-pec,chip-id=0,index=0
-device nec-usb-xhci,bus=pci.0,addr=0x0
In case of user created devices, a lookup on 'chip-id' is required to
assign the owning chip.
To be noted, that the PEC PHB4 devices can
The powernv machine uses the object hierarchy to populate the device
tree and each device should be parented to the chip it belongs to.
This is not the case for user created devices which are parented to
the container "/unattached".
Make sure a PHB3 device is parented to its chip by reparenting th
When -nodefaults is supported for PHB4 devices, the pecs array under
the chip will be empty. This will break the 'info pic' HMP command.
Do a QOM loop on the chip children and look for PEC PHB4 devices
instead.
Signed-off-by: Cédric Le Goater
---
hw/ppc/pnv.c | 20 +---
1 file c
Peter Maydell writes:
> In process_its_cmd() and process_mapti() we must check the
> event ID against a limit defined by the size field in the DTE,
> which specifies the number of ID bits minus one. Convert
> this code to our num_foo convention, fixing the off-by-one error.
>
> Signed-off-by: P
It is not used elsewhere so that's where it belongs.
Signed-off-by: Cédric Le Goater
---
include/hw/ppc/pnv.h | 4 ++--
hw/ppc/pnv.c | 7 +++
2 files changed, 5 insertions(+), 6 deletions(-)
diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h
index ca27bd39f0ac..251c9854329d 10
And check the PEC index using the chip class.
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Frederic Barrat
Signed-off-by: Cédric Le Goater
---
include/hw/pci-host/pnv_phb4.h | 2 ++
hw/pci-host/pnv_phb4_pec.c | 7 +++
hw/ppc/pnv.c | 2 ++
3 files changed, 11 inse
This change will help us providing support for user created PHB4
devices.
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Cédric Le Goater
---
hw/pci-host/pnv_phb4_pec.c | 34 ++
hw/ppc/pnv.c | 37 -
2 files c
Peter Maydell writes:
> The ITS code has to check whether various parameters passed in
> commands are in-bounds, where the limit is defined in terms of the
> number of bits that are available for the parameter. (For example,
> the GITS_TYPER.Devbits ID register field specifies the number of
>
Peter Maydell writes:
> In several places we have a local variable max_l2_entries which is
> the number of entries which will fit in a level 2 table. The
> calculations done on this value are correct; rename it to
> num_l2_entries to fit the convention we're using in this code.
>
> Signed-off-
It is never used.
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Frederic Barrat
Signed-off-by: Cédric Le Goater
---
hw/ppc/pnv.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 74c25c1c5d98..0413d221b311 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -
When Altivec support was added to the e6500 kernel in 2012[1], the
QEMU code was not changed, so we don't register the VPU/VPUA
exceptions for the e6500:
qemu: fatal: Raised an exception without defined vector 73
Note that the error message says 73, instead of 32, which is the IVOR
for VPU. Thi
Peter Maydell writes:
> The bounds check on the number of interrupt IDs is correct, but
> doesn't match our convention; change the variable name, initialize it
> to the 2^n value rather than (2^n)-1, and use >= instead of > in the
> comparison.
>
> Signed-off-by: Peter Maydell
Reviewed-by: Al
Peter Maydell writes:
> process_its_cmd() returns a bool, like all the other process_ functions.
> However we were putting its return value into 'res', not 'result',
> which meant we would ignore it when deciding whether to continue
> or stall the command queue. Fix the typo.
Arguably having t
The cp0_count_ns value is calculated from the CP0_COUNT_RATE_DEFAULT
constant in target/mips/cpu.c. The cycle counter resolution is defined
per-CPU in target/mips/cpu-defs.c.inc; use this value for calculating
cp0_count_ns. Fixings timing problems on guest OSs for the 20Kc CPU
which has a CCRes o
On Tue, Dec 07, 2021 at 01:55:34PM +, Peter Maydell wrote:
> On Tue, 7 Dec 2021 at 13:53, Stefan Hajnoczi wrote:
> >
> > On Mon, Dec 06, 2021 at 02:34:45PM +, Peter Maydell wrote:
> > > On Mon, 6 Dec 2021 at 14:33, Stefan Hajnoczi wrote:
> > > >
> > > > v3:
> > > > - Added __attribute__((
Hi Phil,
=?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= wrote:
> Oops, missing your Signed-off-by tag, see:
> https://www.qemu.org/docs/master/devel/submitting-a-patch.html#patch-emails-must-includ
e-a-signed-off-by-line
>
> Do you mind re-sending with your S-o-b? Meanwhile, patch dropped.
Hopefully I'
On 12/13/21 14:35, Fabiano Rosas wrote:
When Altivec support was added to the e6500 kernel in 2012[1], the
QEMU code was not changed, so we don't register the VPU/VPUA
exceptions for the e6500:
qemu: fatal: Raised an exception without defined vector 73
Note that the error message says 73, in
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