On Sat, Dec 11, 2021 at 03:00:27AM +, Longpeng (Mike, Cloud Infrastructure
Service Product Dept.) wrote:
>
>
> > -Original Message-
> > From: Stefan Hajnoczi [mailto:stefa...@redhat.com]
> > Sent: Thursday, December 9, 2021 5:17 PM
> > To: Longpeng (Mike, Cloud Infrastructure Service
On Fri, Dec 10, 2021 at 01:09:46PM +, Peter Griffin wrote:
> Hi Michael,
>
> On Fri, 10 Dec 2021, Michael S. Tsirkin wrote:
>
> > On Thu, Dec 09, 2021 at 02:55:58PM +, Peter Griffin wrote:
> > > Signed-off-by: Peter Griffin
> > > ---
> > > include/standard-headers/linux/virtio_video.h |
.
On Thu, Dec 9, 2021 at 11:28 PM Eric DeVolder wrote:
>
> This builds the ACPI ERST table to inform OSPM how to communicate
> with the acpi-erst device.
This patch starts in the middle of pci device code addition, between
erst_reg_ops and erst_post_load. I do not like this :(
>
> Signed-off-by
On 12/11/21 11:11 AM, Peter Maydell wrote:
From: Alex Bennée
While trying to debug a GIC ITS failure I saw some guest errors that
had poor formatting as well as leaving me confused as to what failed.
As most of the checks aren't possible without a valid dte split that
check apart and then check
On 12/11/21 11:11 AM, Peter Maydell wrote:
The checks in the ITS on the rdbase values in guest commands are
off-by-one: they permit the guest to pass us a value equal to
s->gicv3->num_cpu, but the valid values are 0...num_cpu-1. This
meant the guest could cause us to index off the end of the
s->
On 12/11/21 11:11 AM, Peter Maydell wrote:
We currently define a bitmask for the GITS_CTLR ENABLED bit in
two ways: as ITS_CTLR_ENABLED, and via the FIELD() macro as
R_GITS_CTLR_ENABLED_MASK. Consistently use the FIELD macro version
everywhere and remove the redundant ITS_CTLR_ENABLED define.
Si
On 12/11/21 11:11 AM, Peter Maydell wrote:
The TableDesc struct defines properties of the in-guest-memory tables
which the guest tells us about by writing to the GITS_BASER
registers. This struct currently has a union 'maxids', but all the
fields of the union have the same type (uint32_t) and do
On 12/11/21 11:11 AM, Peter Maydell wrote:
In extract_table_params() we process each GITS_BASER register. If
the register's Valid bit is not set, this means there is no
in-guest-memory table and so we should not try to interpret the other
fields in the register. This was incorrectly coded as a
On 12/11/21 11:11 AM, Peter Maydell wrote:
The extract_table_params() decodes the fields in the GITS_BASER
registers into TableDesc structs. Since the fields are the same for
all the GITS_BASER registers, there is currently a lot of code
duplication within the switch (type) statement. Refactor
On 12/11/21 11:11 AM, Peter Maydell wrote:
We set the TableDesc entry_sz field from the appropriate
GITS_BASER.ENTRYSIZE field. That ID register field specifies the
number of bytes per table entry minus one. However when we use
td->entry_sz we assume it to be the number of bytes per table entry
On 12/11/21 11:11 AM, Peter Maydell wrote:
The GITS_TYPE_PHYSICAL define is the value we set the
GITS_TYPER.Physical field to -- this is 1 to indicate that we support
physical LPIs. (Support for virtual LPIs is the GITS_TYPER.Virtual
field.) We also use this define as the *value* that we write i
On 12/11/21 11:11 AM, Peter Maydell wrote:
The MAPI command takes arguments DeviceID, EventID, ICID, and is
defined to be equivalent to MAPTI DeviceID, EventID, EventID, ICID.
(That is, where MAPTI takes an explicit pINTID, MAPI uses the EventID
as the pINTID.)
We didn't quite get this right. I
On 12/11/21 11:11 AM, Peter Maydell wrote:
Currently the ITS code that reads and writes DTEs uses open-coded
shift-and-mask to assemble the various fields into the 64-bit DTE
word. The names of the macros used for mask and shift values are
also somewhat inconsistent, and don't follow our usual c
On 12/11/21 11:11 AM, Peter Maydell wrote:
The DTE.SIZE field is 5 bits, which means that DTE.SIZE + 1
might in theory be 32. When calculating 1 << (DTE.SIZE + 1)
use 1ULL to ensure that we don't do this arithmetic at 32 bits
and shift the 1 off the end in this case.
Signed-off-by: Peter Maydell
On 12/11/21 11:11 AM, Peter Maydell wrote:
The comment says that in our CTE format the RDBase field is 36 bits;
in fact for us it is only 16 bits, because we use the RDBase format
where it specifies a 16-bit CPU number. The code already uses
RDBASE_PROCNUM_LENGTH (16) as the field width, so fix t
On 12/11/21 11:11 AM, Peter Maydell wrote:
Use FIELD macros to handle CTEs, rather than ad-hoc mask-and-shift.
Signed-off-by: Peter Maydell
---
hw/intc/gicv3_internal.h | 3 ++-
hw/intc/arm_gicv3_its.c | 7 ---
2 files changed, 6 insertions(+), 4 deletions(-)
Reviewed-by: Richard Hen
On 12/11/21 11:11 AM, Peter Maydell wrote:
In several places we have a local variable max_l2_entries which is
the number of entries which will fit in a level 2 table. The
calculations done on this value are correct; rename it to
num_l2_entries to fit the convention we're using in this code.
Sig
On 12/11/21 11:11 AM, Peter Maydell wrote:
if (dte_valid) {
-max_eventid = 1UL << (FIELD_EX64(dte, DTE, SIZE) + 1);
+max_eventid = 1ULL << (FIELD_EX64(dte, DTE, SIZE) + 1);
Without changing the type of max_eventid, I think it'd be easiest to fix the off-by-one
bug by n
On 12/11/21 20:11, Peter Maydell wrote:
> We currently define a bitmask for the GITS_CTLR ENABLED bit in
> two ways: as ITS_CTLR_ENABLED, and via the FIELD() macro as
> R_GITS_CTLR_ENABLED_MASK. Consistently use the FIELD macro version
> everywhere and remove the redundant ITS_CTLR_ENABLED define.
On 12/11/21 20:11, Peter Maydell wrote:
> The extract_table_params() decodes the fields in the GITS_BASER
> registers into TableDesc structs. Since the fields are the same for
> all the GITS_BASER registers, there is currently a lot of code
> duplication within the switch (type) statement. Refact
On 12/11/21 11:11 AM, Peter Maydell wrote:
process_its_cmd() returns a bool, like all the other process_ functions.
However we were putting its return value into 'res', not 'result',
which meant we would ignore it when deciding whether to continue
or stall the command queue. Fix the typo.
Signed
On 12/11/21 11:11 AM, Peter Maydell wrote:
In process_cmdq(), we read 64 bits of the command packet, which
contain the command identifier, which we then switch() on to dispatch
to an appropriate sub-function. However, if address_space_ldq_le()
reports a memory transaction failure, we still read
On 12/11/21 11:11 AM, Peter Maydell wrote:
When an ITS detects an error in a command, it has an
implementation-defined (CONSTRAINED UNPREDICTABLE) choice of whether
to ignore the command, proceeding to the next one in the queue, or to
stall the ITS command queue, processing nothing further. The
On 12/11/21 20:11, Peter Maydell wrote:
> Currently the ITS code that reads and writes DTEs uses open-coded
> shift-and-mask to assemble the various fields into the 64-bit DTE
> word. The names of the macros used for mask and shift values are
> also somewhat inconsistent, and don't follow our usua
On 12/11/21 11:11 AM, Peter Maydell wrote:
Fix process_its_cmd() to consistently return CMD_STALL for
memory errors and CMD_CONTINUE for parameter errors, as
we claim in the comments that we do.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
r~
On 12/11/21 11:11 AM, Peter Maydell wrote:
Refactor process_its_cmd() so that it consistently uses
the structure
do thing;
if (error condition) {
return early;
}
do next thing;
rather than doing some of the work nested inside if (not error)
code blocks.
Signed-off-by: Peter M
On 12/11/21 11:11 AM, Peter Maydell wrote:
Fix process_mapti() to consistently return CMD_STALL for memory
errors and CMD_CONTINUE for parameter errors, as we claim in the
comments that we do.
Signed-off-by: Peter Maydell
---
hw/intc/arm_gicv3_its.c | 28 +---
1 file c
On 12/11/21 11:11 AM, Peter Maydell wrote:
Fix process_mapc() to consistently return CMD_STALL for memory
errors and CMD_CONTINUE for parameter errors, as we claim in the
comments that we do.
Signed-off-by: Peter Maydell
---
hw/intc/arm_gicv3_its.c | 8 +++-
1 file changed, 3 insertions(+
On 12/11/21 11:11 AM, Peter Maydell wrote:
Fix process_mapd() to consistently return CMD_STALL for memory
errors and CMD_CONTINUE for parameter errors, as we claim in the
comments that we do.
Signed-off-by: Peter Maydell
---
hw/intc/arm_gicv3_its.c | 10 --
1 file changed, 4 insertion
On 12/11/21 11:11 AM, Peter Maydell wrote:
The ITS has several tables which all share a similar format,
described by the TableDesc struct: the guest may configure them
to be a single-level table or a two-level table. Currently we
open-code the process of finding the table entry in all the
functio
On Thu, Dec 09, 2021 at 12:57:31PM -0500, Eric DeVolder wrote:
> This builds the ACPI ERST table to inform OSPM how to communicate
> with the acpi-erst device.
>
> Signed-off-by: Eric DeVolder
> ---
> hw/acpi/erst.c | 241
> +
> 1 file cha
On Sun, Dec 12, 2021 at 5:30 PM Michael S. Tsirkin wrote:
>
> On Sat, Dec 11, 2021 at 03:00:27AM +, Longpeng (Mike, Cloud
> Infrastructure Service Product Dept.) wrote:
> >
> >
> > > -Original Message-
> > > From: Stefan Hajnoczi [mailto:stefa...@redhat.com]
> > > Sent: Thursday, Dece
Ping!
Please help review the V3 patch, thank you!
On 12/04/2021 08:06 PM, Xiaojuan Yang wrote:
> This series patch add softmmu support for LoongArch.
> Base on the linux-user emulation support V13 patch.
> *
> https://patchew.org/QEMU/1638610165-15036-1-git-send-email-gaos...@loongson.cn/
> Th
On Sat, Dec 11, 2021 at 1:23 PM Longpeng (Mike, Cloud Infrastructure
Service Product Dept.) wrote:
>
>
>
> > -Original Message-
> > From: Jason Wang [mailto:jasow...@redhat.com]
> > Sent: Wednesday, December 8, 2021 2:27 PM
> > To: Longpeng (Mike, Cloud Infrastructure Service Product Dept.
On Fri, Dec 10, 2021 at 3:37 PM Yifei Jiang wrote:
>
> Get isa info from kvm while kvm init.
>
> Signed-off-by: Yifei Jiang
> Signed-off-by: Mingwang Li
> Reviewed-by: Alistair Francis
Looks good to me.
Reviewed-by: Anup Patel
Regards,
Anup
> ---
> target/riscv/kvm.c | 32
On Fri, Dec 10, 2021 at 3:37 PM Yifei Jiang wrote:
>
> Get GPR CSR and FP registers from kvm by KVM_GET_ONE_REG ioctl.
>
> Signed-off-by: Yifei Jiang
> Signed-off-by: Mingwang Li
> Reviewed-by: Alistair Francis
Looks good to me.
Reviewed-by: Anup Patel
Regards,
Anup
> ---
> target/riscv/k
On Fri, Dec 10, 2021 at 3:37 PM Yifei Jiang wrote:
>
> Put GPR CSR and FP registers to kvm by KVM_SET_ONE_REG ioctl
>
> Signed-off-by: Yifei Jiang
> Signed-off-by: Mingwang Li
> Reviewed-by: Alistair Francis
Looks good to me.
Reviewed-by: Anup Patel
Regards,
Anup
> ---
> target/riscv/kvm.
On Fri, Dec 10, 2021 at 3:37 PM Yifei Jiang wrote:
>
> Get kernel and fdt start address in virt.c, and pass them to KVM
> when cpu reset. In addition, add kvm_riscv.h to place riscv specific
> interface.
>
> Signed-off-by: Yifei Jiang
> Signed-off-by: Mingwang Li
> Reviewed-by: Alistair Francis
On Fri, Dec 10, 2021 at 3:37 PM Yifei Jiang wrote:
>
> When KVM is enabled, set the S-mode external interrupt through
> kvm_riscv_set_irq function.
>
> Signed-off-by: Yifei Jiang
> Signed-off-by: Mingwang Li
> Reviewed-by: Alistair Francis
> ---
> target/riscv/cpu.c | 6 +-
> target
On Fri, Dec 10, 2021 at 3:37 PM Yifei Jiang wrote:
>
> Use char-fe to handle console sbi call, which implement early
> console io while apply 'earlycon=sbi' into kernel parameters.
>
> Signed-off-by: Yifei Jiang
> Signed-off-by: Mingwang Li
Looks good to me.
Reviewed-by: Anup Patel
Regards,
On Fri, Dec 10, 2021 at 3:38 PM Yifei Jiang wrote:
>
> Add virtual time context description to vmstate_kvmtimer. After cpu being
> loaded, virtual time context is updated to KVM.
>
> Signed-off-by: Yifei Jiang
> Signed-off-by: Mingwang Li
> ---
> target/riscv/machine.c | 37
On Fri, Dec 10, 2021 at 3:38 PM Yifei Jiang wrote:
>
> We hope that virtual time adjusts with vm state changing. When a vm
> is stopped, guest virtual time should stop counting and kvm_timer
> should be stopped. When the vm is resumed, guest virtual time should
> continue to count and kvm_timer sh
All work related to VIOT tables are being done by Jean. Adding him as the
maintainer for acpi VIOT table code in qemu.
Signed-off-by: Ani Sinha
---
MAINTAINERS | 7 +++
1 file changed, 7 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 7543eb4d59..f9580f2fe2 100644
--- a/MAINTAINE
On Fri, Dec 10, 2021 at 3:37 PM Yifei Jiang wrote:
>
> Add kvm_riscv_get/put_regs_timer to synchronize virtual time context
> from KVM.
>
> To set register of RISCV_TIMER_REG(state) will occur a error from KVM
> on kvm_timer_state == 0. It's better to adapt in KVM, but it doesn't matter
> that ada
Vladislav Yaroshchuk writes:
> Create separate netdevs for each vmnet operating mode:
> - vmnet-host
> - vmnet-shared
> - vmnet-bridged
>
> Signed-off-by: Vladislav Yaroshchuk
QAPI schema
Acked-by: Markus Armbruster
This patch allows to proceed further to be able to build with Muon buildsystem
https://sr.ht/~lattis/muon/
There are still few bugs remain, but they are on the Muon side:
https://todo.sr.ht/~lattis/muon/21
Best regards,
Anton Kochkov.
>From fa80e0c17b14b8f5067d13ad7bc63e0d2cbb94ce Mon Sep 17 00
On 10/12/2021 14.05, Philippe Mathieu-Daudé wrote:
On 12/9/21 16:22, Richard W.M. Jones wrote:
On Thu, Dec 09, 2021 at 04:08:24PM +0100, Thomas Huth wrote:
On 09/12/2021 15.55, Richard W.M. Jones wrote:
On Thu, Dec 09, 2021 at 03:48:01PM +0100, Thomas Huth wrote:
It's easier to do this in mes
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