[PATCH v11 00/77] support vector extension v1.0

From: Frank Chang This patchset implements the vector extension v1.0 for RISC-V on QEMU. RVV v1.0 spec is now fronzen for public review: https://github.com/riscv/riscv-v-spec/releases/tag/v1.0 The port is available here: https://github.com/sifive/qemu/tree/rvv-1.0-upstream-v11 RVV v1.0 can be

[PATCH v11 18/77] target/riscv: rvv-1.0: remove amo operations instructions

From: Frank Chang Vector AMOs are removed from standard vector extensions. Will be added later as separate Zvamo extension, but will need a different encoding from earlier proposal. Signed-off-by: Frank Chang Reviewed-by: Alistair Francis --- target/riscv/helper.h | 27

[PATCH v11 06/77] target/riscv: rvv-1.0: introduce writable misa.v field

From: Frank Chang Implementations may have a writable misa.v field. Analogous to the way in which the floating-point unit is handled, the mstatus.vs field may exist even if misa.v is clear. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/ris

[PATCH v11 07/77] target/riscv: rvv-1.0: add translation-time vector context status

From: Frank Chang Signed-off-by: LIU Zhiwei Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu.h | 5 +- target/riscv/cpu_helper.c | 3 + target/riscv/insn_trans/trans_rvv.c.inc | 75 ++

[PATCH v11 25/77] target/riscv: rvv-1.0: update vext_max_elems() for load/store insns

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Alistair Francis --- target/riscv/insn_trans/trans_rvv.c.inc | 32 ++-- target/riscv/vector_helper.c| 99 ++--- 2 files changed, 80 insertions(+), 51 deletions(-) diff --git a/target/riscv/insn_trans

[PATCH v11 09/77] target/riscv: rvv-1.0: add vcsr register

From: LIU Zhiwei Signed-off-by: LIU Zhiwei Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu_bits.h | 7 +++ target/riscv/csr.c | 17 + 2 files changed, 24 insertions(+) diff --git a/target/riscv/cpu_bits.h

[PATCH v11 03/77] target/riscv: rvv-1.0: add mstatus VS field

From: LIU Zhiwei Signed-off-by: LIU Zhiwei Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu.h| 2 ++ target/riscv/cpu_bits.h | 1 + target/riscv/cpu_helper.c | 20 +++- target/riscv/csr.c| 12

[PATCH v11 05/77] target/riscv: rvv-1.0: add sstatus VS field

From: LIU Zhiwei Signed-off-by: LIU Zhiwei Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu_bits.h | 1 + target/riscv/csr.c | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu_bits.h b/target

[PATCH v11 29/77] target/riscv: rvv-1.0: count population in mask instruction

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/helper.h | 2 +- target/riscv/insn32.decode | 2 +- target/riscv/insn_trans/trans_rvv.c.inc | 7 --- target/riscv/vector_helper.c

[PATCH v11 11/77] target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr registers

From: Frank Chang If VS field is off, accessing vector csr registers should raise an illegal-instruction exception. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/csr.c | 5 + 1 file changed, 5 insertions(+) diff --git a/target/r

[PATCH v11 04/77] target/riscv: rvv-1.0: set mstatus.SD bit if mstatus.VS is dirty

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/csr.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 9b5bd5d7b4..bb500afdeb 100644 --- a/target/riscv/csr.c +++ b/targe

[PATCH v11 08/77] target/riscv: rvv-1.0: remove rvv related codes from fcsr registers

From: Frank Chang * Remove VXRM and VXSAT fields from FCSR register as they are only presented in VCSR register. * Remove RVV loose check in fs() predicate function. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/csr.c | 13

[PATCH v11 38/77] target/riscv: rvv-1.0: floating-point scalar move instructions

From: Frank Chang NaN-boxed the scalar floating-point register based on RVV 1.0's rules. Signed-off-by: Frank Chang Acked-by: Alistair Francis --- target/riscv/insn32.decode | 4 +-- target/riscv/insn_trans/trans_rvv.c.inc | 38 - target/riscv/internals.h

[PATCH v11 10/77] target/riscv: rvv-1.0: add vlenb register

From: Greentime Hu Signed-off-by: Greentime Hu Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu_bits.h | 1 + target/riscv/csr.c | 7 +++ 2 files changed, 8 insertions(+) diff --git a/target/riscv/cpu_bits.h b/target/riscv

[PATCH v11 12/77] target/riscv: rvv-1.0: remove MLEN calculations

From: Frank Chang As in RVV 1.0 design, MLEN is hardcoded with value 1 (Section 4.5). Thus, remove all MLEN related calculations. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/insn_trans/trans_rvv.c.inc | 35 +--- target/riscv/inter

[PATCH v11 16/77] target/riscv: introduce more imm value modes in translator functions

From: Frank Chang Immediate value in translator function is extended not only zero-extended and sign-extended but with more modes to be applicable with multiple formats of vector instructions. * IMM_ZX: Zero-extended * IMM_SX: Sign-extended * IMM_TRUNC_SEW: Truncate to log(SEW)

[PATCH v11 45/77] target/riscv: rvv-1.0: widening integer multiply-add instructions

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/insn32.decode | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index a3f1101cd6..7548b71efd 100644 --- a/target/riscv/in

[PATCH v11 15/77] target/riscv: rvv-1.0: update check functions

From: Frank Chang Update check functions with RVV 1.0 rules. Signed-off-by: Frank Chang Reviewed-by: Alistair Francis --- target/riscv/insn_trans/trans_rvv.c.inc | 715 +--- 1 file changed, 507 insertions(+), 208 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvv

[PATCH v11 23/77] target/riscv: rvv-1.0: fault-only-first unit stride load

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/helper.h | 26 ++--- target/riscv/insn32.decode | 14 ++--- target/riscv/insn_trans/trans_rvv.c.inc | 33 +++ target/riscv/vect

[PATCH v11 13/77] target/riscv: rvv-1.0: add fractional LMUL

From: Frank Chang Introduce the concepts of fractional LMUL for RVV 1.0. In RVV 1.0, LMUL bits are contiguous in vtype register. Also rearrange rvv bits in TB_FLAGS to skip MSTATUS_VS (0x600) and MSTATUS_FS (0x6000) bits. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by:

[PATCH v11 47/77] target/riscv: rvv-1.0: integer comparison instructions

From: Frank Chang * Sign-extend vmselu.vi and vmsgtu.vi immediate values. * Remove "set tail elements to zeros" as tail elements can be unchanged for either VTA to have undisturbed or agnostic setting. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/insn_trans/tra

[PATCH v11 24/77] target/riscv: rvv-1.0: load/store whole register instructions

From: Frank Chang Add the following instructions: * vlre.v * vsr.v Signed-off-by: Frank Chang Reviewed-by: Alistair Francis --- target/riscv/helper.h | 21 target/riscv/insn32.decode | 22 target/riscv/insn_trans/trans_rvv.c.inc | 68 +

[PATCH v11 50/77] target/riscv: rvv-1.0: slide instructions

From: Frank Chang * Remove clear function from helper functions as the tail elements are unchanged in RVV 1.0. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/vector_helper.c | 19 --- 1 file changed, 12 insertions(+), 7 deletions(-) diff --git a/

[PATCH v11 22/77] target/riscv: rvv-1.0: fix address index overflow bug of indexed load/store insns

From: Frank Chang Replace ETYPE from signed int to unsigned int to prevent index overflow issue, which would lead to wrong index address. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/vector_helper.c | 8 1 file changed, 4 i

[PATCH v11 17/77] target/riscv: rvv:1.0: add translation-time nan-box helper function

From: Frank Chang * Add fp16 nan-box check generator function, if a 16-bit input is not properly nanboxed, then the input is replaced with the default qnan. * Add do_nanbox() helper function to utilize gen_check_nanbox_X() to generate the NaN-boxed floating-point values based on SEW setting.

[PATCH v11 28/77] target/riscv: rvv-1.0: floating-point classify instructions

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/insn32.decode | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 92a0e6fe51..f61eaf7c6b 100

[PATCH v11 35/77] target/riscv: rvv-1.0: register gather instructions

From: Frank Chang * Add vrgatherei16.vv instruction. Signed-off-by: Frank Chang Reviewed-by: Alistair Francis --- target/riscv/helper.h | 4 target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvv.c.inc | 27 ++--- target/r

[PATCH v11 19/77] target/riscv: rvv-1.0: configure instructions

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/insn_trans/trans_rvv.c.inc | 62 +++-- target/riscv/vector_helper.c| 14 +- 2 files changed, 40 insertions(+), 36 deletions(-) diff -

[PATCH v11 26/77] target/riscv: rvv-1.0: take fractional LMUL into vector max elements calculation

From: Frank Chang Update vext_get_vlmax() and MAXSZ() to take fractional LMUL into calculation for RVV 1.0. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu.h | 27 - target/riscv/cpu_hel

[PATCH v11 37/77] target/riscv: rvv-1.0: floating-point move instruction

From: Frank Chang NaN-boxed the scalar floating-point register based on RVV 1.0's rules. Signed-off-by: Frank Chang Reviewed-by: Alistair Francis --- target/riscv/insn_trans/trans_rvv.c.inc | 16 ++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/target/riscv/insn

[PATCH v11 54/77] target/riscv: rvv-1.0: widening floating-point reduction instructions

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/insn_trans/trans_rvv.c.inc | 9 - 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index 998247d71

[PATCH v11 31/77] target/riscv: rvv-1.0: set-X-first mask bit instructions

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/insn32.decode | 6 +++--- target/riscv/insn_trans/trans_rvv.c.inc | 5 - target/riscv/vector_helper.c| 4 3 files changed, 7 insertions(

[PATCH v11 20/77] target/riscv: rvv-1.0: stride load and store instructions

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Alistair Francis --- target/riscv/helper.h | 129 ++-- target/riscv/insn32.decode | 43 ++- target/riscv/insn_trans/trans_rvv.c.inc | 376 target/riscv/vector_helper.c

[PATCH v11 55/77] target/riscv: rvv-1.0: single-width scaling shift instructions

From: Frank Chang log(SEW) truncate vssra.vi immediate value. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/insn_trans/trans_rvv.c.inc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/i

[PATCH v11 39/77] target/riscv: rvv-1.0: whole register move instructions

From: Frank Chang Add the following instructions: * vmv1r.v * vmv2r.v * vmv4r.v * vmv8r.v Signed-off-by: Frank Chang Acked-by: Alistair Francis --- target/riscv/insn32.decode | 4 target/riscv/insn_trans/trans_rvv.c.inc | 25 + 2 files changed, 29 i

[PATCH v11 33/77] target/riscv: rvv-1.0: element index instruction

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/insn32.decode | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 3ac5162aeb..ab274dcde1 100

[PATCH v11 40/77] target/riscv: rvv-1.0: integer extension instructions

From: Frank Chang Add the following instructions: * vzext.vf2 * vzext.vf4 * vzext.vf8 * vsext.vf2 * vsext.vf4 * vsext.vf8 Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/helper.h | 14 + target/riscv/insn32.decode | 8 +++ target

[PATCH v11 56/77] target/riscv: rvv-1.0: remove widening saturating scaled multiply-add

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/helper.h | 22 --- target/riscv/insn32.decode | 7 - target/riscv/insn_trans/trans_rvv.c.inc | 9 -- target/riscv/vector_helper.c| 205 --

[PATCH v11 21/77] target/riscv: rvv-1.0: index load and store instructions

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Alistair Francis --- target/riscv/helper.h | 67 +++ target/riscv/insn32.decode | 21 +++-- target/riscv/insn_trans/trans_rvv.c.inc | 110 +--- target/riscv/vector_helper.

[PATCH v11 42/77] target/riscv: rvv-1.0: single-width bit shift instructions

From: Frank Chang Truncate vsll.vi, vsrl.vi, vsra.vi's immediate values to lg2(SEW) bits. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/insn_trans/trans_rvv.c.inc | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/target/riscv/insn_trans/tra

[PATCH v11 36/77] target/riscv: rvv-1.0: integer scalar move instructions

From: Frank Chang * Remove "vmv.s.x: dothing if rs1 == 0" constraint. * Add vmv.x.s instruction. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Acked-by: Alistair Francis --- target/riscv/insn32.decode | 3 +- target/riscv/insn_trans/trans_rvv.c.inc | 43

[PATCH v11 62/77] target/riscv: rvv-1.0: widening floating-point/integer type-convert

From: Frank Chang Add the following instructions: * vfwcvt.rtz.xu.f.v * vfwcvt.rtz.x.f.v Also adjust GEN_OPFV_WIDEN_TRANS() to accept multiple floating-point rounding modes. Signed-off-by: Frank Chang Acked-by: Alistair Francis --- target/riscv/helper.h | 2 + target/risc

[PATCH v11 27/77] target/riscv: rvv-1.0: floating-point square-root instruction

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/insn32.decode | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 7d8441d1f2..92a0e6fe51 100

[PATCH v11 68/77] target/riscv: gdb: support vector registers for rv64 & rv32

From: Hsiangkai Wang Signed-off-by: Hsiangkai Wang Signed-off-by: Greentime Hu Signed-off-by: Frank Chang Acked-by: Alistair Francis --- target/riscv/cpu.c | 2 + target/riscv/cpu.h | 1 + target/riscv/gdbstub.c | 184 + 3 files changed, 18

[PATCH v11 41/77] target/riscv: rvv-1.0: single-width averaging add and subtract instructions

From: Frank Chang Add the following instructions: * vaaddu.vv * vaaddu.vx * vasubu.vv * vasubu.vx Remove the following instructions: * vadd.vi Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/helper.h | 16 ++ target/riscv/insn32.decode

[PATCH v11 46/77] target/riscv: rvv-1.0: single-width saturating add and subtract instructions

From: Frank Chang Sign-extend vsaddu.vi immediate value. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/insn_trans/trans_rvv.c.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans

[PATCH v11 30/77] target/riscv: rvv-1.0: find-first-set mask bit instruction

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/helper.h | 2 +- target/riscv/insn32.decode | 2 +- target/riscv/insn_trans/trans_rvv.c.inc | 4 ++-- target/riscv/vector_helper.c

[PATCH v11 48/77] target/riscv: rvv-1.0: floating-point compare instructions

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/vector_helper.c | 9 - 1 file changed, 9 deletions(-) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 277a5e4120..71d7b1e879 100644 --- a/target/riscv/vector_hel

[PATCH v11 49/77] target/riscv: rvv-1.0: mask-register logical instructions

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/insn_trans/trans_rvv.c.inc | 3 ++- target/riscv/vector_helper.c| 4 2 files changed, 2 insertions(+), 5 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/ri

[PATCH v11 69/77] target/riscv: rvv-1.0: floating-point reciprocal square-root estimate instruction

From: Frank Chang Implement the floating-point reciprocal square-root estimate to 7 bits instruction. Signed-off-by: Frank Chang Acked-by: Alistair Francis --- target/riscv/helper.h | 4 + target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvv.c

[PATCH v11 34/77] target/riscv: rvv-1.0: allow load element with sign-extended

From: Frank Chang For some vector instructions (e.g. vmv.s.x), the element is loaded with sign-extended. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/insn_trans/trans_rvv.c.inc | 32 + 1 file changed, 22 inse

[PATCH v11 44/77] target/riscv: rvv-1.0: narrowing integer right shift instructions

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/helper.h | 24 +++--- target/riscv/insn32.decode | 12 +++ target/riscv/insn_trans/trans_rvv.c.inc | 42 - target/riscv/vector_helper.

[PATCH v11 74/77] target/riscv: rvv-1.0: add vector unit-stride mask load/store insns

From: Frank Chang Signed-off-by: Frank Chang Acked-by: Alistair Francis --- target/riscv/helper.h | 2 ++ target/riscv/insn32.decode | 4 +++ target/riscv/insn_trans/trans_rvv.c.inc | 40 + target/riscv/vector_helper.c| 21 ++

[PATCH v11 51/77] target/riscv: rvv-1.0: floating-point slide instructions

From: Frank Chang Add the following instructions: * vfslide1up.vf * vfslide1down.vf Signed-off-by: Frank Chang Reviewed-by: Alistair Francis --- target/riscv/helper.h | 7 ++ target/riscv/insn32.decode | 2 + target/riscv/insn_trans/trans_rvv.c.inc | 16 ++

[PATCH v11 32/77] target/riscv: rvv-1.0: iota instruction

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/insn32.decode | 2 +- target/riscv/insn_trans/trans_rvv.c.inc | 10 -- 2 files changed, 9 insertions(+), 3 deletions(-) diff --git a/target/riscv/i

[PATCH v11 57/77] target/riscv: rvv-1.0: remove vmford.vv and vmford.vf

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/helper.h | 6 -- target/riscv/insn32.decode | 2 -- target/riscv/insn_trans/trans_rvv.c.inc | 2 -- target/riscv/vector_helper.c| 7 --- 4 files chang

[PATCH v11 52/77] target/riscv: rvv-1.0: narrowing fixed-point clip instructions

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/helper.h | 24 ++-- target/riscv/insn32.decode | 12 +++--- target/riscv/insn_trans/trans_rvv.c.inc | 12 +++--- target/riscv/vector_helper.c| 52

[PATCH v11 43/77] target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrow

From: Frank Chang * Only do carry-in or borrow-in if is masked (vm=0). * Remove clear function from helper functions as the tail elements are unchanged in RVV 1.0. Signed-off-by: Frank Chang Reviewed-by: Alistair Francis --- target/riscv/insn32.decode | 20 ++--

[PATCH v11 59/77] target/riscv: rvv-1.0: floating-point min/max instructions

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/vector_helper.c | 24 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index aed230e1ad..cc95b69255 1

[PATCH v11 60/77] target/riscv: introduce floating-point rounding mode enum

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/fpu_helper.c | 12 ++-- target/riscv/insn_trans/trans_rvv.c.inc | 18 +- target/riscv/internals.h| 9 + 3 files changed, 24 insertions(+),

[PATCH v11 53/77] target/riscv: rvv-1.0: single-width floating-point reduction

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/insn_trans/trans_rvv.c.inc | 12 +--- target/riscv/vector_helper.c| 12 ++-- 2 files changed, 15 insertions(+), 9 deletions(-) diff --git a/target/riscv/insn_trans/trans_rv

Re: Redesign of QEMU startup & initial configuration

On 12/9/21 20:11, Daniel P. Berrangé wrote: They still need to bootstrap a QMP monitor, and for that, CLI is fine as long as it's simple and stable. I would go a step further and say that the QMP monitor socket should be created by whoever invoked QEMU and passed down via systemd's soc

[PATCH v11 61/77] target/riscv: rvv-1.0: floating-point/integer type-convert instructions

From: Frank Chang Add the following instructions: * vfcvt.rtz.xu.f.v * vfcvt.rtz.x.f.v Also adjust GEN_OPFV_TRANS() to accept multiple floating-point rounding modes. Signed-off-by: Frank Chang Reviewed-by: Alistair Francis --- target/riscv/insn32.decode | 11 ++-- target/riscv/

[PATCH v11 65/77] target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Alistair Francis --- target/riscv/cpu.h | 2 +- target/riscv/insn_trans/trans_rvv.c.inc | 4 ++-- target/riscv/vector_helper.c| 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/target

[PATCH v11 58/77] target/riscv: rvv-1.0: remove integer extract instruction

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/insn32.decode | 1 - target/riscv/insn_trans/trans_rvv.c.inc | 23 --- 2 files changed, 24 deletions(-) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.

[PATCH v11 71/77] target/riscv: rvv-1.0: rename r2_zimm to r2_zimm11

From: Frank Chang Rename r2_zimm to r2_zimm11 for the upcoming vsetivli instruction. vsetivli has 10-bits of zimm but vsetvli has 11-bits of zimm. Signed-off-by: Frank Chang Reviewed-by: Alistair Francis --- target/riscv/insn32.decode | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)

[PATCH v11 73/77] target/riscv: rvv-1.0: add evl parameter to vext_ldst_us()

From: Frank Chang Add supports of Vector unit-stride mask load/store instructions (vlm.v, vsm.v), which has: evl (effective vector length) = ceil(env->vl / 8). The new instructions operate the same as unmasked byte loads and stores. Add evl parameter to reuse vext_ldst_us(). Signed-off-by:

[PATCH v11 63/77] target/riscv: add "set round to odd" rounding mode helper function

From: Frank Chang helper_set_rounding_mode() is responsible for SIGILL, and "round to odd" should be an interface private to translation, so add a new independent helper_set_rod_rounding_mode(). Signed-off-by: Frank Chang Acked-by: Alistair Francis --- target/riscv/fpu_helper.c | 5 + tar

[PATCH v11 72/77] target/riscv: rvv-1.0: add vsetivli instruction

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Alistair Francis --- target/riscv/insn32.decode | 2 ++ target/riscv/insn_trans/trans_rvv.c.inc | 27 + 2 files changed, 29 insertions(+) diff --git a/target/riscv/insn32.decode b/target/riscv/insn

[PATCH v1] Add dummy Aspeed AST2600 Display Port MCU (DPMCU)

AST2600 Display Port MCU introduces 0x1800~0x1803 as it's memory and io address. If guest machine try to access DPMCU memory, it will cause a fatal error. Signed-off-by: Troy Lee --- hw/arm/aspeed_ast2600.c | 8 include/hw/arm/aspeed_soc.h | 2 ++ 2 files changed, 10 inserti

[PATCH v11 75/77] target/riscv: rvv-1.0: rename vmandnot.mm and vmornot.mm to vmandn.mm and vmorn.mm

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Alistair Francis --- target/riscv/helper.h | 4 ++-- target/riscv/insn32.decode | 4 ++-- target/riscv/insn_trans/trans_rvv.c.inc | 4 ++-- target/riscv/vector_helper.c| 4 ++-- 4 files changed

[PATCH v11 64/77] target/riscv: rvv-1.0: narrowing floating-point/integer type-convert

From: Frank Chang Signed-off-by: Frank Chang Acked-by: Alistair Francis --- target/riscv/helper.h | 22 - target/riscv/insn32.decode | 15 --- target/riscv/insn_trans/trans_rvv.c.inc | 59 + target/riscv/vector_helper.c

[PATCH v11 66/77] target/riscv: rvv-1.0: implement vstart CSR

From: Frank Chang * Update and check vstart value for vector instructions. * Add whole register move instruction helper functions as we have to call helper function for case where vstart is not zero. * Remove probe_pages() calls in vector load/store instructions (except fault-only-first loads

[PATCH] configure: remove dead variables

Signed-off-by: Paolo Bonzini --- configure | 5 - 1 file changed, 5 deletions(-) diff --git a/configure b/configure index 48c21775f3..d3aac031a5 100755 --- a/configure +++ b/configure @@ -626,7 +626,6 @@ fi case $targetos in MINGW32*) mingw32="yes" - supported_os="yes" plugins="no"

[PATCH v11 67/77] target/riscv: rvv-1.0: trigger illegal instruction exception if frm is not valid

From: Frank Chang If the frm field contains an invalid rounding mode (101-111), attempting to execute any vector floating-point instruction, even those that do not depend on the rounding mode, will raise an illegal instruction exception. Call gen_set_rm() with DYN rounding mode to check and trig

Re: [PATCH 3/4] Move CONFIG_XFS handling to meson.build

On 12/10/21 08:53, Thomas Huth wrote: On 02/11/2021 12.34, Paolo Bonzini wrote: On 28/10/21 20:59, Thomas Huth wrote: Checking for xfsctl() can be done more easily in meson.build. Also, this is not a "real" feature like the other features that we provide with the "--enable-xxx" and "--disable-x

[PATCH v11 70/77] target/riscv: rvv-1.0: floating-point reciprocal estimate instruction

From: Frank Chang Implement the floating-point reciprocal estimate to 7 bits instruction. Signed-off-by: Frank Chang Acked-by: Alistair Francis --- target/riscv/helper.h | 4 + target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvv.c.inc | 1 +

[PATCH v11 76/77] target/riscv: rvv-1.0: update opivv_vadc_check() comment

From: Frank Chang Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions is moved to Section 11.4 in RVV v1.0 spec. Update the comment, no functional changes. Signed-off-by: Frank Chang Reviewed-by: Alistair Francis --- target/riscv/insn_trans/trans_rvv.c.inc | 2 +- 1 file changed

[PATCH] tests/tcg: use CONFIG_LINUX_USER, not CONFIG_LINUX

The two more or less overlap, because CONFIG_LINUX is a requirement for Linux user-mode emulation. However, CONFIG_LINUX is technically a host symbol that applies even to system emulation. Defining CONFIG_LINUX_USER, and CONFIG_BSD_USER for eventual future use, is cleaner. Signed-off-by: Paolo B

[PATCH v11 77/77] target/riscv: rvv-1.0: Add ELEN checks for widening and narrowing instructions

From: Frank Chang SEW has the limitation which cannot exceed ELEN. Widening instructions have a destination group with EEW = 2*SEW and narrowing instructions have a source operand with EEW = 2*SEW. Both of the instructions have the limitation of: 2*SEW <= ELEN. Signed-off-by: Frank Chang Acked

[PATCH] uas: add missing return

Otherwise we run the error handling code even for successful requests. Fixes: 13b250b12ad3 ("uas: add stream number sanity checks.") Reported-by: Guenter Roeck Signed-off-by: Gerd Hoffmann --- hw/usb/dev-uas.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/usb/dev-uas.c b/hw/usb/dev-uas

Re: [Libguestfs] [libnbd PATCH 00/13] libnbd patches for NBD_OPT_EXTENDED_HEADERS

On 12/04/21 00:17, Eric Blake wrote: > Available here: > https://repo.or.cz/libnbd/ericb.git/shortlog/refs/tags/exthdr-v1 > > I also want to do followup patches to teach 'nbdinfo --map' and > 'nbdcopy' to utilize 64-bit extents. > > Eric Blake (13): > golang: Simplify nbd_block_status callback

Re: [PATCH 3/4] Move CONFIG_XFS handling to meson.build

On 10/12/2021 09.39, Paolo Bonzini wrote: On 12/10/21 08:53, Thomas Huth wrote: On 02/11/2021 12.34, Paolo Bonzini wrote: On 28/10/21 20:59, Thomas Huth wrote: Checking for xfsctl() can be done more easily in meson.build. Also, this is not a "real" feature like the other features that we provi

Re: [RFC PATCH v2 34/44] target/i386/tdx: set reboot action to shutdown when tdx

On 7/23/2021 1:54 AM, Connor Kuehl wrote: On 7/7/21 7:55 PM, isaku.yamah...@gmail.com wrote: From: Isaku Yamahata In TDX CPU state is also protected, thus vcpu state can't be reset by VMM. It assumes -action reboot=shutdown instead of silently ignoring vcpu reset. TDX module spec version 3

[PATCH] configure: remove DIRS

DIRS is used to create the directory in which the LINKS symbolic links reside, or to create directories for object files. The former can be done directly in the symlinking loop, while the latter is done by Meson already, so DIRS is not necessary. Signed-off-by: Paolo Bonzini --- configure | 9 +

RE: [PATCH v1 04/12] target/riscv: Implement kvm_arch_get_registers

> -Original Message- > From: kvm-riscv [mailto:kvm-riscv-boun...@lists.infradead.org] On Behalf Of > Anup Patel > Sent: Friday, December 3, 2021 2:20 PM > To: Jiangyifei > Cc: QEMU Developers ; open list:RISC-V > ; kvm-ri...@lists.infradead.org; KVM General > ; libvir-l...@redhat.com; An

RE: [PATCH v1 06/12] target/riscv: Support start kernel directly by KVM

> -Original Message- > From: kvm-riscv [mailto:kvm-riscv-boun...@lists.infradead.org] On Behalf Of > Anup Patel > Sent: Friday, December 3, 2021 2:31 PM > To: Jiangyifei > Cc: QEMU Developers ; open list:RISC-V > ; kvm-ri...@lists.infradead.org; KVM General > ; libvir-l...@redhat.com; An

RE: [PATCH v1 05/12] target/riscv: Implement kvm_arch_put_registers

> -Original Message- > From: Anup Patel [mailto:a...@brainfault.org] > Sent: Friday, December 3, 2021 2:22 PM > To: Jiangyifei > Cc: QEMU Developers ; open list:RISC-V > ; kvm-ri...@lists.infradead.org; KVM General > ; libvir-l...@redhat.com; Anup Patel > ; Palmer Dabbelt ; Alistair > Fra

RE: [PATCH v1 12/12] target/riscv: Support virtual time context synchronization

> -Original Message- > From: Richard Henderson [mailto:richard.hender...@linaro.org] > Sent: Sunday, November 21, 2021 6:35 AM > To: Jiangyifei ; qemu-devel@nongnu.org; > qemu-ri...@nongnu.org > Cc: bin.m...@windriver.com; limingwang (A) ; > k...@vger.kernel.org; libvir-l...@redhat.com; an

RE: [PATCH v1 10/12] target/riscv: Add kvm_riscv_get/put_regs_timer

> -Original Message- > From: Anup Patel [mailto:a...@brainfault.org] > Sent: Friday, December 3, 2021 5:38 PM > To: Jiangyifei > Cc: QEMU Developers ; open list:RISC-V > ; kvm-ri...@lists.infradead.org; KVM General > ; libvir-l...@redhat.com; Anup Patel > ; Palmer Dabbelt ; Alistair > Fra

RE: [PATCH v1 07/12] target/riscv: Support setting external interrupt by KVM

> -Original Message- > From: kvm-riscv [mailto:kvm-riscv-boun...@lists.infradead.org] On Behalf Of > Anup Patel > Sent: Friday, December 3, 2021 5:15 PM > To: Jiangyifei > Cc: QEMU Developers ; open list:RISC-V > ; kvm-ri...@lists.infradead.org; KVM General > ; libvir-l...@redhat.com; An

RE: [PATCH v1 03/12] target/riscv: Implement function kvm_arch_init_vcpu

> -Original Message- > From: Richard Henderson [mailto:richard.hender...@linaro.org] > Sent: Sunday, November 21, 2021 6:19 AM > To: Jiangyifei ; qemu-devel@nongnu.org; > qemu-ri...@nongnu.org > Cc: bin.m...@windriver.com; limingwang (A) ; > k...@vger.kernel.org; libvir-l...@redhat.com; an

[PATCH v2 01/12] update-linux-headers: Add asm-riscv/kvm.h

Add asm-riscv/kvm.h for RISC-V KVM, and update linux/kvm.h Signed-off-by: Yifei Jiang Signed-off-by: Mingwang Li Acked-by: Alistair Francis Reviewed-by: Anup Patel --- linux-headers/asm-riscv/kvm.h | 128 ++ linux-headers/linux/kvm.h | 8 +++ 2 files chan

[PATCH v2 00/12] Add riscv kvm accel support

This series adds both riscv32 and riscv64 kvm support, and implements migration based on riscv. Because of RISC-V KVM has been merged into the Linux master, so this series are changed from RFC to patch. Several steps to use this: 1. Build emulation $ ./configure --target-list=riscv64-softmmu $ ma

[PATCH v2 03/12] target/riscv: Implement function kvm_arch_init_vcpu

Get isa info from kvm while kvm init. Signed-off-by: Yifei Jiang Signed-off-by: Mingwang Li Reviewed-by: Alistair Francis --- target/riscv/kvm.c | 32 +++- 1 file changed, 31 insertions(+), 1 deletion(-) diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c index 68

RE: [PATCH v1 08/12] target/riscv: Handle KVM_EXIT_RISCV_SBI exit

> -Original Message- > From: Philippe Mathieu-Daudé [mailto:philippe.mathieu.da...@gmail.com] > On Behalf Of Philippe Mathieu-Daudé > Sent: Saturday, November 20, 2021 8:25 PM > To: Jiangyifei ; qemu-devel@nongnu.org; > qemu-ri...@nongnu.org > Cc: bin.m...@windriver.com; limingwang (A) ; >

[PATCH v2 04/12] target/riscv: Implement kvm_arch_get_registers

Get GPR CSR and FP registers from kvm by KVM_GET_ONE_REG ioctl. Signed-off-by: Yifei Jiang Signed-off-by: Mingwang Li Reviewed-by: Alistair Francis --- target/riscv/kvm.c | 112 - 1 file changed, 111 insertions(+), 1 deletion(-) diff --git a/target/

[PATCH v2 02/12] target/riscv: Add target/riscv/kvm.c to place the public kvm interface

Add target/riscv/kvm.c to place kvm_arch_* function needed by kvm/kvm-all.c. Meanwhile, add kvm support in meson.build file. Signed-off-by: Yifei Jiang Signed-off-by: Mingwang Li Reviewed-by: Alistair Francis Reviewed-by: Anup Patel --- meson.build | 2 + target/riscv/kvm.c

[PATCH v2 09/12] target/riscv: Add host cpu type

'host' type cpu is set isa to RV32 or RV64 simply, more isa info will obtain from KVM in kvm_arch_init_vcpu() Signed-off-by: Yifei Jiang Signed-off-by: Mingwang Li Reviewed-by: Alistair Francis Reviewed-by: Anup Patel --- target/riscv/cpu.c | 15 +++ target/riscv/cpu.h | 1 + 2 f

[PATCH v2 07/12] target/riscv: Support setting external interrupt by KVM

When KVM is enabled, set the S-mode external interrupt through kvm_riscv_set_irq function. Signed-off-by: Yifei Jiang Signed-off-by: Mingwang Li Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 6 +- target/riscv/kvm-stub.c | 5 + target/riscv/kvm.c | 17 ++

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