On Thu, Dec 02, 2021 at 01:14:47PM +0800, Rao, Lei wrote:
> Sorry, resending with correct indentation and quoting.
>
> On 12/1/2021 10:27 PM, Vladimir Sementsov-Ogievskiy wrote:
> > 01.12.2021 12:48, Rao, Lei wrote:
> > >
> > >
> > > -Original Message-
> > > From: Daniel P. Berrangé
> >
On 7/23/2021 1:53 AM, Connor Kuehl wrote:
On 7/7/21 7:54 PM, isaku.yamah...@gmail.com wrote:
From: Xiaoyao Li
Reuse -cpu,tsc-frequency= to get user wanted tsc frequency and pass it
to KVM_TDX_INIT_VM.
Besides, sanity check the tsc frequency to be in the legal range and
legal granularity (requ
On 01/12/2021 19.45, Collin Walling wrote:
Polite ping. I may have missed if this patch was picked already. Thanks!
I've already queued it to my s390x-next branch:
https://gitlab.com/thuth/qemu/-/commits/s390x-next/
It just came in very late for 6.2, and it didn't seem too critical to me, so
02.12.2021 11:53, Daniel P. Berrangé wrote:
On Thu, Dec 02, 2021 at 01:14:47PM +0800, Rao, Lei wrote:
Sorry, resending with correct indentation and quoting.
On 12/1/2021 10:27 PM, Vladimir Sementsov-Ogievskiy wrote:
01.12.2021 12:48, Rao, Lei wrote:
-Original Message-
From: Daniel P
On Thu, Dec 02, 2021 at 02:50:34AM +0800, 罗勇刚(Yonggang Luo) wrote:
> On Wed, Nov 24, 2021 at 7:06 PM Gerd Hoffmann wrote:
> >
> > qemu -display egl-headless
>
> Thanks a lot, I tried this, and it's forced me to provide rendernode
> option like this:
> ```
> -display egl-headless,rendernode=/dev/
I fat-fingered Edgar's e-mail address. Sorry for the inconvenience.
On Mon, 1 Feb 2021 16:59:31 -0800
Ben Widawsky wrote:
> This cleanup will make it easier to add support for CXL to the mix.
>
> Signed-off-by: Ben Widawsky
Hi Ben / all (particularly PCI experts!)
So... I was looking at the large impact this has on needing to update
ACPI tables for the tests
On 11/29/21 13:58, Alex Bennée wrote:
>
> Juro Bystricky writes:
>
>> Fix compiler warnings. The warnings can result in a broken build.
>> This patch fixes warnings such as:
>
> Queued to for-6.2/more-misc-fixes, thanks.
I wondered if this single patch would justify delaying the 6.2
release by
在2021年11月30日十一月 下午9:52，Philippe Mathieu-Daudé写道：
> On 11/30/21 22:17, Jiaxun Yang wrote:
>> bl_gen_write_ulong uses sd for both 32 and 64 bit CPU,
>> while sd is illegal on 32 bit CPUs.
>>
>> Replace sd with sw on 32bit CPUs.
>>
>> Fixes: 3ebbf86 ("hw/mips: Add a bootloader helper")
>> Signed-
On Mon, Nov 29, 2021 at 02:05:08PM +, Daniel P. Berrangé wrote:
> Currently QEMU defaults to a resolution of 1024x768 when exposing EDID
> info to the guest OS. The EDID default info is important as this will
> influence what resolution many guest OS will configure the screen with
> on boot. It
On Mon, 29 Nov 2021 at 14:13, Daniel P. Berrangé wrote:
> This patch thus suggests a modest change to 1280x800 (WXGA).
Does this change need to be versioned so as to not change
behaviour for older machine types ?
thanks
-- PMM
On Thu, Dec 02, 2021 at 11:00:53AM +, Peter Maydell wrote:
> On Mon, 29 Nov 2021 at 14:13, Daniel P. Berrangé wrote:
> > This patch thus suggests a modest change to 1280x800 (WXGA).
>
> Does this change need to be versioned so as to not change
> behaviour for older machine types ?
I don't th
Philippe Mathieu-Daudé writes:
> On 11/29/21 13:58, Alex Bennée wrote:
>>
>> Juro Bystricky writes:
>>
>>> Fix compiler warnings. The warnings can result in a broken build.
>>> This patch fixes warnings such as:
>>
>> Queued to for-6.2/more-misc-fixes, thanks.
>
> I wondered if this single
* Juan Quintela (quint...@redhat.com) wrote:
> This patch adds counters and similar. Logic will be added on the
> following patch.
>
> Signed-off-by: Juan Quintela
> ---
> migration/multifd.h| 13 -
> migration/multifd.c| 22 +++---
> migration/trace-events |
Hi,
> The virtio-gpu change I'm not so sure about - it feeds into the
> EDID code, but not sure if it has other consequences that matter
> from a guest ABI pov.
virtio-gpu has two ways to query the display resolution (one predating
edid support), the change will affect both. The effect will be
"Dr. David Alan Gilbert" wrote:
> * Juan Quintela (quint...@redhat.com) wrote:
>> This patch adds counters and similar. Logic will be added on the
>> following patch.
>>
>> Signed-off-by: Juan Quintela
>> ---
>> migration/multifd.h| 13 -
>> migration/multifd.c| 22
Leonardo Bras Soares Passos wrote:
> On Tue, Nov 16, 2021 at 1:08 PM Juan Quintela wrote:
>>
>> I would prefer to check for QIO_CHANNEL_FEATUR_WRITE_ZEROCPY there, but
>> I can't see a way of doing that without a qio.
>
> Yeah, I think I should leave the feature testing in here, and move the
> pa
On Wed, Dec 01, 2021 at 12:55:08PM +0100, Stefano Garzarella wrote:
> On Tue, Nov 30, 2021 at 11:20:57AM +, Stefan Hajnoczi wrote:
> > @@ -657,10 +704,7 @@ bool aio_poll(AioContext *ctx, bool blocking)
> > }
> >
> > progress |= aio_bh_poll(ctx);
> > -
> > -if (ret > 0) {
> > -
On Wed, Dec 01, 2021 at 07:24:33PM +0100, Florian Weimer wrote:
> * Stefan Hajnoczi:
>
> > +#elif defined(__x86_64__)
> > +#define QEMU_CO_TLS_ADDR(ret, var) \
> > +asm volatile("rdfsbase %0\n\t" \
> > + "lea "#var"@tpof
On Thu, Dec 02, 2021 at 01:09:23PM +, Stefan Hajnoczi wrote:
On Wed, Dec 01, 2021 at 12:55:08PM +0100, Stefano Garzarella wrote:
On Tue, Nov 30, 2021 at 11:20:57AM +, Stefan Hajnoczi wrote:
> @@ -657,10 +704,7 @@ bool aio_poll(AioContext *ctx, bool blocking)
> }
>
> progress |= a
All POWER8 machines have a maximum of 3 PHB3 devices. Adapt the
PNV8_CHIP_PHB3_MAX definition for consistency.
Signed-off-by: Cédric Le Goater
---
include/hw/ppc/pnv.h | 2 +-
hw/ppc/pnv.c | 6 +++---
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/include/hw/ppc/pnv.h b/i
It is never used.
Signed-off-by: Cédric Le Goater
---
hw/ppc/pnv.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index bd768dcc28ad..988b305398b2 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -1764,7 +1764,6 @@ static Property pnv_chip_properties[] = {
DEF
POWER9 processor comes with 3 PHB4 PECs (PCI Express Controller) and
each PEC can have several PHBs :
* PEC0 provides 1 PHB (PHB0)
* PEC1 provides 2 PHBs (PHB1 and PHB2)
* PEC2 provides 3 PHBs (PHB3, PHB4 and PHB5)
A num_pecs class attribute represents better the logic units of the
POWER9
This requires a link to the chip to add the regions under the XSCOM
address space. This change will help us providing support for user
created PHB3 devices.
Signed-off-by: Cédric Le Goater
---
include/hw/pci-host/pnv_phb3.h | 3 +++
hw/pci-host/pnv_phb3.c | 1 +
hw/pci-host/pnv_phb3_pb
Hello,
On the POWER8 processor, powernv8 machine, PHB3 devices can simply be
created with :
-device pnv-phb3,chip-id=0,index=1
with a maximum of 3 PHB3s per chip, each PHB3 adding a new PCIe bus.
On the POWER9 processor, powernv9 machine, the logic is different. The
the chip comes with 3 PH
The powernv machine uses the object hierarchy to populate the device
tree and each device should be parented to the chip it belongs to.
This is not the case for user created devices which are parented to
the container "/unattached".
Make sure a PHB3 device is parented to its chip by reparenting th
PHB3 devices and PCI devices can now be added to the powernv8 machine
using :
-device pnv-phb3,chip-id=0,index=1 \
-device nec-usb-xhci,bus=pci.1,addr=0x0
The 'index' property identifies the PHB3 in the chip. In case of user
created devices, a lookup on 'chip-id' is required to assign the
own
Next changes will make use of it.
Signed-off-by: Cédric Le Goater
---
include/hw/pci-host/pnv_phb4.h | 2 ++
hw/pci-host/pnv_phb4_pec.c | 2 ++
hw/ppc/pnv.c | 2 ++
3 files changed, 6 insertions(+)
diff --git a/include/hw/pci-host/pnv_phb4.h b/include/hw/pci-host/pnv_phb4.
Signed-off-by: Cédric Le Goater
---
include/hw/pci-host/pnv_phb4.h | 2 ++
hw/pci-host/pnv_phb4_pec.c | 2 ++
hw/ppc/pnv.c | 4 ++--
3 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/include/hw/pci-host/pnv_phb4.h b/include/hw/pci-host/pnv_phb4.h
index 27556ae53
PHB3s ared SysBus devices and should be allowed to be dynamically
created.
Signed-off-by: Cédric Le Goater
---
hw/pci-host/pnv_phb3.c | 9 +
hw/ppc/pnv.c | 2 ++
2 files changed, 11 insertions(+)
diff --git a/hw/pci-host/pnv_phb3.c b/hw/pci-host/pnv_phb3.c
index e91f658b0060..
Each PEC devices of the POWER9 chip has a predefined number of stacks,
equivalent of a root port complex:
PEC0 -> 1 stack
PEC1 -> 2 stacks
PEC2 -> 3 stacks
Introduce a class attribute to hold these values and remove the
"num-stacks" property.
Signed-off-by: Cédric Le Goater
---
include/h
This is not useful and will be in the way for support of user created
PHB4 devices.
Signed-off-by: Cédric Le Goater
---
hw/pci-host/pnv_phb4_pec.c | 6 +-
hw/ppc/pnv.c | 2 --
2 files changed, 1 insertion(+), 7 deletions(-)
diff --git a/hw/pci-host/pnv_phb4_pec.c b/hw/pci-host
On Thu, 2 Dec 2021 at 14:44, Peter Maydell wrote:
> My compiler-developer colleagues present the following case where
> 'noinline' is not sufficient for the compiler to definitely
> use different values of the address-of-the-TLS-var across an
> intervening function call:
>
> __thread int i;
>
>
Use the num_stacks class attribute to compute the PHB index depending
on the PEC index :
* PEC0 provides 1 PHB (PHB0)
* PEC1 provides 2 PHBs (PHB1 and PHB2)
* PEC2 provides 3 PHBs (PHB3, PHB4 and PHB5)
Signed-off-by: Cédric Le Goater
---
hw/pci-host/pnv_phb4_pec.c | 16
On Wed, 1 Dec 2021 at 17:19, Stefan Hajnoczi wrote:
>
> Compiler optimizations can cache TLS values across coroutine yield
> points, resulting in stale values from the previous thread when a
> coroutine is re-entered by a new thread.
>
> Serge Guelton developed an __attribute__((noinline)) wrapper
This change will help us providing support for user created PHB4
devices.
Signed-off-by: Cédric Le Goater
---
hw/pci-host/pnv_phb4_pec.c | 36
hw/ppc/pnv.c | 31 +--
2 files changed, 33 insertions(+), 34 deletions(-)
* Peter Maydell:
> On Thu, 2 Dec 2021 at 14:44, Peter Maydell wrote:
>> My compiler-developer colleagues present the following case where
>> 'noinline' is not sufficient for the compiler to definitely
>> use different values of the address-of-the-TLS-var across an
>> intervening function call:
>>
PHB4 devices and PCI devices can now be added to the powernv9 machine
using:
-device pnv-phb4-pec,chip-id=0,index=0
-device nec-usb-xhci,bus=pci.0,addr=0x0
In case of user created devices, a lookup on 'chip-id' is required to
assign the owning chip.
To be noted, that the PEC PHB4 devices can
v2:
- Cleaned up unused return values in nvme and virtio-blk [Stefano]
- Documented try_poll_mode() ready_list argument [Stefano]
- Unified virtio-blk/scsi dataplane and non-dataplane virtqueue handlers
[Stefano]
The first patch improves AioContext's adaptive polling execution time
measurement. T
On Mittwoch, 1. Dezember 2021 23:46:43 CET Will Cohen wrote:
> On Wed, Nov 24, 2021 at 9:23 AM Christian Schoenebeck <
>
> qemu_...@crudebyte.com> wrote:
> > On Montag, 22. November 2021 01:49:05 CET Will Cohen wrote:
> > > From: Keno Fischer
> > >
> > > Signed-off-by: Keno Fischer
> > > Signed
The virtqueue host notifier API
virtio_queue_aio_set_host_notifier_handler() polls the virtqueue for new
buffers. AioContext previously required a bool progress return value
indicating whether an event was handled or not. This is no longer
necessary because the AioContext polling API has been split
Adaptive polling measures the execution time of the polling check plus
handlers called when a polled event becomes ready. Handlers can take a
significant amount of time, making it look like polling was running for
a long time when in fact the event handler was running for a long time.
For example,
The difference between ->handle_output() and ->handle_aio_output() was
that ->handle_aio_output() returned a bool return value indicating
progress. This was needed by the old polling API but now that the bool
return value is gone, the two functions can be unified.
Signed-off-by: Stefan Hajnoczi
-
Now that virtio-blk and virtio-scsi are ready, get rid of
the handle_aio_output() callback. It's no longer needed.
Signed-off-by: Stefan Hajnoczi
---
include/hw/virtio/virtio.h | 4 +--
hw/block/dataplane/virtio-blk.c | 16 ++
hw/scsi/virtio-scsi-dataplane.c | 54 --
The return value of virtio_blk_handle_vq() is no longer used. Get rid of
it. This is a step towards unifying the dataplane and non-dataplane
virtqueue handler functions.
Prepare virtio_blk_handle_output() to be used by both dataplane and
non-dataplane by making the condition for starting ioeventfd
Prepare virtio_scsi_handle_cmd() to be used by both dataplane and
non-dataplane by making the condition for starting ioeventfd more
specific. This way it won't trigger when dataplane has already been
started.
Signed-off-by: Stefan Hajnoczi
---
hw/scsi/virtio-scsi.c | 2 +-
1 file changed, 1 inse
Not sure if this is related, but builds are failing with:
FAILED: libblockdev.fa.p/block_export_fuse.c.o
cc -m64 -mcx16 -Ilibblockdev.fa.p -I. -I.. -Iqapi -Itrace -Iui -Iui/shader
-I/usr/include/fuse3 -I/usr/include/p11-kit-1 -I/usr/include/glib-2.0
-I/usr/lib64/glib-2.0/include -I/usr/includ
On 12/2/21 04:23, Thomas Huth wrote:
> On 01/12/2021 19.45, Collin Walling wrote:
>> Polite ping. I may have missed if this patch was picked already. Thanks!
>
> I've already queued it to my s390x-next branch:
>
> https://gitlab.com/thuth/qemu/-/commits/s390x-next/
>
> It just came in very late
On Thu, Dec 02, 2021 at 03:49:08PM +, Richard W.M. Jones wrote:
>
> Not sure if this is related, but builds are failing with:
>
> FAILED: libblockdev.fa.p/block_export_fuse.c.o
> cc -m64 -mcx16 -Ilibblockdev.fa.p -I. -I.. -Iqapi -Itrace -Iui -Iui/shader
> -I/usr/include/fuse3 -I/usr/include
huang...@chinatelecom.cn writes:
> From: Hyman Huang(黄勇)
>
> Implement dirtyrate calculation periodically basing on
> dirty-ring and throttle vCPU until it reachs the quota
> dirty page rate given by user.
>
> Introduce qmp commands set-dirty-limit/cancel-dirty-limit to
> set/cancel dirty page li
Vasilev Oleg writes:
> Hi everyone,
>
> I've recently been tasked with improving QEMU performance and would like
> to discuss several possible optimizations which we could implement and
> later upstream.
Excellent - it's always good to see others that want to improve our
emulation performance
* Juan Quintela (quint...@redhat.com) wrote:
> "Dr. David Alan Gilbert" wrote:
> > * Juan Quintela (quint...@redhat.com) wrote:
> >> This patch adds counters and similar. Logic will be added on the
> >> following patch.
> >>
> >> Signed-off-by: Juan Quintela
> >> ---
> >> migration/multifd.h
"Dr. David Alan Gilbert" wrote:
> * Juan Quintela (quint...@redhat.com) wrote:
>> "Dr. David Alan Gilbert" wrote:
>> > * Juan Quintela (quint...@redhat.com) wrote:
>> >> This patch adds counters and similar. Logic will be added on the
>> >> following patch.
>> >>
>> >> Signed-off-by: Juan Quint
The current default PCI group being used can technically collide with a
real group ID passed from a hostdev. Let's instead use a group ID that comes
from a special pool that is architected to be reserved for simulated devices.
Fixes: 28dc86a072 ("s390x/pci: use a PCI Group structure")
Signed-off-
Instead use the values from clp info, they will either be the hard-coded
values or what came from the host driver via vfio.
Fixes: 9670ee752727 ("s390x/pci: use a PCI Function structure")
Signed-off-by: Matthew Rosato
---
hw/s390x/s390-pci-inst.c | 9 +
1 file changed, 5 insertions(+), 4
A collection of small fixes for s390x PCI (not urgent). The first 3 are
fixes related to always using the host-provided CLP value when provided
vs a hard-coded value. The last patch adds logic for QEMU to report a
proper DTSM clp response rather than just 0s (guest linu
We may have gotten a measurement update interval from the underlying host
via vfio -- Use it to set the interval via which we update the function
measurement block.
Fixes: 28dc86a072 ("s390x/pci: use a PCI Group structure")
Signed-off-by: Matthew Rosato
---
hw/s390x/s390-pci-inst.c | 5 +++--
1
The DTSM is a mask that specifies which I/O Address Translation designation
types are supported. A linux guest today does not look at this field but
could in the future; let's advertise what QEMU actually supports.
Signed-off-by: Matthew Rosato
---
hw/s390x/s390-pci-bus.c | 1 +
hw/s390
On 02.12.21 17:41, Matthew Rosato wrote:
> The current default PCI group being used can technically collide with a
> real group ID passed from a hostdev. Let's instead use a group ID that comes
> from a special pool that is architected to be reserved for simulated devices.
>
> Fixes: 28dc86a072 (
* Juan Quintela (quint...@redhat.com) wrote:
> This implements the zero page dection and handling.
>
> Signed-off-by: Juan Quintela
> ---
> migration/multifd.c | 33 +++--
> 1 file changed, 31 insertions(+), 2 deletions(-)
>
> diff --git a/migration/multifd.c b/migra
* Juan Quintela (quint...@redhat.com) wrote:
> "Dr. David Alan Gilbert" wrote:
> > * Juan Quintela (quint...@redhat.com) wrote:
> >> "Dr. David Alan Gilbert" wrote:
> >> > * Juan Quintela (quint...@redhat.com) wrote:
> >> >> This patch adds counters and similar. Logic will be added on the
> >> >
Sorry... I missed copy maintainers and qemu-stable. This should be
considered a regression.
-- Forwarded message -
From: Mark Mielke
Date: Thu, Dec 2, 2021 at 11:26 AM
Subject: [PATCH] virtio-blk: Fix clean up of host notifiers for single
MR transaction.
To:
The code that intro
This reverts commit 7852a77f598635a67a222b6c1463c8b46098aed2.
The check is bogus as it ends up finding itself and falling over.
Signed-off-by: Alex Bennée
Resolves: https://gitlab.com/qemu-project/qemu.git/-/issues/733
---
hw/display/vga-isa.c | 10 --
1 file changed, 10 deletions(-)
d
"Dr. David Alan Gilbert" wrote:
> * Juan Quintela (quint...@redhat.com) wrote:
>> This implements the zero page dection and handling.
>>
>> Signed-off-by: Juan Quintela
>> ---
>> migration/multifd.c | 33 +++--
>> 1 file changed, 31 insertions(+), 2 deletions(-)
>>
"Dr. David Alan Gilbert" wrote:
> * Juan Quintela (quint...@redhat.com) wrote:
>> "Dr. David Alan Gilbert" wrote:
>> > * Juan Quintela (quint...@redhat.com) wrote:
>> >> "Dr. David Alan Gilbert" wrote:
>> >> > * Juan Quintela (quint...@redhat.com) wrote:
>> >> >> This patch adds counters and sim
On Thu, Dec 02, 2021 at 04:49:29PM +, Alex Bennée wrote:
> This reverts commit 7852a77f598635a67a222b6c1463c8b46098aed2.
>
> The check is bogus as it ends up finding itself and falling over.
>
> Signed-off-by: Alex Bennée
> Resolves: https://gitlab.com/qemu-project/qemu.git/-/issues/733
> --
The code that introduced "virtio-blk: Configure all host notifiers in
a single MR transaction" introduced a second loop variable to perform
cleanup in second loop, but mistakenly still refers to the first
loop variable within the second loop body.
Fixes: d0267da61489 ("virtio-blk: Configure all ho
From: Hyman Huang(黄勇)
Introduce the third method GLOBAL_DIRTY_LIMIT of dirty
tracking for calculate dirtyrate periodly for dirty restraint.
Implement thread for calculate dirtyrate periodly, which will
be used for dirty restraint.
Add dirtylimit.h to introduce the util function for dirty
limit
From: Hyman Huang(黄勇)
Impose dirty restraint on vCPU by kicking it and sleep
as the auto-converge does during migration, but just
kick the specified vCPU instead, not all vCPUs of vm.
Start a thread to track the dirtylimit status and adjust
the throttle pencentage dynamically depend on current
a
From: Hyman Huang(黄勇)
v8:
- rebase on master
- polish the error message and remove the "unlikely" compilation syntax
according to the advice given by Markus.
- keep the dirty tracking enabled during "dirtylimit-calc" lifecycle
so that the overhead can be reduced according to the advice given
From: Hyman Huang(黄勇)
Implement dirtyrate calculation periodically basing on
dirty-ring and throttle vCPU until it reachs the quota
dirty page rate given by user.
Introduce qmp commands "vcpu-dirty-limit", "query-vcpu-dirty-limit"
to enable, disable, query dirty page limit for virtual CPU.
Mean
On Thu, Dec 02 2021, Alex Bennée wrote:
> This reverts commit 7852a77f598635a67a222b6c1463c8b46098aed2.
>
> The check is bogus as it ends up finding itself and falling over.
>
> Signed-off-by: Alex Bennée
> Resolves: https://gitlab.com/qemu-project/qemu.git/-/issues/733
> ---
> hw/display/vga-i
On 12/2/21 11:43 AM, David Hildenbrand wrote:
On 02.12.21 17:41, Matthew Rosato wrote:
The current default PCI group being used can technically collide with a
real group ID passed from a hostdev. Let's instead use a group ID that comes
from a special pool that is architected to be reserved for
* Juan Quintela (quint...@redhat.com) wrote:
> So we use multifd to transmit zero pages.
>
> Signed-off-by: Juan Quintela
> ---
> migration/ram.c | 22 +++---
> 1 file changed, 11 insertions(+), 11 deletions(-)
>
> diff --git a/migration/ram.c b/migration/ram.c
> index 57efa67f2
On 12/2/21 11:42, Cédric Le Goater wrote:
All POWER8 machines have a maximum of 3 PHB3 devices. Adapt the
PNV8_CHIP_PHB3_MAX definition for consistency.
I suggest "3 PHB3 devices per chip" for clarity.
Signed-off-by: Cédric Le Goater
---
Reviewed-by: Daniel Henrique Barboza
includ
On 12/2/21 11:42, Cédric Le Goater wrote:
It is never used.
Signed-off-by: Cédric Le Goater
---
Reviewed-by: Daniel Henrique Barboza
hw/ppc/pnv.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index bd768dcc28ad..988b305398b2 100644
--- a/hw/ppc/pnv.c
On 12/2/21 11:42, Cédric Le Goater wrote:
This requires a link to the chip to add the regions under the XSCOM
address space. This change will help us providing support for user
created PHB3 devices.
Signed-off-by: Cédric Le Goater
---
Reviewed-by: Daniel Henrique Barboza
include/hw/pc
On 12/2/21 11:42, Cédric Le Goater wrote:
PHB3 devices and PCI devices can now be added to the powernv8 machine
using :
-device pnv-phb3,chip-id=0,index=1 \
-device nec-usb-xhci,bus=pci.1,addr=0x0
The 'index' property identifies the PHB3 in the chip. In case of user
created devices, a
On 12/2/21 11:42, Cédric Le Goater wrote:
The powernv machine uses the object hierarchy to populate the device
tree and each device should be parented to the chip it belongs to.
This is not the case for user created devices which are parented to
the container "/unattached".
Make sure a PHB3 d
On 12/2/21 11:42, Cédric Le Goater wrote:
PHB3s ared SysBus devices and should be allowed to be dynamically
created.
Signed-off-by: Cédric Le Goater
---
Reviewed-by: Daniel Henrique Barboza
hw/pci-host/pnv_phb3.c | 9 +
hw/ppc/pnv.c | 2 ++
2 files changed, 11 inse
On 12/2/21 11:42, Cédric Le Goater wrote:
POWER9 processor comes with 3 PHB4 PECs (PCI Express Controller) and
each PEC can have several PHBs :
* PEC0 provides 1 PHB (PHB0)
* PEC1 provides 2 PHBs (PHB1 and PHB2)
* PEC2 provides 3 PHBs (PHB3, PHB4 and PHB5)
A num_pecs class attribut
"Dr. David Alan Gilbert" wrote:
> * Juan Quintela (quint...@redhat.com) wrote:
>> So we use multifd to transmit zero pages.
>>
>> Signed-off-by: Juan Quintela
>> ---
>> migration/ram.c | 22 +++---
>> 1 file changed, 11 insertions(+), 11 deletions(-)
>>
>> diff --git a/migratio
On 12/2/21 11:42, Cédric Le Goater wrote:
Next changes will make use of it.
Signed-off-by: Cédric Le Goater
---
Reviewed-by: Daniel Henrique Barboza
include/hw/pci-host/pnv_phb4.h | 2 ++
hw/pci-host/pnv_phb4_pec.c | 2 ++
hw/ppc/pnv.c | 2 ++
3 files changed,
On 12/2/21 12:08, Alex Bennée wrote:
> Philippe Mathieu-Daudé writes:
>> On 11/29/21 13:58, Alex Bennée wrote:
>>>
>>> Juro Bystricky writes:
>>>
Fix compiler warnings. The warnings can result in a broken build.
This patch fixes warnings such as:
>>>
>>> Queued to for-6.2/more-misc-fixe
On 12/2/21 11:42, Cédric Le Goater wrote:
Each PEC devices of the POWER9 chip has a predefined number of stacks,
s/devices/device ?
equivalent of a root port complex:
PEC0 -> 1 stack
PEC1 -> 2 stacks
PEC2 -> 3 stacks
Introduce a class attribute to hold these values and remove th
On 12/2/21 11:42, Cédric Le Goater wrote:
Use the num_stacks class attribute to compute the PHB index depending
on the PEC index :
* PEC0 provides 1 PHB (PHB0)
* PEC1 provides 2 PHBs (PHB1 and PHB2)
* PEC2 provides 3 PHBs (PHB3, PHB4 and PHB5)
Signed-off-by: Cédric Le Goater
---
On 12/2/21 11:42, Cédric Le Goater wrote:
This change will help us providing support for user created PHB4
devices.
Signed-off-by: Cédric Le Goater
---
Reviewed-by: Daniel Henrique Barboza
hw/pci-host/pnv_phb4_pec.c | 36
hw/ppc/pnv.c
On 12/2/21 11:42, Cédric Le Goater wrote:
This is not useful and will be in the way for support of user created
PHB4 devices.
Signed-off-by: Cédric Le Goater
---
Reviewed-by: Daniel Henrique Barboza
hw/pci-host/pnv_phb4_pec.c | 6 +-
hw/ppc/pnv.c | 2 --
2 files ch
* Juan Quintela (quint...@redhat.com) wrote:
> "Dr. David Alan Gilbert" wrote:
> > * Juan Quintela (quint...@redhat.com) wrote:
> >> So we use multifd to transmit zero pages.
> >>
> >> Signed-off-by: Juan Quintela
> >> ---
> >> migration/ram.c | 22 +++---
> >> 1 file changed, 1
On 12/2/21 18:27, Daniel Henrique Barboza wrote:
On 12/2/21 11:42, Cédric Le Goater wrote:
All POWER8 machines have a maximum of 3 PHB3 devices. Adapt the
PNV8_CHIP_PHB3_MAX definition for consistency.
I suggest "3 PHB3 devices per chip" for clarity.
Fixed.
Thanks,
C.
Signed-off-by:
On 12/2/21 17:49, Alex Bennée wrote:
> This reverts commit 7852a77f598635a67a222b6c1463c8b46098aed2.
>
> The check is bogus as it ends up finding itself and falling over.
>
> Signed-off-by: Alex Bennée
> Resolves: https://gitlab.com/qemu-project/qemu.git/-/issues/733
This link gives 404. The co
On 12/2/21 11:42, Cédric Le Goater wrote:
PHB4 devices and PCI devices can now be added to the powernv9 machine
using:
-device pnv-phb4-pec,chip-id=0,index=0
-device nec-usb-xhci,bus=pci.0,addr=0x0
In case of user created devices, a lookup on 'chip-id' is required to
assign the owning
On 12/2/21 11:42, Cédric Le Goater wrote:
Signed-off-by: Cédric Le Goater
---
Reviewed-by: Daniel Henrique Barboza
include/hw/pci-host/pnv_phb4.h | 2 ++
hw/pci-host/pnv_phb4_pec.c | 2 ++
hw/ppc/pnv.c | 4 ++--
3 files changed, 6 insertions(+), 2 deletions(-)
On 12/2/21 11:51, Jiaxun Yang wrote:
> 在2021年11月30日十一月 下午9:52，Philippe Mathieu-Daudé写道：
>> On 11/30/21 22:17, Jiaxun Yang wrote:
>>> bl_gen_write_ulong uses sd for both 32 and 64 bit CPU,
>>> while sd is illegal on 32 bit CPUs.
>>>
>>> Replace sd with sw on 32bit CPUs.
>>>
>>> Fixes: 3ebbf86 ("hw/m
On 11/30/21 22:17, Jiaxun Yang wrote:
> Two problems caught when I was trying to add CI job for various
> configurations.
>
> Jiaxun Yang (2):
> hw/mips: bootloader: Fix write_ulong
> hw/mips/boston: Fix elf_load error detection
Thanks, queued to mips-fixes.
On 02/12/2021 17:14, Cornelia Huck wrote:
On Thu, Dec 02 2021, Alex Bennée wrote:
This reverts commit 7852a77f598635a67a222b6c1463c8b46098aed2.
The check is bogus as it ends up finding itself and falling over.
Signed-off-by: Alex Bennée
Resolves: https://gitlab.com/qemu-project/qemu.git/-/
Following the guidelines in tests/qtest/bios-tables-test.c, this
change adds empty placeholder files per step 1 for the new ERST
table, and excludes resulting changed files in bios-tables-test-allowed-diff.h
per step 2.
Signed-off-by: Eric DeVolder
Acked-by: Igor Mammedov
---
tests/data/acpi/mi
Information on the implementation of the ACPI ERST support.
Signed-off-by: Eric DeVolder
Acked-by: Ani Sinha
---
docs/specs/acpi_erst.rst | 200 +++
1 file changed, 200 insertions(+)
create mode 100644 docs/specs/acpi_erst.rst
diff --git a/docs/spec
This implements a PCI device for ACPI ERST. This implements the
non-NVRAM "mode" of operation for ERST as it is supported by
Linux and Windows.
Signed-off-by: Eric DeVolder
---
hw/acpi/Kconfig | 6 +
hw/acpi/erst.c | 836 +++
hw/acpi/m
This change provides a qtest that locates and then does a simple
interrogation of the ERST feature within the guest.
Signed-off-by: Eric DeVolder
---
tests/qtest/erst-test.c | 167
tests/qtest/meson.build | 2 +
2 files changed, 169 insertions(+
1 - 100 of 163 matches
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