On 11/19/21 7:13 AM, Song Gao wrote:
+static bool gen_rr(DisasContext *ctx, arg_rr *a,
+ DisasExtend src_ext, DisasExtend dst_ext,
+ void (*func)(TCGv, TCGv))
+{
+TCGv dest = gpr_dst(ctx, a->rd, dst_ext);
+TCGv src1 = gpr_src(ctx, a->rj, src_ext);
+
+
On 11/19/21 7:13 AM, Song Gao wrote:
DEF_HELPER_FLAGS_1(bitswap, TCG_CALL_NO_RWG_SE, tl, tl)
+
+DEF_HELPER_3(asrtle_d, void, env, tl, tl)
+DEF_HELPER_3(asrtgt_d, void, env, tl, tl)
Use DEF_HELPER_FLAGS_3 and TCG_CALL_NO_WG.
(They do not write globals, but do implicitly read them via the exce
On 11/19/21 7:13 AM, Song Gao wrote:
This includes:
- LL.{W/D}, SC.{W/D}
- AM{SWAP/ADD/AND/OR/XOR/MAX/MIN}[_DB].{W/D}
- AM{MAX/MIN}[_DB].{WU/DU}
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
Reviewed-by: Richard Henderson
---
target/loongarch/insn_trans/trans_atomic.c.inc | 130 +
On 11/19/21 7:13 AM, Song Gao wrote:
+DEF_HELPER_3(crc32, tl, tl, tl, tl)
+DEF_HELPER_3(crc32c, tl, tl, tl, tl)
+DEF_HELPER_2(cpucfg, tl, env, tl)
DEF_HELPER_FLAGS_N, TCG_CALL_NO_RWG_SE.
+target_ulong helper_cpucfg(CPULoongArchState *env, target_ulong rj)
+{
+return env->cpucfg[rj];
+}
Hi Richard,
On 2021/11/20 下午3:17, Richard Henderson wrote:
On 11/19/21 7:13 AM, Song Gao wrote:
+static bool gen_rrr(DisasContext *ctx, arg_rrr *a,
+ DisasExtend src1_ext, DisasExtend src2_ext,
+ DisasExtend dst_ext, void (*func)(TCGv, TCGv,
TCGv))
+{
+
On 11/19/21 7:13 AM, Song Gao wrote:
+static void update_fcsr0_mask(CPULoongArchState *env, uintptr_t pc, int mask)
+{
+int flags = get_float_exception_flags(&env->fp_status);
+
+set_float_exception_flags(0, &env->fp_status);
+
+if (~mask) {
+flags = flags & (~mask);
+}
On 11/20/21 9:52 AM, gaosong wrote:
You're right, gen_set_gpr not need EXT_NONE at all, and we need not condition
around gen_set_gpr.
I think that if we know the dst_ext is EXT_NONE, we do't need gen_set_gpr.
But that assumes that gpr_dst did not return a temporary.
I think it's cleaner to ass
Damien Hedde writes:
> Hi all,
>
> This series adds support for cold-plugging devices using QMP
> commands. It is a step towards machine configuration using QMP, but
> it does not allow the user to add more devices than he could do with
> the CLI options before.
>
> Right now we can add a device
On 11/19/21 7:13 AM, Song Gao wrote:
+static bool trans_fcmp_cond_s(DisasContext *ctx, arg_fcmp_cond_s *a)
+{
+TCGv var = tcg_temp_new();
+uint32_t flags;
+void (*fn)(TCGv, TCGv_env, TCGv, TCGv, TCGv_i32);
+
+fn = (a->fcond & 1 ? gen_helper_fcmp_s_s : gen_helper_fcmp_c_s);
+fl
On 11/19/21 7:13 AM, Song Gao wrote:
+static bool gen_fload_imm(DisasContext *ctx, arg_fr_i *a,
+ MemOp mop, bool nanbox)
Don't pass nanbox, as it can be determined from mop.
I think you should split out
static void maybe_nanbox_load(TCGv freg, MemOp mop)
{
if ((m
On 11/20/21 9:20 AM, Richard Henderson wrote:
%i14s2 10:s14 !function=shl_2
Of course you have a times_4 function introduced later which could be used for
this.
r~
Hi Richard,
On 2021/11/20 下午3:42, Richard Henderson wrote:
On 11/19/21 7:13 AM, Song Gao wrote:
+static bool gen_shift(DisasContext *ctx, arg_rr_i *a,
+ void(*func)(TCGv, TCGv, TCGv))
+{
+ TCGv dest = gpr_dst(ctx, a->rd, EXT_SIGN);
+ TCGv src1 = gpr_src(ctx, a->rj, EX
On 11/19/21 7:13 AM, Song Gao wrote:
+tcg_gen_ld8u_tl(src1, cpu_env,
+offsetof(CPULoongArchState, cf[a->cj & 0x7]));
Mask of cj not needed; it's done by decode.
+&rr_dj_offs rd rj offs
+&rr_offs rj rd offs
...
+@rr_dj_offs16 .. rj:5
On 11/19/21 7:13 AM, Song Gao wrote:
+static void output_r_offs(DisasContext *ctx, arg_r_offs *a,
+ const char *mnemonic)
+{
+output(ctx, mnemonic, "r%d, %d # 0x%lx", a->rj, a->offs,
%lx is wrong; use PRIx64.
Many instances.
If you use
make docker-test-build@f
On 11/19/21 7:13 AM, Song Gao wrote:
This includes:
- sockbits.h
- target_errno_defs.h
- target_fcntl.h
- termbits.h
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
---
linux-user/loongarch64/sockbits.h | 11 +++
linux-user/loongarch64/target_errno_defs.h | 12 ++
On 11/19/21 7:13 AM, Song Gao wrote:
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
---
linux-user/loongarch64/target_structs.h | 48 +
1 file changed, 48 insertions(+)
create mode 100644 linux-user/loongarch64/target_structs.h
diff --git a/linux-user
While using SCSI passthrough, Following scenario makes qemu doesn't
realized the capacity change of remote scsi target:
1. online resize the scsi target.
2. issue 'rescan-scsi-bus.sh -s ...' in host.
3. issue 'rescan-scsi-bus.sh -s ...' in vm.
In above scenario I used to experienced errors while a
On 11/19/21 7:13 AM, Song Gao wrote:
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
---
linux-user/loongarch64/signal.c| 162 +
linux-user/loongarch64/target_signal.h | 29 ++
2 files changed, 191 insertions(+)
create mode 100644 linux-us
On 11/19/21 7:13 AM, Song Gao wrote:
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
---
include/elf.h | 2 ++
linux-user/elfload.c| 58 +
linux-user/loongarch64/target_elf.h | 12
3 files changed, 72 in
From: Hyman Huang(黄勇)
v3:
- rebase on master
- modify the following points according to the advice given by Markus
1. remove the DirtyRateQuotaVcpu and use its field as option directly
2. add comments to show details of what dirtylimit setup do
3. explain how to use dirtylimit in combinatio
From: Hyman Huang(黄勇)
implement dirtyrate calculation periodically basing on
dirty-ring and throttle vCPU until it reachs the quota
dirtyrate given by user.
introduce qmp commands set-dirty-limit/cancel-dirty-limit to
set/cancel dirty limit on vCPU.
Signed-off-by: Hyman Huang(黄勇)
---
cpus-com
From: Hyman Huang(黄勇)
impose dirty restraint on vCPU by kicking it and sleep
as the auto-converge does during migration, but just
kick the specified vCPU instead, not all vCPUs of vm.
start a thread to track the dirtylimit status and adjust
the throttle pencentage dynamically depend on current
a
From: Hyman Huang(黄勇)
introduce the third method GLOBAL_DIRTY_RESTRAINT of dirty
tracking for calculate dirtyrate periodly for dirty restraint.
implement thread for calculate dirtyrate periodly, which will
be used for dirty restraint.
add dirtylimit.h to introduce the util function for dirty
li
On 11/19/21 7:13 AM, Song Gao wrote:
+static inline abi_ulong target_shmlba(CPULoongArchState *env)
+{
+return 0x4;
+}
include/asm/shmparam.h:#define SHMLBA SZ_64K
Otherwise,
Reviewed-by: Richard Henderson
r~
On 11/19/21 7:13 AM, Song Gao wrote:
+case EXCP_ADE:
+force_sig_fault(TARGET_SIGSEGV, TARGET_SEGV_MAPERR, env->badaddr);
+break;
No longer required; should be handled correctly by cpu_loop_exit_sigsegv.
Otherwise,
Reviewed-by: Richard Henderson
r~
On 11/19/21 5:58 PM, Juan Quintela wrote:
It just calls buffer_is_zero(). Just change the callers.
Signed-off-by: Juan Quintela
---
migration/ram.c | 9 ++---
1 file changed, 2 insertions(+), 7 deletions(-)
Reviewed-by: Richard Henderson
r~
On 11/19/21 5:58 PM, Juan Quintela wrote:
It just calls buffer_is_zero(). Just change the callers.
Signed-off-by: Juan Quintela
---
dump/dump.c | 10 +-
1 file changed, 1 insertion(+), 9 deletions(-)
Reviewed-by: Richard Henderson
r~
Hi,
On 11/20/21 08:46, Yifei Jiang wrote:
> Use char-fe to handle console sbi call, which implement early
> console io while apply 'earlycon=sbi' into kernel parameters.
>
> Signed-off-by: Yifei Jiang
> Signed-off-by: Mingwang Li
> ---
> target/riscv/kvm.c | 42
On 11/19/21 5:58 PM, Juan Quintela wrote:
We were using the iov directly, but we will need this info on the
following patch.
Signed-off-by: Juan Quintela
---
migration/multifd.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/migration/multifd.c b/migration/multifd.c
index 7c9deb1921..
On 11/19/21 5:58 PM, Juan Quintela wrote:
static int nocomp_send_prepare(MultiFDSendParams *p, uint32_t used,
Error **errp)
{
+MultiFDPages_t *pages = p->pages;
+
+for (int i = 0; i < used; i++) {
+p->iov[p->iovs_used].iov_base = pages->block->
On 11/19/21 3:51 PM, Alex Bennée wrote:
When dealing with multi-threaded userspace programs there is a race
condition with the addition of cpu->opaque (aka TaskState). This is
due to cpu_copy calling cpu_create which updates the global vCPU list.
However the task state isn't set until later. This
On Fri, Nov 19, 2021 at 09:47:33PM +0800, Chao Peng wrote:
> Current code assume the private memory is persistent and KVM can check
> with backing store to see if private memory exists at the same address
> by calling get_pfn(alloc=false).
>
> Signed-off-by: Yu Zhang
> Signed-off-by: Chao Peng
>
From: "Maciej S. Szmigiero"
This way there is at least some contact point for incoming patches.
We'll see whether the code still gets just a random patch a few times
a year or whether it requires a permanent maintainer to take care of it.
Signed-off-by: Maciej S. Szmigiero
---
MAINTAINERS | 6
On 19/11/2021 08:39, Finn Thain wrote:
On Thu, 18 Nov 2021, Mark Cave-Ayland wrote:
Hi Finn,
I've not forgotten about this series - we're now in 6.2 freeze, but it's
on my TODO list to revisit in the next development cycle this along with
the ESP stress-ng changes which I've also been lookin
On 11/20/21 8:46 AM, Yifei Jiang wrote:
+id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG,
KVM_REG_RISCV_CONFIG_REG(isa));
+ret = kvm_get_one_reg(cs, id, &isa);
+if (ret) {
+return ret;
+}
+env->misa_mxl |= isa;
This doesn't look right.
I'm sure you meant
env->m
On 11/20/21 8:46 AM, Yifei Jiang wrote:
const VMStateDescription vmstate_riscv_cpu = {
.name = "cpu",
.version_id = 3,
.minimum_version_id = 3,
+.post_load = cpu_post_load,
.fields = (VMStateField[]) {
VMSTATE_UINTTL_ARRAY(env.gpr, RISCVCPU, 32),
On Sat, 20 Nov 2021, Mark Cave-Ayland wrote:
> On 19/11/2021 08:39, Finn Thain wrote:
>
> > On Thu, 18 Nov 2021, Mark Cave-Ayland wrote:
> >
> >>
> >> Hi Finn,
> >>
> >> I've not forgotten about this series - we're now in 6.2 freeze, but it's
> >> on my TODO list to revisit in the next developme
On Sat, Nov 20, 2021 at 01:23:16AM +, Sean Christopherson wrote:
> On Fri, Nov 19, 2021, Jason Gunthorpe wrote:
> > On Fri, Nov 19, 2021 at 10:21:39PM +, Sean Christopherson wrote:
> > > On Fri, Nov 19, 2021, Jason Gunthorpe wrote:
> > > > On Fri, Nov 19, 2021 at 07:18:00PM +, Sean Chri
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