On 11/1/21 6:01 AM, LIU Zhiwei wrote:
static bool trans_fld(DisasContext *ctx, arg_fld *a)
{
-TCGv addr;
+TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
+TCGv addr = temp_new(ctx);
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVD);
-addr = get_gpr(ctx, a->rs1, EXT_NONE);
-
On Tue, 26 Oct 2021 at 01:33, Simon Glass wrote:
>
> Add this file, generated from qemu, so there is a reference devicetree
> in the U-Boot tree.
>
> Signed-off-by: Simon Glass
Note that the dtb you get from QEMU is only guaranteed to work if:
1) you run it on the exact same QEMU version you ge
On 11/1/21 6:01 AM, LIU Zhiwei wrote:
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -37,7 +37,7 @@ static bool trans_vsetvl(DisasContext *ctx, arg_vsetvl *a)
} else {
s1 = get_gpr(ctx, a->rs1, EXT_ZERO);
}
-gen_helper_vset
On Tue, 26 Oct 2021 at 15:11, Damien Hedde wrote:
>
> When loading a binary file, we only check if it is smaller than the
> ram_size. It does not really check if the file will be loaded at an
> existing location (if there is nothing at the target address, it will
> "fail" silently later). It preve
On 11/1/21 6:01 AM, LIU Zhiwei wrote:
-((1 << s->sew) <= sizeof(target_ulong)) &&
+((1 << s->sew) <= (get_olen(s) / 8)) &&
XLEN not OLEN.
But this will also clash with rv128, since we still won't have 128-bit atomics. So I
think you need to be more reserved in this ch
Hi Simon,
On Thu, 28 Oct 2021 at 05:51, Simon Glass wrote:
>
> Hi Ilias,
>
> On Tue, 26 Oct 2021 at 00:46, Ilias Apalodimas
> wrote:
> >
> > Hi Simon,
> >
> > A bit late to the party, sorry!
>
> (Did you remember the beer?
We'll probably need something stronger to sort this out :)
> I am reply
Hi Xuerui,
On 2021/11/1 下午6:45, WANG Xuerui wrote:
While I can see this patch and the next one are clearly from me, my
author info is lost as I didn't spot any "From:" line in the mail body?
Also I don't remember seeing "Base-on" tags in QEMU either.
Sorry, I refer to the commit 35f171a2eb25f
On Mon, 4 Oct 2021 at 16:54, Tong Ho wrote:
>
> Hi Peter,
>
> I will follow up with patches to fix the memory leaks.
>
> Where can I get a copy of the Coverity reports that have the 10 issues you
> indicated?
They're on https://scan.coverity.com/projects/qemu?tab=overview
You'll need to create a
On 11/1/21 6:01 AM, LIU Zhiwei wrote:
Signed-off-by: LIU Zhiwei
---
target/riscv/insn_trans/trans_rvv.c.inc | 8
target/riscv/internals.h| 1 +
target/riscv/vector_helper.c| 54 +
3 files changed, 46 insertions(+), 17 deletions(-)
On 10/27/21 06:14, Philippe Mathieu-Daudé wrote:
> As of this commit, the nanoMIPS toolchains haven't been merged
> in mainstream projects. However MediaTek provides a toolchain:
> https://github.com/MediaTek-Labs/nanomips-gnu-toolchain/releases/tag/nanoMIPS-2021.02-01
>
> QEMU deprecation policy
On 10/27/21 06:14, Philippe Mathieu-Daudé wrote:
> Move various files unrelated to MIPS TCG frontend into
> new sections.
>
> Since v1:
> - Do not add Paul without his consent
> - un-deprecate nanoMIPS
>
> Philippe Mathieu-Daudé (4):
> MAINTAINERS: Add MIPS general architecture support entry
>
Per the "P32 Porting Guide" (rev 1.2) [1], chapter 2:
p32 ABI Overview
The Application Binary Interface, or ABI, is the set of rules
that all binaries must follow in order to run on a nanoMIPS
system. This includes, for example, object file format,
instruction set, da
Peter Xu wrote:
> save_snapshot() checks migration blocker, which looks sane. At the meantime
> we
> should also teach the blocker add helper to fail if during a snapshot, just
> like for migrations.
>
> Reviewed-by: Marc-André Lureau
> Signed-off-by: Peter Xu
Reviewed-by: Juan Quintela
Peter Xu wrote:
> Both dump-guest-memory and live migration caches vm state at the beginning.
> Either of them entering the other one will cause race on the vm state, and
> even
> more severe on that (please refer to the crash report in the bug link).
>
> Let's block live migration in dump-guest-
Richard Henderson writes:
> Pretending that the source is i64 when it is in fact i32 is
> incorrect; we have type-changing opcodes that must be used.
> This bug trips up the subsequent change to the optimizer.
>
> Fixes: 4f2331e5b67a
> Signed-off-by: Richard Henderson
Reviewed-by: Alex Bennée
David Hildenbrand wrote:
> The parameter is unused, let's drop it.
>
> Reviewed-by: Peter Xu
> Reviewed-by: Philippe Mathieu-Daudé
> Reviewed-by: Juan Quintela
> Signed-off-by: David Hildenbrand
This was already been included.
David Hildenbrand wrote:
> Introduce replay_discarded callback similar to our existing
> replay_populated callback, to be used my migration code to never migrate
> discarded memory.
>
> Acked-by: Peter Xu
> Signed-off-by: David Hildenbrand
Reviewed-by: Juan Quintela
Signed-off-by: Maxim Levitsky
---
accel/kvm/kvm-all.c | 25 ++
gdbstub.c| 62
include/sysemu/kvm.h | 15 +++
3 files changed, 91 insertions(+), 11 deletions(-)
diff --git a/accel/kvm/kvm-all.c b/accel/kvm/kvm-all.c
These patches implement the qemu side logic to support
the KVM features I developed recently.
All 3 patches are for features that are accepted upstream in KVM.
V2: rebased and fixed patch 2 to compile without kvm
Best regards,
Maxim Levitsky
Maxim Levitsky (3):
KVM: use KVM_{GET|SET}_SREG
Signed-off-by: Maxim Levitsky
---
target/i386/cpu.c | 5 +
target/i386/cpu.h | 4
target/i386/kvm/kvm.c | 15 +++
target/i386/machine.c | 23 +++
4 files changed, 47 insertions(+)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 598d451d
This allows to make PDPTRs part of the migration
stream and thus not reload them after migration which
is against X86 spec.
Signed-off-by: Maxim Levitsky
---
accel/kvm/kvm-all.c | 5 ++
include/sysemu/kvm.h | 4 ++
target/i386/cpu.h | 3 ++
target/i386/kvm/kvm.c | 107 ++
On 11/1/21 6:01 AM, LIU Zhiwei wrote:
Only check the range that has passed the address translation.
Signed-off-by: LIU Zhiwei
---
target/riscv/vector_helper.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
Reviewed-by: Richard Henderson
@@ -638,12 +638,12 @@ vext_ldff(void *
On 11/1/21 6:33 AM, Philippe Mathieu-Daudé wrote:
On 10/31/21 17:43, Taylor Simpson wrote:
Tests for
packet semantics
vector loads (aligned and unaligned)
vector stores (aligned and unaligned)
vector masked stores
vector new value store
maximum HVX temps in a packet
Hello,
I've found an issue when hot-plugging the secondary virtio_blk device
into q35 Windows guest(2019) with upstream qemu 6.1.0(+1 patch). The
first disk can be hot-plugged successfully.
The qemu options for PCIe root port is,
-device
pcie-root-port,port=2,chassis=2,id=pciroot2,bus=pcie
Plan-A should be to update the container with the new toolchain.
Plan-B would be to remove the vector registers from the inline asm.
Thanks!
Taylor
> -Original Message-
> From: Richard Henderson
> Sent: Monday, November 1, 2021 8:44 AM
> To: Philippe Mathieu-Daudé ; Taylor Simpson
> ;
On 11/1/21 15:09, Taylor Simpson wrote:
> Plan-A should be to update the container with the new toolchain.
IIUC Richard is going with Plan-A: wait Alex queue get merged,
then retry merging this pull request.
> Plan-B would be to remove the vector registers from the inline asm.
>
>
> Thanks!
> T
On Mon, Nov 01, 2021 at 11:03:22AM +0300, Vladimir Sementsov-Ogievskiy wrote:
> 29.10.2021 23:32, Eric Blake wrote:
> > On Thu, Oct 28, 2021 at 12:24:39PM +0200, Vladimir Sementsov-Ogievskiy
> > wrote:
> > > Let's detect block-size automatically if not specified by user:
> > >
> > > If both fil
On Thu, 21 Oct 2021 at 05:20, David Gibson wrote:
>
> From: BALATON Zoltan
>
> Issue a warning when using VOF (which is the default) but no -kernel
> option given to let users know that it will likely fail as the guest
> has nothing to run. It is not a hard error because it may still be
> useful
On 11/1/21 5:21 AM, Dov Murik wrote:
Commit cff03145ed3c ("sev/i386: Introduce sev_add_kernel_loader_hashes
for measured linux boot", 2021-09-30) introduced measured direct boot
with -kernel, using an OVMF-designated hashes table which QEMU fills.
However, if OVMF doesn't designate such an area,
On Thu, 14 Oct 2021 at 17:37, Paolo Bonzini wrote:
>
> This brings a change that makes audio drivers more similar to all
> other modules. All drivers are built by default, while
> --audio-drv-list only governs the default choice of the audio driver.
>
> Meson options are added to disable the driv
On 10/25/21 2:19 PM, Markus Armbruster wrote:
> Michal Privoznik writes:
>
>> The -preconfig option and exit-preconfig command are around for
>> quite some time now. However, they are still marked as unstable.
>> This is suboptimal because it may block some upper layer in
>> consuming it. In this
At some point in the last month a meson change landed, and now
when meson runs it complains:
WARNING: Broken python installation detected. Python files installed
by Meson might not be found by python interpreter.
There's nothing in the meson log here that says what it's
complaining about:
Bui
On Tue, 19 Oct 2021 at 10:04, Kashyap Chamarthy wrote:
>
> My main motivation was to convert SubmitAPatch[1] based on a chat with
> Peter Maydell and Dan Berrangé on #qemu channel (on OFTC). But the page
> also links to a couple of other contribution-related pages, so I
> converted them too:
>
>
On Mon, Nov 01, 2021 at 03:37:58PM +0100, Michal Prívozník wrote:
> On 10/25/21 2:19 PM, Markus Armbruster wrote:
> > Michal Privoznik writes:
> >
> >> The -preconfig option and exit-preconfig command are around for
> >> quite some time now. However, they are still marked as unstable.
> >> This i
On Tue, 19 Oct 2021 at 10:04, Kashyap Chamarthy wrote:
>
> Add the entries for contributing-related rSTified wiki docs.
>
> Signed-off-by: Kashyap Chamarthy
> ---
> docs/devel/index.rst | 5 +
> 1 file changed, 5 insertions(+)
>
> diff --git a/docs/devel/index.rst b/docs/devel/index.rst
> in
On 11/1/21 10:17 AM, Philippe Mathieu-Daudé wrote:
On 11/1/21 15:09, Taylor Simpson wrote:
Plan-A should be to update the container with the new toolchain.
IIUC Richard is going with Plan-A: wait Alex queue get merged,
then retry merging this pull request.
Correct.
r~
On Mon, Nov 01, 2021 at 02:53:44PM +, Peter Maydell wrote:
> At some point in the last month a meson change landed, and now
> when meson runs it complains:
>
> WARNING: Broken python installation detected. Python files installed
> by Meson might not be found by python interpreter.
>
> There
Suggested-by: Peter Maydell
Signed-off-by: BALATON Zoltan
---
hw/ppc/pegasos2.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/hw/ppc/pegasos2.c b/hw/ppc/pegasos2.c
index e427ac2fe0..298e6b93e2 100644
--- a/hw/ppc/pegasos2.c
+++ b/hw/ppc/pegasos2.c
@@ -23,6 +23,7 @@
#incl
On Mon, 1 Nov 2021 at 15:07, Daniel P. Berrangé wrote:
>
> On Mon, Nov 01, 2021 at 02:53:44PM +, Peter Maydell wrote:
> > At some point in the last month a meson change landed, and now
> > when meson runs it complains:
> >
> > WARNING: Broken python installation detected. Python files install
Richard Henderson writes:
> On 10/26/21 3:22 AM, Alex Bennée wrote:
>> This is a bit of a band-aid against hand-built images that have been
>> accidentally polluted by a user build. All images pulled from the
>> registry shouldn't have the user defined.
>
> I believe that I've fixed the images
On Fri, Oct 29, 2021 at 04:22:55PM +0200, Damien Hedde wrote:
> Hi,
>
> Dynamic sysbus devices are allowed by a per-machine basis.
> Right now, the allowance check is done during an machine_init_done
> notifier, well after such devices are created.
>
> This series move the check at the right plac
On 11/1/21 4:27 AM, Laurent Vivier wrote:
From: Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Damien Hedde
Message-Id: <20210920064048.2729397-4-f4...@amsat.org>
Signed-off-by: Laurent Vivier
---
hw/hppa/lasi.c | 10 +-
hw/input/lasips2.c
On Mon, Nov 1, 2021 at 9:58 AM Eugenio Perez Martin wrote:
>
> On Mon, Nov 1, 2021 at 4:34 AM Jason Wang wrote:
> >
> > On Fri, Oct 29, 2021 at 10:16 PM Eugenio Pérez wrote:
> > >
> > > The -1 assumes that all devices with no cvq have an spare vq allocated
> > > for them, but with no offer of VI
On 11/1/21 16:31, Richard Henderson wrote:
> On 11/1/21 4:27 AM, Laurent Vivier wrote:
>> From: Philippe Mathieu-Daudé
>>
>> Signed-off-by: Philippe Mathieu-Daudé
>> Reviewed-by: Damien Hedde
>> Message-Id: <20210920064048.2729397-4-f4...@amsat.org>
>> Signed-off-by: Laurent Vivier
>> ---
>>
On Thu, Oct 28, 2021 at 06:47:38PM +0200, Philippe Mathieu-Daudé wrote:
> On 10/28/21 17:54, Daniel P. Berrangé wrote:
> > This turns the pattern
> >
> > if (err) {
> > hmp_handle_error(mon, err);
> > return;
> > }
> >
> > into
> >
> > if (hmp_handle_error(mon, err);
> > ret
On 2021/11/1 下午6:46, Richard Henderson wrote:
On 11/1/21 6:01 AM, LIU Zhiwei wrote:
static bool trans_fld(DisasContext *ctx, arg_fld *a)
{
- TCGv addr;
+ TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
+ TCGv addr = temp_new(ctx);
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVD);
-
On Thu, Oct 28, 2021 at 07:08:13PM +0200, Philippe Mathieu-Daudé wrote:
> On 10/28/21 17:54, Daniel P. Berrangé wrote:
> > This is a counterpart to the HMP "info opcount" command. It is being
> > added with an "x-" prefix because this QMP command is intended as an
> > ad hoc debugging tool and will
On 211029 0853, Qiuhao Li wrote:
> Sounds great. How about mentioning this program on the Security
> Process web page [1]? Hackers who report vulnerabilities may be
> interested in fixing bugs.
Sounds like a good idea to me.
>
> Just curious. Why didn't those bugs [2] get fixed before disclosure
On Thu, 23 Sept 2021 at 14:29, Peter Maydell wrote:
>
> On Mon, 20 Sept 2021 at 13:25, Eric Auger wrote:
> >
> > The PL031 currently is not able to report guest RTC change to the QMP
> > monitor as opposed to mc146818 or spapr RTCs. This patch adds the call
> > to qapi_event_send_rtc_change() whe
On 11/1/21 11:27, Philippe Mathieu-Daudé wrote:
> Build failed running the 'clang-user' job:
>
> TESTlinux-test on sh4
> ../linux-user/syscall.c:10373:34: runtime error: member access within
> misaligned address 0x0048af34 for type 'struct linux_dirent64',
> which requires 8 byte alignme
Cortex-M CPUs with MVE should advertise this fact to gdb, using the
org.gnu.gdb.arm.m-profile-mve XML feature, which defines the VPR
register. Presence of this feature also tells gdb to create
pseudo-registers Q0..Q7, so we do not need to tell gdb about them
separately.
Note that unless you have
On 30/10/2021 19.15, Richard Henderson wrote:
Split host_signal_pc and host_signal_write out of user-exec.c.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
linux-user/host/s390/host-signal.h | 93 -
linux-user/host/s390x/host-signal.h |
On Sun, Oct 31, 2021 at 11:14:04AM +0100, Philippe Mathieu-Daudé wrote:
> On 10/30/21 19:15, Richard Henderson wrote:
> > The fallback code in cpu_loop_exit_sigsegv is sufficient
> > for microblaze linux-user.
> >
> > Remove the code from cpu_loop that handled the unnamed 0xaa exception.
> >
> >
Ping^3, now 2 months after patch posted and reviewed...
-- PMM
On Mon, 27 Sept 2021 at 11:03, Peter Maydell wrote:
>
> Ping^2 !
>
> thanks
> -- PMM
>
> On Mon, 13 Sept 2021 at 13:34, Peter Maydell wrote:
> >
> > Ping? (this has been reviewed)
> >
> > thanks
> > -- PMM
> >
> > On Wed, 1 Sept 202
On 4/25/19 22:00, Eduardo Habkost wrote:
> Only softmmu code uses gpio, so move gpio code from qdev.c to
> gpio.c and compile it only on softmmu mode.
>
> Signed-off-by: Eduardo Habkost
> ---
> hw/core/gpio.c| 206 ++
> hw/core/qdev.c| 184
On Sat, 30 Oct 2021 at 19:11, Richard Henderson
wrote:
>
> Because of the complexity of setting ESR, continue to use
> arm_deliver_fault. This means we cannot remove the code
> within cpu_loop that decodes EXCP_DATA_ABORT and
> EXCP_PREFETCH_ABORT.
>
> But using the new hook means that we don't h
On Sat, 30 Oct 2021 at 19:42, Richard Henderson
wrote:
>
> Because of the complexity of setting ESR, re-use the existing
> arm_cpu_do_unaligned_access function. This means we have to
> handle the exception ourselves in cpu_loop, transforming it
> to the appropriate signal.
>
> Reviewed-by: Warner
On 11/1/21 6:01 AM, LIU Zhiwei wrote:
@@ -2677,6 +2677,7 @@ static bool trans_vmv_s_x(DisasContext *s, arg_vmv_s_x *a)
/* This instruction ignores LMUL and vector register groups */
int maxsz = s->vlen >> 3;
TCGv_i64 t1;
+TCGv src1 = get_gpr(s, a->rs1, EXT_ZE
On 11/1/21 6:01 AM, LIU Zhiwei wrote:
After excpetion return, we should give a xlen view of context in new
priveledge, including the general registers, pc, and CSRs.
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 1 +
.../riscv/insn_trans/trans_privileged.c.in
On 11/1/21 6:01 AM, LIU Zhiwei wrote:
As pc will be written by the xepc in exception return, just ignore
pc in translation.
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 4 ++--
target/riscv/insn_trans/trans_privileged.c.inc | 7 ++-
target/riscv/op_helpe
Hi Peter,
On Mon, 1 Nov 2021 at 04:48, Peter Maydell wrote:
>
> On Tue, 26 Oct 2021 at 01:33, Simon Glass wrote:
> >
> > Add this file, generated from qemu, so there is a reference devicetree
> > in the U-Boot tree.
> >
> > Signed-off-by: Simon Glass
>
> Note that the dtb you get from QEMU is o
On 11/1/21 6:01 AM, LIU Zhiwei wrote:
mask |= MSTATUS_MPV | MSTATUS_GVA;
+if ((val ^ mstatus) & MSTATUS64_UXL) {
+mask |= MSTATUS64_UXL;
+}
Why do you need the conditional here?
Why is this not just
mask |= MSTATUS_MPV | MSTATUS_GVA | MSTATUS64_UXL;
On 11/1/21 12:10 PM, Thomas Huth wrote:
Since you moved code around, should this file also bear the original copyright
statement?
Probably.
License changes from LGPL to GPL - intended? (I personally don't mind, I just wanted to
check whether this was on purpose or by accident)
Not really i
On 11/1/21 12:30 PM, Peter Maydell wrote:
We seem to be restricting tlb_fill to sysemu already.
Not true:
-#endif /* !defined(CONFIG_USER_ONLY) */
-
bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
MMUAccessType access_type, int mmu_idx,
On Fri, 8 Oct 2021 at 01:26, Hao Wu wrote:
>
> From: Shengtan Mao
>
> Signed-off-by: Shengtan Mao
> Reviewed-by: Hao Wu
> Reviewed-by: Chris Rauer
> Reviewed-by: Tyrone Ting
> Signed-off-by: Hao Wu
> ---
> +default:
> +qemu_log_mask(LOG_GUEST_ERROR, "SDHCI read of nonexist reg:
On Fri, 8 Oct 2021 at 01:26, Hao Wu wrote:
>
> From: Shengtan Mao
>
> Signed-off-by: Shengtan Mao
> Reviewed-by: Hao Wu
> Reviewed-by: Chris Rauer
> Reviewed-by: Tyrone Ting
> Signed-off-by: Hao Wu
> ---
> tests/qtest/libqos/meson.build | 1 +
> tests/qtest/libqos/sdhci-cmd.c | 116 ++
On Fri, 8 Oct 2021 at 01:26, Hao Wu wrote:
>
> From: Shengtan Mao
>
> Signed-off-by: Shengtan Mao
> Reviewed-by: Hao Wu
> Reviewed-by: Chris Rauer
> Reviewed-by: Tyrone Ting
> Signed-off-by: Hao Wu
Reviewed-by: Peter Maydell
thanks
-- PMM
On Fri, 8 Oct 2021 at 01:26, Hao Wu wrote:
>
> From: Shengtan Mao
>
> Signed-off-by: Shengtan Mao
> Reviewed-by: Hao Wu
> Reviewed-by: Chris Rauer
> Reviewed-by: Tyrone Ting
> Signed-off-by: Hao Wu
Reviewed-by: Peter Maydell
thanks
-- PMM
On 11/1/21 17:08, Peter Maydell wrote:
> Cortex-M CPUs with MVE should advertise this fact to gdb, using the
> org.gnu.gdb.arm.m-profile-mve XML feature, which defines the VPR
> register. Presence of this feature also tells gdb to create
> pseudo-registers Q0..Q7, so we do not need to tell gdb abo
Split out a function to adjust the raw signal pc into a
value that could be passed to cpu_restore_state.
Reviewed-by: Warner Losh
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
v2: Adjust pc in place; return MMUAccessType.
---
include/exec/exec-all.h | 10 ++
Remove the comment about siglongjmp. We do use sigsetjmp
in the main cpu loop, but we do not save the signal mask
as most exits from the cpu loop do not require them.
Reviewed-by: Warner Losh
Signed-off-by: Richard Henderson
---
accel/tcg/user-exec.c | 14 ++
1 file changed, 2 inse
Changes for v7:
Drop prctl changes (phil).
Fix copyright & license for linux-user/host/*/host-signal.h (thuth).
What's left is all of the changes for accel/tcg, the targets,
and the linux-user changes to match.
This does *not* actually enable user-only unaligned access exceptions
for any targ
Split host_signal_pc and host_signal_write out of user-exec.c.
Cc: Thomas Huth
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
linux-user/host/s390/host-signal.h | 94 -
linux-user/host/s390x/host-signal.h | 2 +-
accel/tcg/user-exec.c
The existing code for safe-syscall.inc.S will compile
without change for riscv32 and riscv64. We may also
drop the meson.build stanza that merges them for tcg/.
Reviewed-by: Warner Losh
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
Signed-off-by: Richard Henderson
---
con
Add stub host-signal.h for all linux-user hosts.
Add new code replacing cpu_signal_handler.
Full migration will happen one host at a time.
Reviewed-by: Warner Losh
Reviewed-by: Philippe Mathieu-Daudé
Acked-by: Alistair Francis
Signed-off-by: Richard Henderson
---
linux-user/host/aarch64/host-
On Mon, 1 Nov 2021 at 17:09, Richard Henderson
wrote:
>
> On 11/1/21 12:30 PM, Peter Maydell wrote:
> > We seem to be restricting tlb_fill to sysemu already.
>
> Not true:
>
> > -#endif /* !defined(CONFIG_USER_ONLY) */
> > -
> > bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
> >
Split host_signal_pc and host_signal_write out of user-exec.c.
Cc: Thomas Huth
Reviewed-by: Warner Losh
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
linux-user/host/mips/host-signal.h | 63 +-
accel/tcg/user-exec.c | 52 +---
Currently there are only two places that require we reset this
value before exiting to the main loop, but that will change.
Reviewed-by: Warner Losh
Signed-off-by: Richard Henderson
---
accel/tcg/cpu-exec.c | 3 ++-
accel/tcg/user-exec.c | 2 --
2 files changed, 2 insertions(+), 3 deletions(-)
Split host_signal_pc and host_signal_write out of user-exec.c.
Drop the *BSD code, to be re-created under bsd-user/ later.
Cc: Thomas Huth
Reviewed-by: Warner Losh
Signed-off-by: Richard Henderson
---
linux-user/host/i386/host-signal.h | 26 -
linux-user/host/x32/host-signal.h| 2
This is the major portion of handle_cpu_signal which is specific
to tcg, handling the page protections for the translations.
Most of the rest will migrate to linux-user/ shortly.
Reviewed-by: Warner Losh
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
v2: Pass guest add
Split host_signal_pc and host_signal_write out of user-exec.c.
Cc: Thomas Huth
Reviewed-by: Warner Losh
Reviewed-by: Alistair Francis
Signed-off-by: Richard Henderson
---
linux-user/host/riscv/host-signal.h | 86 +-
accel/tcg/user-exec.c | 134 --
Split host_signal_pc and host_signal_write out of user-exec.c.
Drop the *BSD code, to be re-created under bsd-user/ later.
Cc: Thomas Huth
Reviewed-by: Warner Losh
Signed-off-by: Richard Henderson
---
linux-user/host/ppc/host-signal.h | 26 +-
linux-user/host/ppc64/host-signal.h | 2
Split host_signal_pc and host_signal_write out of user-exec.c.
Drop the *BSD code, to be re-created under bsd-user/ later.
Cc: Thomas Huth
Reviewed-by: Warner Losh
Signed-off-by: Richard Henderson
---
linux-user/host/aarch64/host-signal.h | 75 -
accel/tcg/user-exec.c
Split host_signal_pc and host_signal_write out of user-exec.c.
Drop the *BSD code, to be re-created under bsd-user/ later.
Cc: Thomas Huth
Reviewed-by: Warner Losh
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
linux-user/host/arm/host-signal.h | 31 +
Now that all of the linux-user hosts have been converted
to host-signal.h, drop the compatibility code.
Reviewed by: Warner Losh
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
include/exec/exec-all.h | 12
linux-user/signal.c | 14 --
2 fi
The named function no longer exists.
Refer to host_signal_handler instead.
Reviewed-by: Warner Losh
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/arm/sve_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/arm/sve_helper.c b/tar
Split host_signal_pc and host_signal_write out of user-exec.c.
Drop the *BSD code, to be re-created under bsd-user/ later.
Drop the Solaris code as completely unused.
Cc: Thomas Huth
Reviewed-by: Warner Losh
Signed-off-by: Richard Henderson
---
linux-user/host/sparc/host-signal.h | 55 ++
This is a new interface to be provided by the os emulator for
raising SIGSEGV on fault. Use the new record_sigsegv target hook.
Reviewed by: Warner Losh
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
include/exec/exec-all.h | 15 +++
accel/tcg/user-exec.c
Add a new user-only interface for updating cpu state before
raising a signal. This will replace tlb_fill for user-only
and should result in less boilerplate for each guest.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
include/hw/core/tcg-cpu-ops.h | 26 +
The fallback code in cpu_loop_exit_sigsegv is sufficient
for hppa linux-user.
Remove the code from cpu_loop that raised SIGSEGV.
This makes all of the code in mem_helper.c sysemu only,
so remove the ifdefs and move the file to hppa_softmmu_ss.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: R
The fallback code in cpu_loop_exit_sigsegv is sufficient
for m68k linux-user.
Remove the code from cpu_loop that handled EXCP_ACCESS.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
linux-user/m68k/cpu_loop.c | 10 --
target/m68k/cpu.c | 2 +-
target/
Record trap_arg{0,1,2} for the linux-user signal frame.
Fill in the stores to trap_arg{1,2} that were missing
from the previous user-only alpha_cpu_tlb_fill function.
Use maperr to simplify computation of trap_arg1.
Remove the code for EXCP_MMFAULT from cpu_loop, as
that part is now handled by cp
Do not read 4 bytes before we determine the size of the insn.
Simplify triple switches in favor of checking major opcodes.
Include the missing cases of compact fsd and fsdsp.
Reviewed-by: Alistair Francis
Signed-off-by: Richard Henderson
---
linux-user/host/riscv/host-signal.h | 83 ++--
Record cr2, error_code, and exception_index. That last means
that we must exit to cpu_loop ourselves, instead of letting
exception_index being overwritten.
Use the maperr parameter to properly set PG_ERROR_P_MASK.
Reviewed by: Warner Losh
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Rich
Because of the complexity of setting ESR, continue to use
arm_deliver_fault. This means we cannot remove the code
within cpu_loop that decodes EXCP_DATA_ABORT and
EXCP_PREFETCH_ABORT.
But using the new hook means that we don't have to do the
page_get_flags check manually, and we'll be able to res
The fallback code in cpu_loop_exit_sigsegv is sufficient
for hexagon linux-user.
Remove the code from cpu_loop that raises SIGSEGV.
Reviewed-by: Taylor Simpson
Signed-off-by: Richard Henderson
---
linux-user/hexagon/cpu_loop.c | 24 +---
target/hexagon/cpu.c | 23 -
The fallback code in cpu_loop_exit_sigsegv is sufficient
for mips linux-user.
This means we can remove tcg/user/tlb_helper.c entirely.
Remove the code from cpu_loop that raised SIGSEGV.
Reviewed-by: Warner Losh
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/mi
Split host_signal_pc and host_signal_write out of user-exec.c.
Cc: Thomas Huth
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
linux-user/host/alpha/host-signal.h | 42 +
accel/tcg/user-exec.c | 31 +
2 file
The fallback code in cpu_loop_exit_sigsegv is sufficient
for sparc linux-user.
This makes all of the code in mmu_helper.c sysemu only, so remove
the ifdefs and move the file to sparc_softmmu_ss. Remove the code
from cpu_loop that handled TT_DFAULT and TT_TFAULT.
Cc: Mark Cave-Ayland
Reviewed-by
The fallback code in cpu_loop_exit_sigsegv is sufficient
for cris linux-user.
Remove the code from cpu_loop that handled the unnamed 0xaa exception.
This makes all of the code in helper.c sysemu only, so remove the
ifdefs and move the file to cris_softmmu_ss.
Reviewed-by: Philippe Mathieu-Daudé
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