On 10/30/21 19:16, Richard Henderson wrote:
> We will raise SIGBUS directly from cpu_loop_exit_sigbus.
>
> Signed-off-by: Richard Henderson
> ---
> linux-user/hppa/cpu_loop.c | 7 ---
> 1 file changed, 7 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
On 10/30/21 19:16, Richard Henderson wrote:
> QEMU does not allow the system control bits for either exception to
> be enabled in linux-user, therefore both exceptions are dead code.
>
> Signed-off-by: Richard Henderson
> ---
> linux-user/openrisc/cpu_loop.c | 17 +
> 1 file chan
On 10/30/21 19:15, Richard Henderson wrote:
> The fallback code in cpu_loop_exit_sigsegv is sufficient
> for hppa linux-user.
>
> Remove the code from cpu_loop that raised SIGSEGV.
> This makes all of the code in mem_helper.c sysemu only,
> so remove the ifdefs and move the file to hppa_softmmu_ss
On 10/30/21 19:15, Richard Henderson wrote:
> The fallback code in cpu_loop_exit_sigsegv is sufficient
> for microblaze linux-user.
>
> Remove the code from cpu_loop that handled the unnamed 0xaa exception.
>
> Signed-off-by: Richard Henderson
> ---
> target/microblaze/cpu.h | 8 -
On 10/30/21 19:16, Richard Henderson wrote:
> We will raise SIGBUS directly from cpu_loop_exit_sigbus.
>
> Signed-off-by: Richard Henderson
> ---
> linux-user/ppc/cpu_loop.c | 8
> 1 file changed, 8 deletions(-)
>
> diff --git a/linux-user/ppc/cpu_loop.c b/linux-user/ppc/cpu_loop.c
> i
On 10/30/21 19:16, Richard Henderson wrote:
> Not sure why the user-only code wasn't rewritten to use
> probe_access_flags at the same time that the sysemu code
> was converted. For the purpose of user-only, this is an
> exact replacement.
>
> Signed-off-by: Richard Henderson
> ---
> target/s39
On 10/30/21 19:16, Richard Henderson wrote:
> The fallback code in cpu_loop_exit_sigsegv is sufficient
> for sh4 linux-user.
>
> Remove the code from cpu_loop that raised SIGSEGV.
>
> Signed-off-by: Richard Henderson
> ---
> target/sh4/cpu.h | 6 +++---
> linux-user/sh4/cpu_loop.c | 8
On 10/30/21 19:15, Richard Henderson wrote:
> Record trap_arg{0,1,2} for the linux-user signal frame.
>
> Fill in the stores to trap_arg{1,2} that were missing
> from the previous user-only alpha_cpu_tlb_fill function.
> Use maperr to simplify computation of trap_arg1.
>
> Remove the code for EXC
Hi Richard,
On 10/30/21 19:15, Richard Henderson wrote:
> Changes for v6:
> Rebase and apply some patch review (phil)
>
> Changes for v5:
> I've combined the sigsegv and sigbus patch sets, because they're
> so very closely modelled. We've got user-only hooks named
>
> record_sigsegv
>
Hi Philippe,
On 2021/10/28 23:05, Philippe Mathieu-Daudé wrote:
Signed-off-by: Philippe Mathieu-Daudé
---
hw/core/qdev-hotplug.c | 73 ++
hw/core/qdev.c | 60 --
hw/core/meson.build| 1 +
3 files changed,
Hi Philippe,
On 2021/10/28 23:05, Philippe Mathieu-Daudé wrote:
Restrict hotplug to system emulation, add stubs for the other uses.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/core/hotplug-stubs.c | 34 ++
hw/core/meson.build | 12 ++--
2 files
Hi Philippe,
I saw that there are some cross-build failures and a clang complain
about this patch in your triggered CI pipeline. I believe the minor
diff below will resolve them. If you are going to resend v2 of the
"qdev-hotplug" patches, I would very much appreciate it if you
can also help to r
On 10/31/21 3:30 AM, Philippe Mathieu-Daudé wrote:
I could look at these, but unfortunately don't have enough time
for the rest. Would it help to merge the 60 first patches for
this release and delay the prctl() ones for the next dev window?
It would. The first 60 are perhaps more tcg-ish than
Add HVX support to the semantics generator
Acked-by: Richard Henderson
Signed-off-by: Taylor Simpson
---
target/hexagon/gen_semantics.c | 33 +
target/hexagon/hex_common.py | 13 +
2 files changed, 46 insertions(+)
diff --git a/target/hexagon/gen_s
Reviewed-by: Richard Henderson
Signed-off-by: Taylor Simpson
---
target/hexagon/hex_regs.h | 1 +
target/hexagon/cpu.c | 2 +-
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/hexagon/hex_regs.h b/target/hexagon/hex_regs.h
index f291911..e1b3149 100644
--- a/target/hexag
Acked-by: Richard Henderson
Signed-off-by: Taylor Simpson
---
target/hexagon/gen_helper_funcs.py | 112 ++--
target/hexagon/gen_helper_protos.py | 16 ++-
target/hexagon/gen_tcg_funcs.py | 254 ++--
3 files changed, 360 insertions(+), 22 deletion
HVX is a set of wide vector instructions. Machine state includes
vector registers (VRegs)
vector predicate registers (QRegs)
temporary registers for intermediate values
store buffer (masked stores and scatter/gather)
Acked-by: Richard Henderson
Signed-off-by: Taylor Simpson
---
Acked-by: Richard Henderson
Signed-off-by: Taylor Simpson
---
target/hexagon/attribs_def.h.inc | 22 ++
1 file changed, 22 insertions(+)
diff --git a/target/hexagon/attribs_def.h.inc b/target/hexagon/attribs_def.h.inc
index e44a7ea..dc890a5 100644
--- a/target/hexagon/attrib
macros to interface with the generator
macros referenced in instruction semantics
Acked-by: Richard Henderson
Signed-off-by: Taylor Simpson
---
target/hexagon/macros.h | 22 +++
target/hexagon/mmvec/macros.h | 354 ++
2 files changed, 376 insertion
The following changes since commit af531756d25541a1b3b3d9a14e72e7fedd941a2e:
Merge remote-tracking branch 'remotes/philmd/tags/renesas-20211030' into
staging (2021-10-30 11:31:41 -0700)
are available in the git repository at:
https://github.com/quic/qemu tags/pull-hex-20211031
Acked-by: Richard Henderson
Signed-off-by: Taylor Simpson
---
target/hexagon/gen_dectree_import.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/target/hexagon/gen_dectree_import.c
b/target/hexagon/gen_dectree_import.c
index 5b7ecfc..ee35467 100644
--- a/target/hexagon/gen_d
Reviewed-by: Richard Henderson
Signed-off-by: Taylor Simpson
---
target/hexagon/README | 81 ++-
1 file changed, 80 insertions(+), 1 deletion(-)
diff --git a/target/hexagon/README b/target/hexagon/README
index b0b2435..372e247 100644
--- a/target/
Reviewed-by: Richard Henderson
Signed-off-by: Taylor Simpson
---
target/hexagon/gen_tcg_hvx.h | 122 +++
1 file changed, 122 insertions(+)
diff --git a/target/hexagon/gen_tcg_hvx.h b/target/hexagon/gen_tcg_hvx.h
index ac2143e..e865410 100644
--- a/target/
Acked-by: Richard Henderson
Signed-off-by: Taylor Simpson
---
tests/tcg/hexagon/scatter_gather.c | 1011
tests/tcg/hexagon/Makefile.target |2 +
2 files changed, 1013 insertions(+)
create mode 100644 tests/tcg/hexagon/scatter_gather.c
diff --git a/test
Reviewed-by: Richard Henderson
Signed-off-by: Taylor Simpson
---
target/hexagon/gen_tcg_hvx.h | 103 +++
1 file changed, 103 insertions(+)
diff --git a/target/hexagon/gen_tcg_hvx.h b/target/hexagon/gen_tcg_hvx.h
index f53a7f2..32f8e20 100644
--- a/target/
Build the infrastructure to create overrides for HVX instructions.
We create a new empty file (gen_tcg_hvx.h) that will be populated
in subsequent patches.
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Signed-off-by: Taylor Simpson
---
target/hexagon/gen_tcg_hvx.h|
Imported from the Hexagon architecture library
imported/allext_macros.def Top level macro include for all extensions
imported/macros.def Scalar core macros (some HVX here)
imported/mmvec/macros.defHVX macro definitions
The macro definition files specify instru
Reviewed-by: Richard Henderson
Signed-off-by: Taylor Simpson
---
target/hexagon/gen_tcg_hvx.h | 42 ++
1 file changed, 42 insertions(+)
diff --git a/target/hexagon/gen_tcg_hvx.h b/target/hexagon/gen_tcg_hvx.h
index f548404..f53a7f2 100644
--- a/target/hex
Reviewed-by: Richard Henderson
Signed-off-by: Taylor Simpson
---
target/hexagon/gen_tcg_hvx.h | 26 ++
1 file changed, 26 insertions(+)
diff --git a/target/hexagon/gen_tcg_hvx.h b/target/hexagon/gen_tcg_hvx.h
index 32f8e20..435c7b5 100644
--- a/target/hexagon/gen_tcg_hvx
Functions to support scatter/gather
Add new file to target/hexagon/meson.build
Reviewed-by: Richard Henderson
Signed-off-by: Taylor Simpson
---
target/hexagon/mmvec/system_ext_mmvec.h | 25 ++
target/hexagon/mmvec/system_ext_mmvec.c | 47 +
target
Reviewed-by: Richard Henderson
Signed-off-by: Taylor Simpson
---
target/hexagon/gen_tcg_hvx.h | 31 +++
1 file changed, 31 insertions(+)
diff --git a/target/hexagon/gen_tcg_hvx.h b/target/hexagon/gen_tcg_hvx.h
index a560504..916230e 100644
--- a/target/hexagon/gen_tc
Reviewed-by: Richard Henderson
Signed-off-by: Taylor Simpson
---
target/hexagon/gen_tcg_hvx.h | 34 ++
1 file changed, 34 insertions(+)
diff --git a/target/hexagon/gen_tcg_hvx.h b/target/hexagon/gen_tcg_hvx.h
index e865410..f548404 100644
--- a/target/hexagon/gen
Acked-by: Richard Henderson
Signed-off-by: Taylor Simpson
---
target/hexagon/gen_tcg_hvx.h | 218 +++
1 file changed, 218 insertions(+)
diff --git a/target/hexagon/gen_tcg_hvx.h b/target/hexagon/gen_tcg_hvx.h
index 2d1d778..cdcc938 100644
--- a/target/hex
Reviewed-by: Richard Henderson
Signed-off-by: Taylor Simpson
---
target/hexagon/gen_tcg_hvx.h | 106 +++
1 file changed, 106 insertions(+)
diff --git a/target/hexagon/gen_tcg_hvx.h b/target/hexagon/gen_tcg_hvx.h
index b5c6cad..a560504 100644
--- a/target/
Reviewed-by: Richard Henderson
Signed-off-by: Taylor Simpson
---
target/hexagon/gen_tcg_hvx.h | 50
1 file changed, 50 insertions(+)
diff --git a/target/hexagon/gen_tcg_hvx.h b/target/hexagon/gen_tcg_hvx.h
index 916230e..ac2143e 100644
--- a/target/h
Add new file to target/hexagon/meson.build
Acked-by: Richard Henderson
Signed-off-by: Taylor Simpson
---
target/hexagon/mmvec/decode_ext_mmvec.h | 24
target/hexagon/decode.c | 24 +++-
target/hexagon/mmvec/decode_ext_mmvec.c | 236
target
Probe and commit vector stores (masked and scatter/gather)
Log vector register writes
Add the execution counters to the debug log
Histogram instructions
Reviewed-by: Richard Henderson
Signed-off-by: Taylor Simpson
---
target/hexagon/helper.h| 16 +++
target/hexagon/op_helper.c | 282 ++
Acked-by: Richard Henderson
Signed-off-by: Taylor Simpson
---
target/hexagon/gen_tcg_hvx.h | 150 +++
1 file changed, 150 insertions(+)
diff --git a/target/hexagon/gen_tcg_hvx.h b/target/hexagon/gen_tcg_hvx.h
index 435c7b5..2d1d778 100644
--- a/target/hex
Reviewed-by: Richard Henderson
Signed-off-by: Taylor Simpson
---
target/hexagon/translate.h | 61
target/hexagon/genptr.c| 15 +++
target/hexagon/translate.c | 239 -
3 files changed, 311 insertions(+), 4 deletions(-)
diff --git a/t
Reviewed-by: Richard Henderson
Signed-off-by: Taylor Simpson
---
tests/tcg/hexagon/vector_add_int.c | 61 ++
tests/tcg/hexagon/Makefile.target | 3 ++
2 files changed, 64 insertions(+)
create mode 100644 tests/tcg/hexagon/vector_add_int.c
diff --git a/test
Acked-by: Richard Henderson
Signed-off-by: Taylor Simpson
---
target/hexagon/decode.c | 4 +
target/hexagon/imported/allextenc.def| 20 +
target/hexagon/imported/encode.def | 1 +
target/hexagon/imported/mmvec/encode_ext.def | 794 +
Tests for
packet semantics
vector loads (aligned and unaligned)
vector stores (aligned and unaligned)
vector masked stores
vector new value store
maximum HVX temps in a packet
vector operations
Acked-by: Richard Henderson
Signed-off-by: Taylor Simpson
---
tests/tcg/h
Acked-by: Richard Henderson
Signed-off-by: Taylor Simpson
---
tests/tcg/hexagon/hvx_histogram_input.h | 717
tests/tcg/hexagon/hvx_histogram_row.h | 24 ++
tests/tcg/hexagon/hvx_histogram.c | 88
tests/tcg/hexagon/Makefile.target | 5 +
tes
Eugenio Pérez wrote:
> As qemu guidelines:
> Unless a pointer is used to modify the pointed-to storage, give it the
> "const" attribute.
>
> In the particular case of iova_tree_find it allows to enforce what is
> requested by its comment, since the compiler would shout in case of
> modifying or fr
On 28/10/21 20:03, Thomas Huth wrote:
Thanks for the update, this works definitely better than the RFC
already. However, I spotted another oddity: "make check-softfloat" now
is way slower than before, it takes more than 2 minutes now, while it
finished within 20 seconds before your change ...
On Fri, Oct 29, 2021 at 04:16:08PM +0200, Eugenio Pérez wrote:
> The -1 assumes that all devices with no cvq have an spare vq allocated
> for them, but with no offer of VIRTIO_NET_F_CTRL_VQ. This may not be the
> case, and the device may have a pair number of queues.
>
> To fix this, just resort t
On Tue, Oct 26, 2021 at 5:41 PM Anup Patel wrote:
>
> The guest external interrupts from an interrupt controller are
> delivered only when the Guest/VM is running (i.e. V=1). This means
> any guest external interrupt which is triggered while the Guest/VM
> is not running (i.e. V=0) will be missed
On Sat, Oct 30, 2021 at 12:26 AM Damien Hedde
wrote:
>
> Right now the allowance check for adding a sysbus device using
> -device cli option (or device_add qmp command) is done well after
> the device has been created. It is done during the machine init done
> notifier: machine_init_notify() in hw
This series adds a standard way of passing information between different
firmware phases. This already exists in U-Boot at a very basic level, in
the form of a bloblist containing an spl_handoff structure, but the intent
here is to define something useful across projects.
The need for this is gr
Add an SPL build for qemu so we can test the standard passage feature.
Include a binman definition so that SPL and U-Boot are in the same image.
For now this just boots to a prompt.
Signed-off-by: Simon Glass
---
arch/arm/dts/qemu-arm-u-boot.dtsi| 22 +
arch/arm/mach-qemu/Kconfig
On Fri, Oct 29, 2021 at 05:24:01PM -0300, matheus.fe...@eldorado.org.br wrote:
> From: Matheus Ferst
>
> There's no reason to keep vector-impl.c.inc separate from
> vmx-impl.c.inc. Additionally, let GVec handle the multiple calls to
> helper_cfuged for us.
>
> Reviewed-by: Richard Henderson
> S
On Mon, Nov 01, 2021 at 11:13:42AM +1100, David Gibson wrote:
> On Fri, Oct 29, 2021 at 05:23:50PM -0300, matheus.fe...@eldorado.org.br wrote:
> > From: Matheus Ferst
> >
> > This patch series implements 56 new instructions for POWER10, moving 28
> > "old" instructions to decodetree along the way
On Sat, Oct 30, 2021 at 02:17:07PM -0700, Richard Henderson wrote:
> On 10/29/21 1:23 PM, matheus.fe...@eldorado.org.br wrote:
> > From: Luis Pires
> >
> > Implement the following PowerISA v3.1 instruction:
> > cntlzdm: Count Leading Zeros Doubleword Under Bit Mask
> >
> > Suggested-by: Richard
On Fri, Oct 29, 2021 at 04:24:02PM -0300, Luis Pires wrote:
> This series moves all existing DFP instructions to decodetree and
> implements the 2 new instructions (dcffixqq and dctfixqq) from
> Power ISA 3.1.
>
> In order to implement dcffixqq, divu128/divs128 were modified to
> support 128-bit q
On Fri, Oct 29, 2021 at 05:23:50PM -0300, matheus.fe...@eldorado.org.br wrote:
> From: Matheus Ferst
>
> This patch series implements 56 new instructions for POWER10, moving 28
> "old" instructions to decodetree along the way. The series is divided by
> facility as follows:
>
> - From patch 1 to
On Fri, Oct 29, 2021 at 10:16 PM Eugenio Pérez wrote:
>
> The -1 assumes that all devices with no cvq have an spare vq allocated
> for them, but with no offer of VIRTIO_NET_F_CTRL_VQ. This may not be the
> case, and the device may have a pair number of queues.
>
> To fix this, just resort to the l
On Fri, Oct 29, 2021 at 4:08 PM Zhang, Chen wrote:
>
>
>
> > -Original Message-
> > From: Jason Wang
> > Sent: Friday, October 29, 2021 11:11 AM
> > To: Zhang, Chen
> > Cc: qemu-dev ; Markus Armbruster
> > ; Li Zhijian
> > Subject: Re: [PATCH V5 1/3] net/filter: Optimize transfer protoc
On Sun, Oct 17, 2021 at 10:01:23PM -0300, Daniel Henrique Barboza wrote:
> This patch starts an IBM Power8+ compatible PMU implementation by adding
> the representation of PMU events that we are going to sample, PMUEvent.
> This struct represents a Perf event, determined by the PMUEventType
> enum,
Pass through RDPID and RDTSCP support in CPUID if host supports it.
Correctly detect if CPU_BASED_TSC_OFFSET and CPU_BASED2_RDTSCP would
be supported in primary and secondary processor-based VM-execution
controls. Enable RDTSCP in secondary processor controls if RDTSCP
support is indicated in CPUI
On Fri, Oct 29, 2021 at 4:59 PM wrote:
>
> From: Frank Chang
>
> Signed-off-by: Frank Chang
> Reviewed-by: Richard Henderson
> Reviewed-by: Alistair Francis
> ---
> target/riscv/cpu.c | 16
> target/riscv/cpu.h | 2 +-
> 2 files changed, 9 insertions(+), 9 deletions(-)
>
Re
On Sat, Oct 30, 2021 at 1:07 PM Bin Meng wrote:
>
> From: Bin Meng
>
> Move the codes around so that the order of .subsections matches
> the one they are referenced in vmstate_riscv_cpu.
>
> Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Alistair
> ---
>
> target/riscv/machine.c | 92
On Tue, Oct 26, 2021 at 5:01 PM Anup Patel wrote:
>
> The RISC-V AIA specification extends RISC-V local interrupts and
> introduces new CSRs. This patch adds defines for the new AIA CSRs.
>
> Signed-off-by: Anup Patel
What's the status of these CSR addresses being finalised?
Alistair
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