[PULL v2 13/18] target/riscv: Implement address masking functions required for RISC-V Pointer Masking extension

From: Anatoly Parshintsev Signed-off-by: Anatoly Parshintsev Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-id: 20211025173609.2724490-8-space.monkey.deliv...@gmail.com Signed-off-by: Alistair Francis --- target/riscv/cpu.h| 2 ++ target/riscv/cpu_helper.c | 18

[PULL v2 04/18] hw/riscv: microchip_pfsoc: Use the PLIC config helper function

From: Alistair Francis Signed-off-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Bin Meng Tested-by: Bin Meng Message-id: 20211022060133.3045020-4-alistair.fran...@opensource.wdc.com --- include/hw/riscv/microchip_pfsoc.h | 1 - hw/riscv/microchip_pfsoc.c | 14

[PULL v2 09/18] target/riscv: Support CSRs required for RISC-V PM extension except for the h-mode

From: Alexey Baturo Signed-off-by: Alexey Baturo Reviewed-by: Alistair Francis Message-id: 20211025173609.2724490-4-space.monkey.deliv...@gmail.com Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 11 ++ target/riscv/cpu.c | 2 + target/riscv/csr.c | 285 +++

[PULL v2 12/18] target/riscv: Support pointer masking for RISC-V for i/c/f/d/a types of instructions

From: Alexey Baturo Signed-off-by: Alexey Baturo Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-id: 20211025173609.2724490-7-space.monkey.deliv...@gmail.com Signed-off-by: Alistair Francis --- target/riscv/translate.c| 8 target/riscv/insn_trans

[PULL v2 16/18] target/riscv: remove force HS exception

From: Jose Martins There is no need to "force an hs exception" as the current privilege level, the state of the global ie and of the delegation registers should be enough to route the interrupt to the appropriate privilege level in riscv_cpu_do_interrupt. The is true for both asynchronous and syn

[PULL v2 05/18] hw/riscv: virt: Use the PLIC config helper function

From: Alistair Francis Signed-off-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Bin Meng Tested-by: Bin Meng Message-id: 20211022060133.3045020-5-alistair.fran...@opensource.wdc.com --- hw/riscv/virt.c | 20 +--- 1 file changed, 1 insertion(+), 19 dele

[PULL v2 14/18] target/riscv: Allow experimental J-ext to be turned on

From: Alexey Baturo Signed-off-by: Alexey Baturo Reviewed-by: Alistair Francis Reviewed-by: Bin Meng Reviewed-by: Richard Henderson Message-id: 20211025173609.2724490-9-space.monkey.deliv...@gmail.com Signed-off-by: Alistair Francis --- target/riscv/cpu.c | 4 1 file changed, 4 inserti

[PULL v2 11/18] target/riscv: Print new PM CSRs in QEMU logs

From: Alexey Baturo Signed-off-by: Alexey Baturo Reviewed-by: Alistair Francis Message-id: 20211025173609.2724490-6-space.monkey.deliv...@gmail.com Signed-off-by: Alistair Francis --- target/riscv/cpu.c | 7 +++ 1 file changed, 7 insertions(+) diff --git a/target/riscv/cpu.c b/target/ris

[PULL v2 07/18] target/riscv: Add J-extension into RISC-V

From: Alexey Baturo Signed-off-by: Alexey Baturo Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: Bin Meng Message-id: 20211025173609.2724490-2-space.monkey.deliv...@gmail.com Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 2 ++ 1 file changed, 2 insertion

[PULL v2 15/18] target/riscv: fix VS interrupts forwarding to HS

From: Jose Martins VS interrupts (2, 6, 10) were not correctly forwarded to hs-mode when not delegated in hideleg (which was not being taken into account). This was mainly because hs level sie was not always considered enabled when it should. The spec states that "Interrupts for higher-privilege

[PATCH] meson.build: Allow to disable OSS again

If sys/soundcard.h is available, it is currently not possible to disable OSS with the --disable-oss or --without-default-features configure switches. Improve the check in meson.build to fix this. Fixes: 87430d5b13 ("configure, meson: move audio driver detection to Meson") Signed-off-by: Thomas Hut

[PULL v2 17/18] softfloat: add APIs to handle alternative sNaN propagation for fmax/fmin

From: Chih-Min Chao For "fmax/fmin ft0, ft1, ft2" and if one of the inputs is sNaN, The original logic: Return NaN and set invalid flag if ft1 == sNaN || ft2 == sNan. The alternative path: Set invalid flag if ft1 == sNaN || ft2 == sNaN. Return NaN only if ft1 == NaN && ft2 == Na

[PULL v2 18/18] target/riscv: change the api for RVF/RVD fmin/fmax

From: Chih-Min Chao The sNaN propagation behavior has been changed since cd20cee7 in https://github.com/riscv/riscv-isa-manual. In Priv spec v1.10, RVF is v2.0. fmin.s and fmax.s are implemented with IEEE 754-2008 minNum and maxNum operations. In Priv spec v1.11, RVF is v2.2. fmin.s and fmax.s

Re: [PATCH v2 2/5] pci: Export pci_for_each_device_under_bus*()

On Thu, Oct 28, 2021 at 12:31:26PM +0800, Peter Xu wrote: > They're actually more commonly used than the helper without _under_bus, > because > most callers do have the pci bus on hand. After exporting we can switch a lot > of the call sites to use these two helpers. > > Reviewed-by: David Hilde

[Bug 1802915] Re: GTK display refresh rate is throttled

The bug is still here. People are simply modifying the code and recompiling.. It only needs to change the code cap from 30ms (10 years old cap) to 16ms, and we got a smooth gui capable of gaming. Please, don't ignore us. Recompiling qemu only for one number is very annoying. -- You received thi

RE: [PATCH V5 1/3] net/filter: Optimize transfer protocol for filter-mirror/redirector

> -Original Message- > From: Jason Wang > Sent: Friday, October 29, 2021 11:11 AM > To: Zhang, Chen > Cc: qemu-dev ; Markus Armbruster > ; Li Zhijian > Subject: Re: [PATCH V5 1/3] net/filter: Optimize transfer protocol for filter- > mirror/redirector > > > 在 2021/10/28 下午5:05, Zhang

Re: [PATCH] pci: fix PCI resource reserve capability on BE

On 20/10/2021 11.54, Michael S. Tsirkin wrote: PCI resource reserve capability should use LE format as all other PCI things. If we don't then seabios won't boot: === PCI new allocation pass #1 === PCI: check devices PCI: QEMU resource reserve cap: size 10 type io PCI: secondary bus 1

Re: Possible reward for fuzzer bug fixes? Secure Open Source Rewards Program

Sounds great. How about mentioning this program on the Security Process web page [1]? Hackers who report vulnerabilities may be interested in fixing bugs. Just curious. Why didn't those bugs [2] get fixed before disclosure? It seems SD and virtio-9p are maintained now. [1] https://www.qemu.org/

[PATCH v9 01/76] target/riscv: drop vector 0.7.1 and add 1.0 support

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 16 target/riscv/cpu.h | 2 +- 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index f7fd

[PATCH v9 00/76] support vector extension v1.0

From: Frank Chang This patchset implements the vector extension v1.0 for RISC-V on QEMU. RVV v1.0 spec is now fronzen for public review: https://github.com/riscv/riscv-v-spec/releases/tag/v1.0 The port is available here: https://github.com/sifive/qemu/tree/rvv-1.0-upstream-v9 RVV v1.0 can be e

[PATCH v9 02/76] target/riscv: Use FIELD_EX32() to extract wd field

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/vector_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 12c31aa4b4d..70f5898

[PATCH v9 03/76] target/riscv: rvv-1.0: add mstatus VS field

From: LIU Zhiwei Signed-off-by: LIU Zhiwei Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu.h| 2 ++ target/riscv/cpu_bits.h | 1 + target/riscv/cpu_helper.c | 20 +++- target/riscv/csr.c| 12

[PATCH v9 06/76] target/riscv: rvv-1.0: introduce writable misa.v field

From: Frank Chang Implementations may have a writable misa.v field. Analogous to the way in which the floating-point unit is handled, the mstatus.vs field may exist even if misa.v is clear. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/ris

[PATCH v9 15/76] target/riscv: rvv-1.0: update check functions

From: Frank Chang Update check functions with RVV 1.0 rules. Signed-off-by: Frank Chang Reviewed-by: Alistair Francis --- target/riscv/insn_trans/trans_rvv.c.inc | 715 +--- 1 file changed, 507 insertions(+), 208 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvv

[PATCH v9 05/76] target/riscv: rvv-1.0: add sstatus VS field

From: LIU Zhiwei Signed-off-by: LIU Zhiwei Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu_bits.h | 1 + target/riscv/csr.c | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu_bits.h b/target

[PATCH v9 04/76] target/riscv: rvv-1.0: set mstatus.SD bit if mstatus.VS is dirty

From: Frank Chang Signed-off-by: Frank Chang --- target/riscv/csr.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 9b5bd5d7b49..bb500afdeb5 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -502,6 +502,7 @@ static RISCVException read_

[PATCH v9 09/76] target/riscv: rvv-1.0: add vcsr register

From: LIU Zhiwei Signed-off-by: LIU Zhiwei Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu_bits.h | 7 +++ target/riscv/csr.c | 17 + 2 files changed, 24 insertions(+) diff --git a/target/riscv/cpu_bits.h

[PATCH v9 10/76] target/riscv: rvv-1.0: add vlenb register

From: Greentime Hu Signed-off-by: Greentime Hu Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu_bits.h | 1 + target/riscv/csr.c | 7 +++ 2 files changed, 8 insertions(+) diff --git a/target/riscv/cpu_bits.h b/target/riscv

[PATCH v9 16/76] target/riscv: introduce more imm value modes in translator functions

From: Frank Chang Immediate value in translator function is extended not only zero-extended and sign-extended but with more modes to be applicable with multiple formats of vector instructions. * IMM_ZX: Zero-extended * IMM_SX: Sign-extended * IMM_TRUNC_SEW: Truncate to log(SEW)

[PATCH v9 08/76] target/riscv: rvv-1.0: remove rvv related codes from fcsr registers

From: Frank Chang * Remove VXRM and VXSAT fields from FCSR register as they are only presented in VCSR register. * Remove RVV loose check in fs() predicate function. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/csr.c | 13

[PATCH v9 07/76] target/riscv: rvv-1.0: add translation-time vector context status

From: Frank Chang Signed-off-by: LIU Zhiwei Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu.h | 5 +- target/riscv/cpu_helper.c | 3 + target/riscv/insn_trans/trans_rvv.c.inc | 75 ++

[PATCH v9 12/76] target/riscv: rvv-1.0: remove MLEN calculations

From: Frank Chang As in RVV 1.0 design, MLEN is hardcoded with value 1 (Section 4.5). Thus, remove all MLEN related calculations. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/insn_trans/trans_rvv.c.inc | 35 +--- target/riscv/inter

[PATCH v9 24/76] target/riscv: rvv-1.0: load/store whole register instructions

From: Frank Chang Add the following instructions: * vlre.v * vsr.v Signed-off-by: Frank Chang Reviewed-by: Alistair Francis --- target/riscv/helper.h | 21 target/riscv/insn32.decode | 22 target/riscv/insn_trans/trans_rvv.c.inc | 68 +

[PATCH v9 11/76] target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr registers

From: Frank Chang If VS field is off, accessing vector csr registers should raise an illegal-instruction exception. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/csr.c | 5 + 1 file changed, 5 insertions(+) diff --git a/target/r

[PATCH v9 25/76] target/riscv: rvv-1.0: update vext_max_elems() for load/store insns

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Alistair Francis --- target/riscv/insn_trans/trans_rvv.c.inc | 32 ++-- target/riscv/vector_helper.c| 99 ++--- 2 files changed, 80 insertions(+), 51 deletions(-) diff --git a/target/riscv/insn_trans

[PATCH v9 17/76] target/riscv: rvv:1.0: add translation-time nan-box helper function

From: Frank Chang * Add fp16 nan-box check generator function, if a 16-bit input is not properly nanboxed, then the input is replaced with the default qnan. * Add do_nanbox() helper function to utilize gen_check_nanbox_X() to generate the NaN-boxed floating-point values based on SEW setting.

[PATCH v9 29/76] target/riscv: rvv-1.0: count population in mask instruction

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/helper.h | 2 +- target/riscv/insn32.decode | 2 +- target/riscv/insn_trans/trans_rvv.c.inc | 7 --- target/riscv/vector_helper.c

[PATCH v9 13/76] target/riscv: rvv-1.0: add fractional LMUL

From: Frank Chang Introduce the concepts of fractional LMUL for RVV 1.0. In RVV 1.0, LMUL bits are contiguous in vtype register. Also rearrange rvv bits in TB_FLAGS to skip MSTATUS_VS (0x600) and MSTATUS_FS (0x6000) bits. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by:

[PATCH v9 18/76] target/riscv: rvv-1.0: remove amo operations instructions

From: Frank Chang Vector AMOs are removed from standard vector extensions. Will be added later as separate Zvamo extension, but will need a different encoding from earlier proposal. Signed-off-by: Frank Chang Reviewed-by: Alistair Francis --- target/riscv/helper.h | 27

[PATCH v9 30/76] target/riscv: rvv-1.0: find-first-set mask bit instruction

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/helper.h | 2 +- target/riscv/insn32.decode | 2 +- target/riscv/insn_trans/trans_rvv.c.inc | 4 ++-- target/riscv/vector_helper.c

[PATCH v9 26/76] target/riscv: rvv-1.0: take fractional LMUL into vector max elements calculation

From: Frank Chang Update vext_get_vlmax() and MAXSZ() to take fractional LMUL into calculation for RVV 1.0. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu.h | 27 - target/riscv/cpu_hel

[PATCH v9 19/76] target/riscv: rvv-1.0: configure instructions

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/insn_trans/trans_rvv.c.inc | 62 +++-- target/riscv/vector_helper.c| 14 +- 2 files changed, 40 insertions(+), 36 deletions(-) diff -

[PATCH v9 27/76] target/riscv: rvv-1.0: floating-point square-root instruction

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/insn32.decode | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 7d8441d1f21..92a0e6fe51e 1

[PATCH v9 21/76] target/riscv: rvv-1.0: index load and store instructions

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Alistair Francis --- target/riscv/helper.h | 67 +++ target/riscv/insn32.decode | 21 +++-- target/riscv/insn_trans/trans_rvv.c.inc | 110 +--- target/riscv/vector_helper.

[PATCH v9 33/76] target/riscv: rvv-1.0: element index instruction

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/insn32.decode | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 3ac5162aeb7..ab274dcde12 1

[PATCH v9 32/76] target/riscv: rvv-1.0: iota instruction

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/insn32.decode | 2 +- target/riscv/insn_trans/trans_rvv.c.inc | 10 -- 2 files changed, 9 insertions(+), 3 deletions(-) diff --git a/target/riscv/i

[PATCH v9 22/76] target/riscv: rvv-1.0: fix address index overflow bug of indexed load/store insns

From: Frank Chang Replace ETYPE from signed int to unsigned int to prevent index overflow issue, which would lead to wrong index address. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/vector_helper.c | 8 1 file changed, 4 i

[PATCH v9 20/76] target/riscv: rvv-1.0: stride load and store instructions

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Alistair Francis --- target/riscv/helper.h | 129 ++-- target/riscv/insn32.decode | 43 ++- target/riscv/insn_trans/trans_rvv.c.inc | 376 target/riscv/vector_helper.c

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