[PATCH v9 35/76] target/riscv: rvv-1.0: register gather instructions

From: Frank Chang * Add vrgatherei16.vv instruction. Signed-off-by: Frank Chang Reviewed-by: Alistair Francis --- target/riscv/helper.h | 4 target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvv.c.inc | 27 ++--- target/r

[PATCH v9 28/76] target/riscv: rvv-1.0: floating-point classify instructions

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/insn32.decode | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 92a0e6fe51e..f61eaf7c6ba 1

[PATCH v9 34/76] target/riscv: rvv-1.0: allow load element with sign-extended

From: Frank Chang For some vector instructions (e.g. vmv.s.x), the element is loaded with sign-extended. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/insn_trans/trans_rvv.c.inc | 32 + 1 file changed, 22 inse

[PATCH v9 23/76] target/riscv: rvv-1.0: fault-only-first unit stride load

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/helper.h | 26 ++--- target/riscv/insn32.decode | 14 ++--- target/riscv/insn_trans/trans_rvv.c.inc | 33 +++ target/riscv/vect

[PATCH v9 36/76] target/riscv: rvv-1.0: integer scalar move instructions

From: Frank Chang * Remove "vmv.s.x: dothing if rs1 == 0" constraint. * Add vmv.x.s instruction. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Acked-by: Alistair Francis --- target/riscv/insn32.decode | 3 +- target/riscv/insn_trans/trans_rvv.c.inc | 43

[PATCH v9 41/76] target/riscv: rvv-1.0: single-width averaging add and subtract instructions

From: Frank Chang Add the following instructions: * vaaddu.vv * vaaddu.vx * vasubu.vv * vasubu.vx Remove the following instructions: * vadd.vi Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/helper.h | 16 ++ target/riscv/insn32.decode

[PATCH v9 37/76] target/riscv: rvv-1.0: floating-point move instruction

From: Frank Chang NaN-boxed the scalar floating-point register based on RVV 1.0's rules. Signed-off-by: Frank Chang Reviewed-by: Alistair Francis --- target/riscv/insn_trans/trans_rvv.c.inc | 16 ++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/target/riscv/insn

[PATCH v9 31/76] target/riscv: rvv-1.0: set-X-first mask bit instructions

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/insn32.decode | 6 +++--- target/riscv/insn_trans/trans_rvv.c.inc | 5 - target/riscv/vector_helper.c| 4 3 files changed, 7 insertions(

[PATCH v9 45/76] target/riscv: rvv-1.0: widening integer multiply-add instructions

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/insn32.decode | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index a3f1101cd63..7548b71efdb 100644 --- a/target/riscv/

[PATCH v9 43/76] target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrow

From: Frank Chang * Only do carry-in or borrow-in if is masked (vm=0). * Remove clear function from helper functions as the tail elements are unchanged in RVV 1.0. Signed-off-by: Frank Chang Reviewed-by: Alistair Francis --- target/riscv/insn32.decode | 20 ++--

[PATCH v9 42/76] target/riscv: rvv-1.0: single-width bit shift instructions

From: Frank Chang Truncate vsll.vi, vsrl.vi, vsra.vi's immediate values to lg2(SEW) bits. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/insn_trans/trans_rvv.c.inc | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/target/riscv/insn_trans/tra

[PATCH v9 46/76] target/riscv: rvv-1.0: single-width saturating add and subtract instructions

From: Frank Chang Sign-extend vsaddu.vi immediate value. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/insn_trans/trans_rvv.c.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans

[PATCH v9 38/76] target/riscv: rvv-1.0: floating-point scalar move instructions

From: Frank Chang NaN-boxed the scalar floating-point register based on RVV 1.0's rules. Signed-off-by: Frank Chang Acked-by: Alistair Francis --- target/riscv/insn32.decode | 4 +-- target/riscv/insn_trans/trans_rvv.c.inc | 38 - target/riscv/internals.h

[PATCH v9 48/76] target/riscv: rvv-1.0: floating-point compare instructions

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/vector_helper.c | 9 - 1 file changed, 9 deletions(-) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 277a5e4120a..71d7b1e8796 100644 --- a/target/riscv/vector_h

[PATCH v9 53/76] target/riscv: rvv-1.0: single-width floating-point reduction

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/insn_trans/trans_rvv.c.inc | 12 +--- target/riscv/vector_helper.c| 12 ++-- 2 files changed, 15 insertions(+), 9 deletions(-) diff --git a/target/riscv/insn_trans/trans_rv

[PATCH v9 47/76] target/riscv: rvv-1.0: integer comparison instructions

From: Frank Chang * Sign-extend vmselu.vi and vmsgtu.vi immediate values. * Remove "set tail elements to zeros" as tail elements can be unchanged for either VTA to have undisturbed or agnostic setting. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/insn_trans/tra

[PATCH v9 40/76] target/riscv: rvv-1.0: integer extension instructions

From: Frank Chang Add the following instructions: * vzext.vf2 * vzext.vf4 * vzext.vf8 * vsext.vf2 * vsext.vf4 * vsext.vf8 Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/helper.h | 14 + target/riscv/insn32.decode | 8 +++ target

[PATCH v9 49/76] target/riscv: rvv-1.0: mask-register logical instructions

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/insn_trans/trans_rvv.c.inc | 3 ++- target/riscv/vector_helper.c| 4 2 files changed, 2 insertions(+), 5 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/ri

[PATCH v9 66/76] target/riscv: rvv-1.0: implement vstart CSR

From: Frank Chang * Update and check vstart value for vector instructions. * Add whole register move instruction helper functions as we have to call helper function for case where vstart is not zero. * Remove probe_pages() calls in vector load/store instructions (except fault-only-first loads

[PATCH v9 39/76] target/riscv: rvv-1.0: whole register move instructions

From: Frank Chang Add the following instructions: * vmv1r.v * vmv2r.v * vmv4r.v * vmv8r.v Signed-off-by: Frank Chang Acked-by: Alistair Francis --- target/riscv/insn32.decode | 4 target/riscv/insn_trans/trans_rvv.c.inc | 25 + 2 files changed, 29 i

[PATCH v9 51/76] target/riscv: rvv-1.0: floating-point slide instructions

From: Frank Chang Add the following instructions: * vfslide1up.vf * vfslide1down.vf Signed-off-by: Frank Chang Reviewed-by: Alistair Francis --- target/riscv/helper.h | 7 ++ target/riscv/insn32.decode | 2 + target/riscv/insn_trans/trans_rvv.c.inc | 16 ++

[PATCH v9 58/76] target/riscv: rvv-1.0: remove integer extract instruction

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/insn32.decode | 1 - target/riscv/insn_trans/trans_rvv.c.inc | 23 --- 2 files changed, 24 deletions(-) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.

[PATCH v9 69/76] target/riscv: rvv-1.0: floating-point reciprocal square-root estimate instruction

From: Frank Chang Implement the floating-point reciprocal square-root estimate to 7 bits instruction. Signed-off-by: Frank Chang --- target/riscv/helper.h | 4 + target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvv.c.inc | 1 + target/riscv/v

[PATCH v9 52/76] target/riscv: rvv-1.0: narrowing fixed-point clip instructions

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/helper.h | 24 ++-- target/riscv/insn32.decode | 12 +++--- target/riscv/insn_trans/trans_rvv.c.inc | 12 +++--- target/riscv/vector_helper.c| 52

[PATCH v9 44/76] target/riscv: rvv-1.0: narrowing integer right shift instructions

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/helper.h | 24 +++--- target/riscv/insn32.decode | 12 +++ target/riscv/insn_trans/trans_rvv.c.inc | 42 - target/riscv/vector_helper.

[PATCH v9 63/76] target/riscv: add "set round to odd" rounding mode helper function

From: Frank Chang helper_set_rounding_mode() is responsible for SIGILL, and "round to odd" should be an interface private to translation, so add a new independent helper_set_rod_rounding_mode(). Signed-off-by: Frank Chang Acked-by: Alistair Francis --- target/riscv/fpu_helper.c | 5 + tar

[PATCH v9 70/76] target/riscv: rvv-1.0: floating-point reciprocal estimate instruction

From: Frank Chang Implement the floating-point reciprocal estimate to 7 bits instruction. Signed-off-by: Frank Chang --- target/riscv/helper.h | 4 + target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvv.c.inc | 1 + target/riscv/vector_helper

[PATCH v9 50/76] target/riscv: rvv-1.0: slide instructions

From: Frank Chang * Remove clear function from helper functions as the tail elements are unchanged in RVV 1.0. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/vector_helper.c | 19 --- 1 file changed, 12 insertions(+), 7 deletions(-) diff --git a/

[PATCH v9 56/76] target/riscv: rvv-1.0: remove widening saturating scaled multiply-add

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/helper.h | 22 --- target/riscv/insn32.decode | 7 - target/riscv/insn_trans/trans_rvv.c.inc | 9 -- target/riscv/vector_helper.c| 205 --

[PATCH v9 64/76] target/riscv: rvv-1.0: narrowing floating-point/integer type-convert

From: Frank Chang Signed-off-by: Frank Chang Acked-by: Alistair Francis --- target/riscv/helper.h | 22 - target/riscv/insn32.decode | 15 --- target/riscv/insn_trans/trans_rvv.c.inc | 59 + target/riscv/vector_helper.c

[PATCH v9 73/76] target/riscv: rvv-1.0: add evl parameter to vext_ldst_us()

From: Frank Chang Add supports of Vector unit-stride mask load/store instructions (vlm.v, vsm.v), which has: evl (effective vector length) = ceil(env->vl / 8). The new instructions operate the same as unmasked byte loads and stores. Add evl parameter to reuse vext_ldst_us(). Signed-off-by:

[PATCH v9 54/76] target/riscv: rvv-1.0: widening floating-point reduction instructions

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/insn_trans/trans_rvv.c.inc | 9 - 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index 998247d71

[PATCH v9 57/76] target/riscv: rvv-1.0: remove vmford.vv and vmford.vf

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/helper.h | 6 -- target/riscv/insn32.decode | 2 -- target/riscv/insn_trans/trans_rvv.c.inc | 2 -- target/riscv/vector_helper.c| 7 --- 4 files chang

[PATCH v9 67/76] target/riscv: rvv-1.0: trigger illegal instruction exception if frm is not valid

From: Frank Chang If the frm field contains an invalid rounding mode (101-111), attempting to execute any vector floating-point instruction, even those that do not depend on the rounding mode, will raise an illegal instruction exception. Call gen_set_rm() with DYN rounding mode to check and trig

[PATCH v9 55/76] target/riscv: rvv-1.0: single-width scaling shift instructions

From: Frank Chang log(SEW) truncate vssra.vi immediate value. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/insn_trans/trans_rvv.c.inc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/i

[PATCH v9 59/76] target/riscv: rvv-1.0: floating-point min/max instructions

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/vector_helper.c | 24 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index aed230e1ad8..cc95b692558

[PATCH v9 60/76] target/riscv: introduce floating-point rounding mode enum

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/fpu_helper.c | 12 ++-- target/riscv/insn_trans/trans_rvv.c.inc | 18 +- target/riscv/internals.h| 9 + 3 files changed, 24 insertions(+),

Re: [PATCH] meson.build: Allow to disable OSS again

On 10/29/21 09:13, Thomas Huth wrote: > If sys/soundcard.h is available, it is currently not possible to > disable OSS with the --disable-oss or --without-default-features > configure switches. Improve the check in meson.build to fix this. > > Fixes: 87430d5b13 ("configure, meson: move audio drive

[PATCH v9 61/76] target/riscv: rvv-1.0: floating-point/integer type-convert instructions

From: Frank Chang Add the following instructions: * vfcvt.rtz.xu.f.v * vfcvt.rtz.x.f.v Also adjust GEN_OPFV_TRANS() to accept multiple floating-point rounding modes. Signed-off-by: Frank Chang Reviewed-by: Alistair Francis --- target/riscv/insn32.decode | 11 ++-- target/riscv/

[PATCH v9 65/76] target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Alistair Francis --- target/riscv/cpu.h | 2 +- target/riscv/insn_trans/trans_rvv.c.inc | 4 ++-- target/riscv/vector_helper.c| 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/target

[PATCH v9 68/76] target/riscv: gdb: support vector registers for rv64 & rv32

From: Hsiangkai Wang Signed-off-by: Hsiangkai Wang Signed-off-by: Greentime Hu Signed-off-by: Frank Chang --- target/riscv/cpu.c | 2 + target/riscv/cpu.h | 1 + target/riscv/gdbstub.c | 184 + 3 files changed, 187 insertions(+) diff --git

[PATCH v9 62/76] target/riscv: rvv-1.0: widening floating-point/integer type-convert

From: Frank Chang Add the following instructions: * vfwcvt.rtz.xu.f.v * vfwcvt.rtz.x.f.v Also adjust GEN_OPFV_WIDEN_TRANS() to accept multiple floating-point rounding modes. Signed-off-by: Frank Chang Acked-by: Alistair Francis --- target/riscv/helper.h | 2 + target/risc

Re: [PATCH v4] migration/rdma: Fix out of order wrid

Li Zhijian wrote: > destination: > ../qemu/build/qemu-system-x86_64 -enable-kvm -netdev > tap,id=hn0,script=/etc/qemu-ifup,downscript=/etc/qemu-ifdown -device > e1000,netdev=hn0,mac=50:52:54:00:11:22 -boot c -drive > if=none,file=./Fedora-rdma-server-migration.qcow2,id=drive-virtio-disk0 > -de

[PATCH v9 71/76] target/riscv: rvv-1.0: rename r2_zimm to r2_zimm11

From: Frank Chang Rename r2_zimm to r2_zimm11 for the upcoming vsetivli instruction. vsetivli has 10-bits of zimm but vsetvli has 11-bits of zimm. Signed-off-by: Frank Chang Reviewed-by: Alistair Francis --- target/riscv/insn32.decode | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)

[PATCH v9 75/76] target/riscv: rvv-1.0: rename vmandnot.mm and vmornot.mm to vmandn.mm and vmorn.mm

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Alistair Francis --- target/riscv/helper.h | 4 ++-- target/riscv/insn32.decode | 4 ++-- target/riscv/insn_trans/trans_rvv.c.inc | 4 ++-- target/riscv/vector_helper.c| 4 ++-- 4 files changed

Re: [PATCH v2 4/9] qapi: Tools for sets of special feature flags in generated code

Markus Armbruster wrote: > New enum QapiSpecialFeature enumerates the special feature flags. > > New helper gen_special_features() returns code to represent a > collection of special feature flags as a bitset. > > The next few commits will put them to use. > > Signed-off-by: Markus Armbruster > R

[PATCH v9 72/76] target/riscv: rvv-1.0: add vsetivli instruction

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Alistair Francis --- target/riscv/insn32.decode | 2 ++ target/riscv/insn_trans/trans_rvv.c.inc | 27 + 2 files changed, 29 insertions(+) diff --git a/target/riscv/insn32.decode b/target/riscv/insn

[PATCH v9 74/76] target/riscv: rvv-1.0: add vector unit-stride mask load/store insns

From: Frank Chang Signed-off-by: Frank Chang --- target/riscv/helper.h | 2 ++ target/riscv/insn32.decode | 4 +++ target/riscv/insn_trans/trans_rvv.c.inc | 40 + target/riscv/vector_helper.c| 21 + 4 files changed

[PATCH v9 76/76] target/riscv: rvv-1.0: update opivv_vadc_check() comment

From: Frank Chang Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions is moved to Section 11.4 in RVV v1.0 spec. Update the comment, no functional changes. Signed-off-by: Frank Chang Reviewed-by: Alistair Francis --- target/riscv/insn_trans/trans_rvv.c.inc | 2 +- 1 file changed

Re: [PATCH v2 5/9] qapi: Generalize struct member policy checking

Markus Armbruster wrote: > The generated visitor functions call visit_deprecated_accept() and > visit_deprecated() when visiting a struct member with special feature > flag 'deprecated'. This makes the feature flag visible to the actual > visitors. I want to make feature flag 'unstable' visible

Re: [PATCH v2 6/9] qapi: Generalize command policy checking

Markus Armbruster wrote: > The code to check command policy can see special feature flag > 'deprecated' as command flag QCO_DEPRECATED. I want to make feature > flag 'unstable' visible there as well, so I can add policy for it. > > To let me make it visible, add member @special_features (a bitset

Re: [PATCH v4 14/22] qapi: introduce x-query-rdma QMP command

On 10/28/21 17:54, Daniel P. Berrangé wrote: > This is a counterpart to the HMP "info rdma" command. It is being > added with an "x-" prefix because this QMP command is intended as an > adhoc debugging tool and will thus not be modelled in QAPI as fully > structured data, nor will it have long term

Re: [PATCH v4 12/22] qapi: introduce x-query-numa QMP command

On 10/28/21 17:54, Daniel P. Berrangé wrote: > This is a counterpart to the HMP "info numa" command. It is being > added with an "x-" prefix because this QMP command is intended as an > adhoc debugging tool and will thus not be modelled in QAPI as fully > structured data, nor will it have long term

Re: [PATCH v4 11/22] qapi: introduce x-query-profile QMP command

On 10/28/21 17:54, Daniel P. Berrangé wrote: > This is a counterpart to the HMP "info profile" command. It is being > added with an "x-" prefix because this QMP command is intended as an > adhoc debugging tool and will thus not be modelled in QAPI as fully > structured data, nor will it have long t

Re: [PATCH v2 7/9] qapi: Generalize enum member policy checking

On 10/28/21 12:25, Markus Armbruster wrote: > The code to check enumeration value policy can see special feature > flag 'deprecated' in QEnumLookup member flags[value]. I want to make > feature flag 'unstable' visible there as well, so I can add policy for > it. > > Instead of extending flags[],

Re: [PATCH v2 4/9] qapi: Tools for sets of special feature flags in generated code

On 10/28/21 12:25, Markus Armbruster wrote: > New enum QapiSpecialFeature enumerates the special feature flags. > > New helper gen_special_features() returns code to represent a > collection of special feature flags as a bitset. > > The next few commits will put them to use. > > Signed-off-by: M

Re: [PATCH] target/mips: Remove obsolete FCR0_HAS2008 comment on P5600 CPU

在 2021/10/28 22:21, Philippe Mathieu-Daudé 写道: FCR0_HAS2008 flag has been enabled in commit ba5c79f2622 ("target-mips: indicate presence of IEEE 754-2008 FPU in R6/R5+MSA CPUs"), so remove the obsolete FIXME comment. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Jiaxun Yang Thanks.

Re: [PATCH] qtest: fix 'expression is always false' build failure in qtest_has_accel()

On Wed, 27 Oct 2021 17:59:44 +0200 Paolo Bonzini wrote: > On 27/10/21 09:45, Igor Mammedov wrote: > > If KVM is disabled or not present, qtest library build > > may fail with: > > libqtest.c: In function 'qtest_has_accel': > >comparison of unsigned expression < 0 is always false > >

Re: [PATCH v4 18/23] hw/intc/sh_intc: Simplify allocating sources array

On Fri, 29 Oct 2021, Philippe Mathieu-Daudé wrote: On 10/28/21 21:27, BALATON Zoltan wrote: Use g_new0 instead of g_malloc0 and avoid some unneeded temporary variable assignments. Signed-off-by: BALATON Zoltan --- hw/intc/sh_intc.c | 13 +++-- 1 file changed, 3 insertions(+), 10 delet

Re: [PATCH v4 02/23] hw/char/sh_serial: Use hw_error instead of fprintf and abort

On Fri, 29 Oct 2021, Philippe Mathieu-Daudé wrote: On 10/28/21 21:27, BALATON Zoltan wrote: It does the same with dumping some more state but avoids calling abort directly and printing to stderr from the device model. hw_error() is unfortunately misnamed, it is meant for CPU code, and we want

Re: [PATCH v4 06/23] hw/char/sh_serial: QOM-ify

On Fri, 29 Oct 2021, Philippe Mathieu-Daudé wrote: On 10/28/21 21:27, BALATON Zoltan wrote: Signed-off-by: BALATON Zoltan --- hw/char/sh_serial.c | 107 +++- hw/sh4/sh7750.c | 62 ++--- include/hw/sh4/sh.h | 9 +--- 3 files cha

Re: [PATCH 1/4] hw/core: Restrict sysemu specific files

On 2021/10/28 23:05, Philippe Mathieu-Daudé wrote: All these files don't make sense for tools and user emulation, restrict them to system emulation. Signed-off-by: Philippe Mathieu-Daudé --- hw/core/meson.build | 18 +- 1 file changed, 9 insertions(+), 9 deletions(-) diff

Re: [PATCH v4 18/23] hw/intc/sh_intc: Simplify allocating sources array

On 10/29/21 13:59, BALATON Zoltan wrote: > On Fri, 29 Oct 2021, Philippe Mathieu-Daudé wrote: >> On 10/28/21 21:27, BALATON Zoltan wrote: >>> Use g_new0 instead of g_malloc0 and avoid some unneeded temporary >>> variable assignments. >>> >>> Signed-off-by: BALATON Zoltan >>> --- >>>  hw/intc/sh_in

Re: [PATCH 2/4] hw/core: Declare meson source set

On 2021/10/28 23:05, Philippe Mathieu-Daudé wrote: As we want to be able to conditionally add files to the hw/core file list, use a source set. Signed-off-by: Philippe Mathieu-Daudé --- meson.build | 4 +++- hw/core/meson.build | 4 ++-- 2 files changed, 5 insertions(+), 3 deletio

Re: [PATCH 2/9] qapi: Mark unstable QMP parts with feature 'unstable'

On Mon, Oct 25, 2021 at 07:25:25AM +0200, Markus Armbruster wrote: > Add special feature 'unstable' everywhere the name starts with 'x-', > except for InputBarrierProperties member x-origin and > MemoryBackendProperties member x-use-canonical-path-for-ramblock-id, > because these two are actually s

Re: [PATCH v2 5/9] qapi: Generalize struct member policy checking

Juan Quintela writes: > Markus Armbruster wrote: >> The generated visitor functions call visit_deprecated_accept() and >> visit_deprecated() when visiting a struct member with special feature >> flag 'deprecated'. This makes the feature flag visible to the actual >> visitors. I want to make fe

Re: [PATCH v4 06/23] hw/char/sh_serial: QOM-ify

On 10/29/21 14:15, BALATON Zoltan wrote: > On Fri, 29 Oct 2021, Philippe Mathieu-Daudé wrote: >> On 10/28/21 21:27, BALATON Zoltan wrote: >>> Signed-off-by: BALATON Zoltan >>> --- >>>  hw/char/sh_serial.c | 107 +++- >>>  hw/sh4/sh7750.c |  62 +++

Re: [PATCH v2 5/9] qapi: Generalize struct member policy checking

On 10/28/21 12:25, Markus Armbruster wrote: > The generated visitor functions call visit_deprecated_accept() and > visit_deprecated() when visiting a struct member with special feature > flag 'deprecated'. This makes the feature flag visible to the actual > visitors. I want to make feature flag '

Re: [PATCH v4 06/23] hw/char/sh_serial: QOM-ify

On Fri, 29 Oct 2021, Philippe Mathieu-Daudé wrote: On 10/29/21 14:15, BALATON Zoltan wrote: On Fri, 29 Oct 2021, Philippe Mathieu-Daudé wrote: On 10/28/21 21:27, BALATON Zoltan wrote: Signed-off-by: BALATON Zoltan ---  hw/char/sh_serial.c | 107 +++-  hw

Re: [PATCH] failover: allow to pause the VM during the migration

"Dr. David Alan Gilbert" wrote: > * Laurent Vivier (lviv...@redhat.com) wrote: >> If we want to save a snapshot of a VM to a file, we used to follow the >> following steps: >> >> 1- stop the VM: >>(qemu) stop >> >> 2- migrate the VM to a file: >>(qemu) migrate "exec:cat > snapshot" >> >

Re: [PATCH] failover: allow to pause the VM during the migration

Laurent Vivier wrote: > If we want to save a snapshot of a VM to a file, we used to follow the > following steps: > > 1- stop the VM: >(qemu) stop > > 2- migrate the VM to a file: >(qemu) migrate "exec:cat > snapshot" > > 3- resume the VM: >(qemu) cont > > After that we can restore the

Re: [PATCH v2 5/9] qapi: Generalize struct member policy checking

Philippe Mathieu-Daudé writes: > On 10/28/21 12:25, Markus Armbruster wrote: >> The generated visitor functions call visit_deprecated_accept() and >> visit_deprecated() when visiting a struct member with special feature >> flag 'deprecated'. This makes the feature flag visible to the actual >> v

Re: [PATCH 8/9] qapi: Factor out compat_policy_input_ok()

Philippe Mathieu-Daudé writes: > On 10/26/21 11:46, Markus Armbruster wrote: >> Philippe Mathieu-Daudé writes: >> >>> On 10/25/21 07:25, Markus Armbruster wrote: The code to check policy for handling deprecated input is triplicated. Factor it out into compat_policy_input_ok() before I

[PATCH] vhost: Fix last queue index of devices with no cvq

The -1 assumes that all devices with no cvq have an spare vq allocated for them, but with no offer of VIRTIO_NET_F_CTRL_VQ. This may not be the case, and the device may have a pair number of queues. To fix this, just resort to the lower even number of queues. Fixes: 049eb15b5fc9 ("vhost: record t

Re: [PATCH v3 02/12] vfio-user: build library

Hi Stefan, > On Oct 27, 2021, at 11:17 AM, Stefan Hajnoczi wrote: > > On Mon, Oct 11, 2021 at 01:31:07AM -0400, Jagannathan Raman wrote: >> diff --git a/hw/remote/Kconfig b/hw/remote/Kconfig >> index 08c16e235f..f9e512d44a 100644 >> --- a/hw/remote/Kconfig >> +++ b/hw/remote/Kconfig >> @@ -1,4 +

[PATCH v3 0/3] Dynamic sysbus device check error report

Hi, Dynamic sysbus devices are allowed by a per-machine basis. Right now, the allowance check is done during an machine_init_done notifier, well after such devices are created. This series move the check at the right place (during the handling of a QMP device_add command or -device CLI option) so

[PATCH v3 2/3] qdev-monitor: Check sysbus device type before creating it

Add an early check to test if the requested sysbus device type is allowed by the current machine before creating the device. This impacts both -device cli option and device_add qmp command. Before this patch, the check was done well after the device has been created (in a machine init done notifie

[PATCH v3 1/3] machine: add device_type_is_dynamic_sysbus function

Right now the allowance check for adding a sysbus device using -device cli option (or device_add qmp command) is done well after the device has been created. It is done during the machine init done notifier: machine_init_notify() in hw/core/machine.c This new function will allow us to do the check

[PATCH v3 3/3] machine: remove the done notifier for dynamic sysbus device type check

Now that we check sysbus device types during device creation, we can remove the check in the machine init done notifier. This was the only thing done by this notifier, so we remove the whole sysbus_notifier structure of the MachineState. Note: This notifier was checking all /peripheral and /periph

Re: [PATCH v3 03/12] vfio-user: define vfio-user-server object

> On Oct 27, 2021, at 11:40 AM, Stefan Hajnoczi wrote: > > On Mon, Oct 11, 2021 at 01:31:08AM -0400, Jagannathan Raman wrote: >> diff --git a/qapi/qom.json b/qapi/qom.json >> index 0222bb4506..97de79cc36 100644 >> --- a/qapi/qom.json >> +++ b/qapi/qom.json >> @@ -705,6 +705,20 @@ >> { 'struct':

[Bug 1414466] Re: -net user,hostfwd=... is not working

I have had the same problem, I tried logging into a buildroot image that was started using the following command line: qemu-system-i386 -drive file=output/images/disk.img,format=raw,index=0,media=disk -vga std -nic user,ipv6=off,model=e1000,mac=10:10:10:10:10:10,hostfwd=tcp::4000-:22 The ssh

Re: [RFC PATCH v1 1/3] virtio: introduce virtio_force_modern()

On Fri, Oct 29 2021, Halil Pasic wrote: > Legacy vs modern should be detected via transport specific means. We > can't wait till feature negotiation is done. Let us introduce > virtio_force_modern() as a means for the transport code to signal > that the device should operate in modern mode (becau

Re: [PATCH v3 04/12] vfio-user: instantiate vfio-user context

> On Oct 27, 2021, at 11:59 AM, Stefan Hajnoczi wrote: > > On Mon, Oct 11, 2021 at 01:31:09AM -0400, Jagannathan Raman wrote: >> @@ -94,9 +101,31 @@ static void vfu_object_set_device(Object *obj, const >> char *str, Error **errp) >> trace_vfu_prop("device", str); >> } >> >> +/* >> + * vfi

Re: [PATCH v2 9/9] qapi: Extend -compat to set policy for unstable interfaces

On Thu, Oct 28, 2021 at 12:25:20PM +0200, Markus Armbruster wrote: > New option parameters unstable-input and unstable-output set policy > for unstable interfaces just like deprecated-input and > deprecated-output set policy for deprecated interfaces (see commit > 6dd75472d5 "qemu-options: New -com

Re: [PATCH v2 9/9] qapi: Extend -compat to set policy for unstable interfaces

Eric Blake writes: > On Thu, Oct 28, 2021 at 12:25:20PM +0200, Markus Armbruster wrote: >> New option parameters unstable-input and unstable-output set policy >> for unstable interfaces just like deprecated-input and >> deprecated-output set policy for deprecated interfaces (see commit >> 6dd7547

Re: [PATCH v2 5/9] qapi: Generalize struct member policy checking

On Thu, Oct 28, 2021 at 12:25:16PM +0200, Markus Armbruster wrote: > The generated visitor functions call visit_deprecated_accept() and > visit_deprecated() when visiting a struct member with special feature > flag 'deprecated'. This makes the feature flag visible to the actual > visitors. I want

[PATCH 0/5] target/riscv: Initial support for native debug feature via M-mode CSRs

This adds initial support for the native debug via the Trigger Module, as defined in the RISC-V Debug Specification [1]. Only "Address / Data Match" trigger (type 2) is implemented as of now, which is mainly used for hardware breakpoint and watchpoint. The number of type 2 triggers implemented i

[PATCH 2/5] target/riscv: debug: Implement debug related TCGCPUOps

Implement .debug_excp_handler, .debug_check_{breakpoint, watchpoint} TCGCPUOps and hook them into riscv_tcg_ops. Signed-off-by: Bin Meng --- target/riscv/debug.h | 4 +++ target/riscv/cpu.c | 3 ++ target/riscv/debug.c | 75 3 files changed, 82 i

[PATCH 4/5] target/riscv: csr: Hook debug CSR read/write

This adds debug CSR read/write support to the RISC-V CSR RW table. Signed-off-by: Bin Meng --- target/riscv/cpu.c | 6 + target/riscv/csr.c | 57 ++ 2 files changed, 63 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 3a2

[PATCH 3/5] target/riscv: Add a config option for native debug

Add a config option to enable support for native M-mode debug. This is enabled by default and can be disabled with 'debug=false'. Signed-off-by: Bin Meng --- target/riscv/cpu.h | 2 ++ target/riscv/cpu.c | 5 + 2 files changed, 7 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv

[PATCH 1/5] target/riscv: Add initial support for native debug

This adds initial support for the native debug via the Trigger Module, as defined in the RISC-V Debug Specification [1]. Only "Address / Data Match" trigger (type 2) is implemented as of now, which is mainly used for hardware breakpoint and watchpoint. The number of type 2 triggers implemented is

[PATCH 5/5] hw/core: tcg-cpu-ops.h: Update comments of debug_check_watchpoint()

This is now used by RISC-V as well. Update the comments. Signed-off-by: Bin Meng --- include/hw/core/tcg-cpu-ops.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h index 6cbe17f2e6..532c148a80 100644 --- a/include/hw/core/tcg-cpu

Re: [PATCH v2 5/5] pc/q35: Add pre-plug hook for x86-iommu

On Fri, 29 Oct 2021 10:53:07 +0800 Peter Xu wrote: > On Thu, Oct 28, 2021 at 10:11:35AM -0600, Alex Williamson wrote: > > Better. Like the class layering proposal, a downside is that the > > driver needs to be aware that it's imposing this requirement to be able > > to mark it in the class init

Re: [PATCH v2 6/9] qapi: Generalize command policy checking

On Thu, Oct 28, 2021 at 12:25:17PM +0200, Markus Armbruster wrote: > The code to check command policy can see special feature flag > 'deprecated' as command flag QCO_DEPRECATED. I want to make feature > flag 'unstable' visible there as well, so I can add policy for it. > > To let me make it visib

Re: [PATCH v2 5/9] qapi: Generalize struct member policy checking

Eric Blake writes: > On Thu, Oct 28, 2021 at 12:25:16PM +0200, Markus Armbruster wrote: >> The generated visitor functions call visit_deprecated_accept() and >> visit_deprecated() when visiting a struct member with special feature >> flag 'deprecated'. This makes the feature flag visible to the

Re: [PULL 0/2] Hexagon (target/hexagon) cleanup and bug fix

On 10/28/21 9:02 PM, Taylor Simpson wrote: The following changes since commit c52d69e7dbaaed0ffdef8125e79218672c30161d: Merge remote-tracking branch 'remotes/cschoenebeck/tags/pull-9p-20211027' into staging (2021-10-27 11:45:18 -0700) are available in the git repository at: https://gith

Re: [PATCH v3 05/12] vfio-user: find and init PCI device

> On Oct 27, 2021, at 12:05 PM, Stefan Hajnoczi wrote: > > On Mon, Oct 11, 2021 at 01:31:10AM -0400, Jagannathan Raman wrote: >> Find the PCI device with specified id. Initialize the device context >> with the QEMU PCI device >> >> Signed-off-by: Elena Ufimtseva >> Signed-off-by: John G Johns

Re: [PATCH 13/24] bsd-user/arm/target_arch_thread.h: Routines to create and switch to a thread

On 10/28/21 12:45 PM, Warner Losh wrote: (2) Changes to CPSR cannot be made manually; you need cpsr_write. So would +        cpsr_write(env, cpsr_read(env) | CPSR_T, CPSR_T, CPSRWriteByInstr); cover what's needed here? You can use cpsr_write(env, CPSR_T, CPSR_T, CPSRWriteByInstr);

Re: [PATCH v2 5/9] qapi: Generalize struct member policy checking

On 10/29/21 16:01, Markus Armbruster wrote: > Philippe Mathieu-Daudé writes: > >> On 10/28/21 12:25, Markus Armbruster wrote: >>> The generated visitor functions call visit_deprecated_accept() and >>> visit_deprecated() when visiting a struct member with special feature >>> flag 'deprecated'. Th

Re: [PATCH v3 04/32] target/mips: Use dup_const() to simplify

On 10/28/21 2:08 PM, Philippe Mathieu-Daudé wrote: The dup_const() helper makes the code easier to follow, use it. Suggested-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- v3: Fix eval_big --- target/mips/tcg/msa_translate.c | 23 +++ 1 file changed, 3 ins

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