iothread is a string property, so None (= JSON null) is not a valid
value for it. Pass the empty string instead to get the default iothread.
Signed-off-by: Kevin Wolf
Reviewed-by: Vladimir Sementsov-Ogievskiy
Message-Id: <20211008133442.141332-6-kw...@redhat.com>
Reviewed-by: Michael S. Tsirkin
vhost-vdpa works only with specific devices. At startup, it second
guesses what the command line option handling will do and error out if
it thinks a non-virtio device will attach to them.
This second guessing is not only ugly, it can lead to wrong error
messages ('-device floppy,netdev=foo' shoul
The only thing the string visitor adds compared to a keyval visitor is
list support. git grep for 'visit_start_list' and 'visit.*List' shows
that devices don't make use of this.
In a world with a QAPIfied command line interface, the keyval visitor is
used to parse the command line. In order to mak
hide_device() is used for virtio-net failover, where the standby virtio
device delays creation of the primary device. It only makes sense to
have a single primary device for each standby device. Adding a second
one should result in an error instead of hiding it and never using it
afterwards.
Prepa
vhost-user works only with specific devices. At startup, it second
guesses what the command line option handling will do and error out if
it thinks a non-virtio device will attach to them.
This second guessing is not only ugly, it can lead to wrong error
messages ('-device floppy,netdev=foo' shoul
The iothread isn't called 'iothread0', but 'thread0'. Depending on the
order that properties are parsed, the error message may change from the
expected one to another one saying that the iothread doesn't exist.
Signed-off-by: Kevin Wolf
Reviewed-by: Vladimir Sementsov-Ogievskiy
Message-Id: <2021
ERRP_GUARD() makes debugging easier by making sure that &error_abort
still fails at the real origin of the error instead of
error_propagate().
Signed-off-by: Kevin Wolf
Message-Id: <20211008133442.141332-5-kw...@redhat.com>
Reviewed-by: Markus Armbruster
Reviewed-by: Michael S. Tsirkin
Tested-b
Instead of accessing the global QemuOptsList, which really belong to the
command line parser and shouldn't be accessed from devices, store a
pointer to the QemuOpts in a new VirtIONet field.
This is not the final state, but just an intermediate step to get rid of
QemuOpts in devices. It will later
Use QTAILQ_FOREACH_SAFE() so that the current QemuOpts can be deleted
while iterating through the whole list.
Signed-off-by: Kevin Wolf
Reviewed-by: Vladimir Sementsov-Ogievskiy
Message-Id: <20211008133442.141332-11-kw...@redhat.com>
Reviewed-by: Michael S. Tsirkin
Tested-by: Peter Krempa
Sign
From: Damien Hedde
qdev_set_id() is mostly used when the user adds a device (using
-device cli option or device_add qmp command). This commit adds
an error parameter to handle the case where the given id is
already taken.
Also document the function and add a return value in order to
be able to c
On 14/10/2021 20:43, Richard Henderson wrote:
[E-MAIL EXTERNO] Não clique em links ou abra anexos, a menos que você
possa confirmar o remetente e saber que o conteúdo é seguro. Em caso de
e-mail suspeito entre imediatamente em contato com o DTI.
On 10/14/21 3:32 PM, matheus.fe...@eldorado.org.
DeviceState.id is a pointer to a string that is stored in the QemuOpts
object DeviceState.opts and freed together with it. We want to create
devices without going through QemuOpts in the future, so make this a
separately allocated string.
Signed-off-by: Kevin Wolf
Reviewed-by: Vladimir Sementsov-
QDicts are both what QMP natively uses and what the keyval parser
produces. Going through QemuOpts isn't useful for either one, so switch
the main device creation function to QDicts. By sharing more code with
the -object/object-add code path, we can even reduce the code size a
bit.
This commit doe
Don't go through the global QemuOptsList, it is state of the legacy
command line parser and we will create devices that are not contained
in it. It is also just the command line configuration and not
necessarily the current runtime state.
Instead, look at the qdev device tree which has the current
Like we already do for -object, introduce support for JSON syntax in
-device, which can be kept stable in the long term and guarantees that a
single code path with identical behaviour is used for both QMP and the
command line. Compared to the QemuOpts based code, the parser contains
less surprises
On Fri, Aug 27, 2021 at 02:48:16PM +0800, Chenyi Qiang wrote:
> Patch 1:
> https://lore.kernel.org/qemu-devel/20210825195438.914387-2-ehabk...@redhat.com/
>
> Patch 2 removes one more feature (core-capability) in Snowridge-v4 CPU
> model based on previous patch.
>
> Chenyi Qiang (2):
> target/
On Thu, Sep 09, 2021 at 10:41:46PM +0800, Xiaoyao Li wrote:
> Some CPUID leaves have meaningful subleaf index. Print the subleaf info
> in feature_word_description for CPUID features.
>
> Signed-off-by: Xiaoyao Li
Reviewed-by: Eduardo Habkost
--
Eduardo
- Remove stray texinfo syntax (remnants of texinfo to rST conversion)
- Clarify the bit about long-term stable CPU models
TODO: In a future patch, include potential examples as discussed
here[1].
[1] https://lists.nongnu.org/archive/html/qemu-devel/2021-10/msg03411.html
-- On versioned
Paolo Bonzini writes:
> eBPF libraries are being included in user emulators, which is useless and
> also breaks --static compilation if a shared library for libbpf is
> present in the system.
>
> Reported-by: Alex Bennée
> Signed-off-by: Paolo Bonzini
Reviewed-by: Alex Bennée
Tested-by: Ale
Pavel Labath writes:
> Ping.
>
> (This is my first qemu patch, so please let me know if I am doing
> something wrong.)
Apologies it slipped though the cracks. I shall have a look on Monday.
>
> regards,
> pavel
>
> On 30/09/2021 11:51, Pavel Labath wrote:
>> Respond with Txxthread:; inste
Hi,
Apologies for the delay. Comments below:
On Thu, Sep 09, 2021 at 10:41:47PM +0800, Xiaoyao Li wrote:
> CPUID leaf 0x14 subleaf 0x0 and 0x1 enumerate the resource and
> capability of Intel PT.
>
> Introduce FeatureWord FEAT_14_0_EBX, FEAT_14_1_EAX and FEAT_14_1_EBX,
> and complete FEAT_14_0_
Commit 7bed89958bfb ("device_core: use drain_call_rcu in in qmp_device_add")
introduced a regression in QEMU 6.0 : passing device_add without argument
hangs the monitor. This was reported against qemu-system-mips64 with TGC,
but I could consistently reproduce it with other targets (x86 and ppc64).
A TCG vCPU doing a busy loop systematicaly hangs the QEMU monitor
if the user passes 'device_add' without argument. This is because
drain_cpu_all() which is called from qmp_device_add() cannot return
if readers don't exit read-side critical sections. That is typically
what busy-looping TCG vCPUs do
The drain_rcu_call() function can be blocked as long as an RCU reader
stays in a read-side critical section. This is typically what happens
when a TCG vCPU is executing a busy loop. It can deadlock the QEMU
monitor as reported in https://gitlab.com/qemu-project/qemu/-/issues/650 .
This can be avoi
On Wed, Oct 13, 2021 at 05:10:35AM -0400, Michael S. Tsirkin wrote:
> On Tue, Oct 12, 2021 at 06:06:46PM +0200, Lukasz Maniak wrote:
> > On Tue, Oct 12, 2021 at 03:25:12AM -0400, Michael S. Tsirkin wrote:
> > > On Thu, Oct 07, 2021 at 06:23:55PM +0200, Lukasz Maniak wrote:
> > > > PCIe devices impl
Hello everyone.
I have a x86_64 L1 guest, running on a x86_64 host, with a
host-pci-device attached to the guest.
The host runs with IOMMU enabled, and passthrough enabled.
Following are the addresses of the bar0-region of the pci-device, as
per the output of lspci -v :
* On host (hpa) => e2c200
On 10/14/21 11:54 PM, frank.ch...@sifive.com wrote:
+/*
+ * In IEEE 754-2019, minNum, maxNum, minNumMag and maxNumMag
+ * are removed and replaced with minimum, minimumNumber, maximum
+ * and maximumNumber.
+ * minimumNumber/maximumNumber behavior for SNaN
On 10/14/21 11:54 PM, frank.ch...@sifive.com wrote:
From: Chih-Min Chao
The sNaN propagation behavior has been changed since
cd20cee7 inhttps://github.com/riscv/riscv-isa-manual
Signed-off-by: Chih-Min Chao
---
target/riscv/fpu_helper.c | 8
1 file changed, 4 insertions(+), 4 deleti
On Fri, Oct 15, 2021 at 06:24:14PM +0200, Lukasz Maniak wrote:
> On Wed, Oct 13, 2021 at 05:10:35AM -0400, Michael S. Tsirkin wrote:
> > On Tue, Oct 12, 2021 at 06:06:46PM +0200, Lukasz Maniak wrote:
> > > On Tue, Oct 12, 2021 at 03:25:12AM -0400, Michael S. Tsirkin wrote:
> > > > On Thu, Oct 07, 2
Hi all,
On Thu, 14 Oct 2021 at 09:28, Tom Rini wrote:
>
> On Thu, Oct 14, 2021 at 09:17:52AM -0600, Simon Glass wrote:
> > Hi Tom,
> >
> > On Thu, 14 Oct 2021 at 08:56, Tom Rini wrote:
> > >
> > > On Wed, Oct 13, 2021 at 12:06:02PM -0600, Simon Glass wrote:
> > > > Hi François,
> > > >
> > > > O
On Thu, Oct 14, 2021 at 10:10 PM Richard Henderson <
richard.hender...@linaro.org> wrote:
> Split out a function to adjust the raw signal pc into a
> value that could be passed to cpu_restore_state.
>
> Reviewed-by: Philippe Mathieu-Daudé
> Signed-off-by: Richard Henderson
> ---
> v2: Adjust pc
From: Matheus Ferst
PowerISA says that mtmsr[d] "does not alter MSR[HV], MSR[S], MSR[ME], or
MSR[LE]", but the current code only filters the GPR-provided value if
L=1. This behavior caused some problems in FreeBSD, and a build option
was added to work around the issue [1], but it seems that the b
On Thu, Oct 14, 2021 at 10:10 PM Richard Henderson <
richard.hender...@linaro.org> wrote:
> This is the major portion of handle_cpu_signal which is specific
> to tcg, handling the page protections for the translations.
> Most of the rest will migrate to linux-user/ shortly.
>
> Reviewed-by: Philip
On Thu, Oct 14, 2021 at 10:10 PM Richard Henderson <
richard.hender...@linaro.org> wrote:
> Remove the comment about siglongjmp. We do use sigsetjmp
> in the main cpu loop, but we do not save the signal mask
> as most exits from the cpu loop do not require them.
>
> Signed-off-by: Richard Henders
On Thu, Oct 14, 2021 at 2:00 PM Eugenio Perez Martin
wrote:
>
> On Wed, Oct 13, 2021 at 5:27 AM Jason Wang wrote:
> >
> >
> > 在 2021/10/1 下午3:05, Eugenio Pérez 写道:
> > > Shadow virtqueue notifications forwarding is disabled when vhost_dev
> > > stops, so code flow follows usual cleanup.
> > >
> >
On Thu, Oct 14, 2021 at 10:10 PM Richard Henderson <
richard.hender...@linaro.org> wrote:
> The existing code for safe-syscall.inc.S will compile
> without change for riscv32 and riscv64. We may also
> drop the meson.build stanza that merges them for tcg/.
>
> Reviewed-by: Philippe Mathieu-Daudé
On Thu, Oct 14, 2021 at 10:11 PM Richard Henderson <
richard.hender...@linaro.org> wrote:
> Split host_signal_pc and host_signal_write out of user-exec.c.
> Drop the *BSD code, to be re-created under bsd-user/ later.
>
> Signed-off-by: Richard Henderson
> ---
> linux-user/host/i386/host-signal.h
On 10/15/21 7:54 AM, Matheus K. Ferst wrote:
While Appendix B does guarantee that "0" is and always will be an invalid
instruction, I
wonder if the test itself would be clearer (i.e. self-documenting the intent)
using
SIGTRAP and "trap".
r~
It would be better, but cpu_loop is currently call
On Thu, Oct 14, 2021 at 10:11 PM Richard Henderson <
richard.hender...@linaro.org> wrote:
> Split host_signal_pc and host_signal_write out of user-exec.c.
> Drop the *BSD code, to be re-created under bsd-user/ later.
>
> Reviewed-by: Philippe Mathieu-Daudé
> Signed-off-by: Richard Henderson
> --
On Thu, Oct 14, 2021 at 10:11 PM Richard Henderson <
richard.hender...@linaro.org> wrote:
> Split host_signal_pc and host_signal_write out of user-exec.c.
> Drop the *BSD code, to be re-created under bsd-user/ later.
> Drop the Solaris code as completely unused.
>
> Signed-off-by: Richard Henderso
On Thu, Oct 14, 2021 at 10:11 PM Richard Henderson <
richard.hender...@linaro.org> wrote:
> Split host_signal_pc and host_signal_write out of user-exec.c.
>
> Reviewed-by: Philippe Mathieu-Daudé
> Signed-off-by: Richard Henderson
> ---
> linux-user/host/mips/host-signal.h | 62 +
On Thu, Oct 14, 2021 at 10:11 PM Richard Henderson <
richard.hender...@linaro.org> wrote:
> The named function no longer exists.
> Refer to host_signal_handler instead.
>
> Signed-off-by: Richard Henderson
> ---
> target/arm/sve_helper.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
On Thu, Oct 14, 2021 at 10:11 PM Richard Henderson <
richard.hender...@linaro.org> wrote:
> Split host_signal_pc and host_signal_write out of user-exec.c.
> Drop the *BSD code, to be re-created under bsd-user/ later.
>
> Signed-off-by: Richard Henderson
> ---
> linux-user/host/aarch64/host-signa
On Thu, Oct 14, 2021 at 10:11 PM Richard Henderson <
richard.hender...@linaro.org> wrote:
> Because of the complexity of setting ESR, continue to use
> arm_deliver_fault. This means we cannot remove the code
> within cpu_loop that decodes EXCP_DATA_ABORT and
> EXCP_PREFETCH_ABORT.
>
> But using t
On Thu, Oct 14, 2021 at 10:11 PM Richard Henderson <
richard.hender...@linaro.org> wrote:
> Split host_signal_pc and host_signal_write out of user-exec.c.
>
> Reviewed-by: Alistair Francis
> Signed-off-by: Richard Henderson
> ---
> linux-user/host/riscv/host-signal.h | 85 +-
>
On Thu, Oct 14, 2021 at 10:11 PM Richard Henderson <
richard.hender...@linaro.org> wrote:
> The fallback code in cpu_loop_exit_sigsegv is sufficient
> for mips linux-user.
>
> This means we can remove tcg/user/tlb_helper.c entirely.
> Remove the code from cpu_loop that raised SIGSEGV.
>
> Reviewed
On Thu, Oct 14, 2021 at 10:11 PM Richard Henderson <
richard.hender...@linaro.org> wrote:
> Use the new os interface for raising the exception,
> rather than calling arm_cpu_tlb_fill directly.
>
> Reviewed-by: Philippe Mathieu-Daudé
> Signed-off-by: Richard Henderson
> ---
> target/arm/mte_help
On Thu, Oct 14, 2021 at 10:11 PM Richard Henderson <
richard.hender...@linaro.org> wrote:
> Record DAR, DSISR, and exception_index. That last means
> that we must exit to cpu_loop ourselves, instead of letting
> exception_index being overwritten.
>
> This is exactly what the user-mode ppc_cpu_tlb
On Thu, Oct 14, 2021 at 10:11 PM Richard Henderson <
richard.hender...@linaro.org> wrote:
> The fallback code in cpu_loop_exit_sigsegv is sufficient
> for riscv linux-user.
>
> Remove the code from cpu_loop that raised SIGSEGV.
>
> Reviewed-by: Alistair Francis
> Reviewed-by: Philippe Mathieu-Dau
On Thu, Oct 14, 2021 at 10:14 PM Richard Henderson <
richard.hender...@linaro.org> wrote:
> Add a new user-only interface for updating cpu state before
> raising a signal. This will take the place of do_unaligned_access
> for user-only and should result in less boilerplate for each guest.
>
> Sig
On Thu, Oct 14, 2021 at 10:14 PM Richard Henderson <
richard.hender...@linaro.org> wrote:
> This is a new interface to be provided by the os emulator for
> raising SIGBUS on fault. Use the new record_sigbus target hook.
>
> Signed-off-by: Richard Henderson
> ---
> include/exec/exec-all.h | 14 +
This patchset introduces support for the ACPI Error Record
Serialization Table, ERST.
For background and implementation information, please see
docs/specs/acpi_erst.rst, which is patch 2/10.
Suggested-by: Konrad Wilk
Signed-off-by: Eric DeVolder
---
v8: 15oct2021
- Added Kconfig option for ER
This change reserves the PCI device_id for the new ACPI ERST
device.
Signed-off-by: Eric DeVolder
Acked-by: Igor Mammedov
Acked-by: Ani Sinha
---
include/hw/pci/pci.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h
index 7fc9013..45b79b1 100644
-
This change introduces the public defintions for ACPI ERST.
Signed-off-by: Eric DeVolder
---
include/hw/acpi/erst.h | 19 +++
1 file changed, 19 insertions(+)
create mode 100644 include/hw/acpi/erst.h
diff --git a/include/hw/acpi/erst.h b/include/hw/acpi/erst.h
new file mode 10
Following the guidelines in tests/qtest/bios-tables-test.c, this
is step 6.
Below is the disassembly of an ERST table, tests/data/acpi/pc/ERST.
This is a PCI device and as such its base address can change; it
is possible for the address fields to differ between this and other
ERST tables.
[000h 0
Information on the implementation of the ACPI ERST support.
Signed-off-by: Eric DeVolder
Acked-by: Ani Sinha
---
docs/specs/acpi_erst.rst | 200 +++
1 file changed, 200 insertions(+)
create mode 100644 docs/specs/acpi_erst.rst
diff --git a/docs/spec
Following the guidelines in tests/qtest/bios-tables-test.c, this
change adds empty placeholder files per step 1 for the new ERST
table, and excludes resulting changed files in bios-tables-test-allowed-diff.h
per step 2.
Signed-off-by: Eric DeVolder
Acked-by: Igor Mammedov
---
tests/data/acpi/mi
This implements a PCI device for ACPI ERST. This implements the
non-NVRAM "mode" of operation for ERST as it is supported by
Linux and Windows.
Signed-off-by: Eric DeVolder
---
hw/acpi/Kconfig | 6 +
hw/acpi/erst.c | 836 +++
hw/acpi/m
This builds the ACPI ERST table to inform OSPM how to communicate
with the acpi-erst device.
Signed-off-by: Eric DeVolder
---
hw/acpi/erst.c | 241 +
1 file changed, 241 insertions(+)
diff --git a/hw/acpi/erst.c b/hw/acpi/erst.c
index 4304
This change provides a qtest that locates and then does a simple
interrogation of the ERST feature within the guest.
Signed-off-by: Eric DeVolder
---
tests/qtest/erst-test.c | 167
tests/qtest/meson.build | 2 +
2 files changed, 169 insertions(+
On Thu, Oct 14, 2021 at 10:14 PM Richard Henderson <
richard.hender...@linaro.org> wrote:
> To be called from tcg generated code on hosts that support
> unaligned accesses natively, in response to an access that
> is supposed to be aligned.
>
> Reviewed-by: Peter Maydell
> Signed-off-by: Richard
This change implements the test suite checks for the ERST table.
Signed-off-by: Eric DeVolder
---
tests/qtest/bios-tables-test.c | 55 ++
1 file changed, 55 insertions(+)
diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c
index 4
On Thu, Oct 14, 2021 at 10:14 PM Richard Henderson <
richard.hender...@linaro.org> wrote:
> This is not used by, nor required by, user-only.
>
> Signed-off-by: Richard Henderson
> ---
> target/ppc/internal.h| 8 +++-
> target/ppc/excp_helper.c | 8 +++-
> 2 files changed, 6 insertion
This change exposes ACPI ERST support for x86 guests.
Signed-off-by: Eric DeVolder
---
hw/i386/acpi-build.c | 9 +
hw/i386/acpi-microvm.c | 9 +
include/hw/acpi/erst.h | 5 +
3 files changed, 23 insertions(+)
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index 8
On Thu, Oct 14, 2021 at 10:14 PM Richard Henderson <
richard.hender...@linaro.org> wrote:
> Use the new cpu_loop_exit_sigbus for cpu_mmu_lookup.
>
> Reviewed-by: Peter Maydell
> Signed-off-by: Richard Henderson
> ---
> accel/tcg/user-exec.c | 7 ++-
> 1 file changed, 6 insertions(+), 1 dele
On 10/15/21 4:08 AM, Christian Borntraeger wrote:
Am 13.10.21 um 11:07 schrieb Paolo Bonzini:
From: Markus Armbruster
Commit 6287d827d4 "monitor: allow device_del to accept QOM paths"
extended find_device_state() to accept QOM paths in addition to qdev
IDs. This added a checked conversion to
On Thu, Oct 14, 2021 at 10:14 PM Richard Henderson <
richard.hender...@linaro.org> wrote:
> This requires extra work for each target, but adds the
> common syscall code, and the necessary flag in CPUState.
>
> Signed-off-by: Richard Henderson
> ---
> include/hw/core/cpu.h |
On Thu, Oct 14, 2021 at 10:14 PM Richard Henderson <
richard.hender...@linaro.org> wrote:
> Because of the complexity of setting ESR, re-use the existing
> arm_cpu_do_unaligned_access function. This means we have to
> handle the exception ourselves in cpu_loop, transforming it
> to the appropriat
On 10/15/21 2:16 AM, Thomas Huth wrote:
Hi!
The following changes since commit bfd9a76f9c143d450ab5545dedfa74364b39fc56:
Merge remote-tracking branch 'remotes/stsquad/tags/pull-for-6.2-121021-2'
into staging (2021-10-12 06:16:25 -0700)
are available in the Git repository at:
https://
On Thu, Oct 14, 2021 at 10:14 PM Richard Henderson <
richard.hender...@linaro.org> wrote:
> Use the new cpu_loop_exit_sigbus for atomic_mmu_lookup, which
> has access to complete alignment info from the TCGMemOpIdx arg.
>
> Reviewed-by: Alex Bennée
> Signed-off-by: Richard Henderson
> ---
> acc
Signed-off-by: Alexey Baturo
---
target/riscv/cpu.c | 2 +
target/riscv/cpu.h | 11 ++
target/riscv/csr.c | 285 +
3 files changed, 298 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 1d69d1887e..75e8b8ca83 100644
--- a/targ
Signed-off-by: Alexey Baturo
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
Reviewed-by: Bin Meng
---
target/riscv/cpu.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 9e55b2f5b1..3f28dc5f3a 100644
--- a/target/riscv/cpu.h
+++
v13:
Rebased QEMU and addressed Richard's comment.
v12:
Updated function for adjusting address with pointer masking to allocate and use
temp register.
v11:
Addressed a few style issues Alistair mentioned in the previous review.
If this patch series would be accepted, I think my further attentio
Signed-off-by: Alexey Baturo
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/cpu.c | 25 +
1 file changed, 25 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 75e8b8ca83..7f9dde70b7 100644
--- a/target/riscv/cpu.c
++
Signed-off-by: Alexey Baturo
Reviewed-by: Alistair Francis
---
target/riscv/cpu_bits.h | 96 +
1 file changed, 96 insertions(+)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 999187a9ee..1a3767804a 100644
--- a/target/riscv/cpu_bits.
From: Anatoly Parshintsev
Signed-off-by: Anatoly Parshintsev
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/cpu.h | 20 ++
target/riscv/translate.c | 56 +---
2 files changed, 66 insertions(+), 10 deletions(-
Signed-off-by: Alexey Baturo
---
target/riscv/cpu.c | 4
1 file changed, 4 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 7f9dde70b7..fb08c0ffb8 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -558,6 +558,9 @@ static void riscv_cpu_realize(DeviceState *
On 15/10/2021 07:14, Laurent Vivier wrote:
Le 13/10/2021 à 23:21, Mark Cave-Ayland a écrit :
According to both Linux and NetBSD, port B bit 6 is used on the Quadra 800 to
configure the GLUE logic in A/UX mode. Whilst the name VIA1B_vMystery isn't
particularly descriptive, the patch leaves this
Signed-off-by: Alexey Baturo
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/insn_trans/trans_rva.c.inc | 3 +++
target/riscv/insn_trans/trans_rvd.c.inc | 2 ++
target/riscv/insn_trans/trans_rvf.c.inc | 2 ++
target/riscv/insn_trans/trans_rvi.c.inc | 2 ++
targ
On 15/10/2021 07:31, Laurent Vivier wrote:
Le 13/10/2021 à 23:21, Mark Cave-Ayland a écrit :
In order to allow dynamic routing of IRQs to different IRQ levels on the CPU
depending upon port B bit 6, use GLUE IRQ numbers and map them to the the
corresponding CPU IRQ level accordingly.
Signed-of
On 10/15/21 11:30 AM, Warner Losh wrote:
+ /*
+ * Fall back to parsing instructions; will only be needed
+ * for really ancient (pre-3.16) kernels.
+ */
+ insn = *(uint32_t *)host_signal_pc(uc);
+
+ return (insn & 0xbfff) == 0x0c00 /* C3.
On 15/10/2021 07:58, Laurent Vivier wrote:
Le 13/10/2021 à 23:21, Mark Cave-Ayland a écrit :
Add a new auxmode GPIO that is updated when port B bit 6 is changed indicating
whether the hardware is configured for A/UX mode.
Signed-off-by: Mark Cave-Ayland
---
hw/misc/mac_via.c | 18 ++
On 15/10/2021 08:17, Laurent Vivier wrote:
Le 13/10/2021 à 23:21, Mark Cave-Ayland a écrit :
Add a new auxmode GPIO that is updated when port B bit 6 is changed indicating
whether the hardware is configured for A/UX mode.
Stupid question: why do you use GPIO to pass the auxmode information be
On 15/10/2021 09:40, Laurent Vivier wrote:
Le 13/10/2021 à 23:21, Mark Cave-Ayland a écrit :
This allows the programmer's switch to be triggered via the monitor for
debugging
purposes. Since the CPU level 7 interrupt is level-triggered, use a timer to
hold
the NMI active for 100ms before rele
On Thu, Sep 09, 2021 at 10:41:48PM +0800, Xiaoyao Li wrote:
> commit e37a5c7fa459 ("i386: Add Intel Processor Trace feature support")
> added the support of Intel PT by making CPUID[14] of PT as fixed feature
> set (from ICX) for any CPU model on any host.
>
> This truly breaks the PT exposing on
On 10/15/21 7:46 AM, Kevin Wolf wrote:
The following changes since commit 4d1a525dfafe995a98bb486e702da09e31b68b9c:
Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into
staging (2021-10-14 10:49:38 -0700)
are available in the Git repository at:
git://repo.or.cz/qemu/kev
Signed-off-by: Tong Ho
---
hw/nvram/xlnx-versal-efuse-ctrl.c | 20 +++-
1 file changed, 15 insertions(+), 5 deletions(-)
diff --git a/hw/nvram/xlnx-versal-efuse-ctrl.c
b/hw/nvram/xlnx-versal-efuse-ctrl.c
index d362376703..b35ba65ab5 100644
--- a/hw/nvram/xlnx-versal-efuse-ctrl.c
Signed-off-by: Tong Ho
---
hw/nvram/xlnx-zynqmp-efuse.c | 18 --
1 file changed, 12 insertions(+), 6 deletions(-)
diff --git a/hw/nvram/xlnx-zynqmp-efuse.c b/hw/nvram/xlnx-zynqmp-efuse.c
index 1f87dbf988..228ba0bbfa 100644
--- a/hw/nvram/xlnx-zynqmp-efuse.c
+++ b/hw/nvram/xlnx-zy
Signed-off-by: Tong Ho
---
hw/nvram/xlnx-efuse.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/hw/nvram/xlnx-efuse.c b/hw/nvram/xlnx-efuse.c
index ee1caab54c..a0fd77b586 100644
--- a/hw/nvram/xlnx-efuse.c
+++ b/hw/nvram/xlnx-efuse.c
@@ -144,10 +144,11 @@ static bool
This series fixes memory leaks in Xilinx eFUSE devices for
the Versal and ZynqMP product families.
The leaks result from failing to free memory allocated
by object_get_canonical_path().
Tong Ho (3):
hw/nvram: Fix Memory Leak in Xilinx eFuse QOM
hw/nvram: Fix Memory Leak in Xilinx Versal eFuse
On 10/15/21 12:03 AM, frank.ch...@sifive.com wrote:
+#define REQUIRE_ZFH(ctx) do { \
+if (!ctx->ext_zfh)\
+return false; \
+} while (0)
Missing braces for if.
Otherwise,
Reviewed-by: Richard Henderson
r~
On 10/15/21 12:03 AM, frank.ch...@sifive.com wrote:
From: Kito Cheng
Signed-off-by: Kito Cheng
Signed-off-by: Chih-Min Chao
Signed-off-by: Frank Chang
---
target/riscv/fpu_helper.c | 82 ++
target/riscv/helper.h | 13 +++
target/riscv/insn32.
On 10/15/21 12:03 AM, frank.ch...@sifive.com wrote:
From: Kito Cheng
Signed-off-by: Kito Cheng
Signed-off-by: Chih-Min Chao
Signed-off-by: Frank Chang
---
target/riscv/fpu_helper.c | 67 +
target/riscv/helper.h | 12 +
target/riscv/insn32.decode
On 10/15/21 12:03 AM, frank.ch...@sifive.com wrote:
From: Kito Cheng
Signed-off-by: Kito Cheng
Signed-off-by: Chih-Min Chao
Signed-off-by: Frank Chang
---
target/riscv/fpu_helper.c | 21 +
target/riscv/helper.h | 3 ++
target/riscv/insn32.deco
From: Vladimir Sementsov-Ogievskiy
Rename size and make it int64_t to correspond to modern block layer,
which always uses int64_t for offset and bytes (not in blk layer yet,
which is a task for following commits).
All callers pass int or unsigned int.
So, for bytes in [0, INT_MAX] nothing is ch
The following changes since commit 253e399bab7c83b3411f8eac01840283a9304cb3:
Merge remote-tracking branch 'remotes/kwolf/tags/for-upstream' into staging
(2021-10-15 12:08:54 -0700)
are available in the Git repository at:
https://repo.or.cz/qemu/ericb.git tags/pull-nbd-2021-10-15
for you to
From: Vladimir Sementsov-Ogievskiy
We updated blk_do_pdiscard() and its wrapper blk_co_pdiscard(). Both
functions are updated so that the parameter type becomes wider, so all
callers should be OK with it.
Look at blk_do_pdiscard(): bytes is passed only to
blk_check_byte_request() and bdrv_co_pdi
From: Vladimir Sementsov-Ogievskiy
For both updated functions, the type of bytes becomes wider, so all callers
should be OK with it.
blk_co_preadv() only passes its arguments to blk_do_preadv().
blk_do_preadv() passes bytes to:
- trace_blk_co_preadv, which is updated too
- blk_check_byte_req
From: Vladimir Sementsov-Ogievskiy
To be consistent with declarations in include/sysemu/block-backend.h.
Signed-off-by: Vladimir Sementsov-Ogievskiy
Message-Id: <20211006131718.214235-12-vsement...@virtuozzo.com>
Reviewed-by: Eric Blake
Signed-off-by: Eric Blake
---
block/block-backend.c | 1
From: Vladimir Sementsov-Ogievskiy
Function is updated so that parameter type becomes wider, so all
callers should be OK with it.
Look at blk_co_copy_range() itself: bytes is passed only to
blk_check_byte_request() and bdrv_co_copy_range(), which already have
int64_t bytes parameter, so we are O
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