The base debian10 image contains enough to build qemu;
we do not need to repeat that within the new image.
Signed-off-by: Richard Henderson
---
tests/docker/dockerfiles/debian-all-test-cross.docker | 5 -
1 file changed, 5 deletions(-)
diff --git a/tests/docker/dockerfiles/debian-all-test-c
Build the entire cross tool chain from source.
For this reason, default to caching.
Signed-off-by: Richard Henderson
---
tests/docker/Makefile.include | 24 +
.../debian-nios2-cross.d/build-toolchain.sh | 87 +++
.../dockerfiles/debian-toolchain.docker
Since gen_mipsdsp_accinsn() got added in commit b53371ed5d4
("target-mips: Add ASE DSP accumulator instructions"), the
'v2_t' TCG temporary has never been used. Remove it.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/tcg/translate.c | 4
1 file changed, 4 deletions(-)
diff --git a
Quoting Philippe Mathieu-Daudé (2021-05-26 02:30:19)
> On 5/25/21 10:12 PM, Helge Deller wrote:
> > The CDE desktop on HP-UX 10 shows wrongly rendered pixels when the local
> > screen
> > menu is closed. This bug was introduced by commit c7050f3f167b
> > ("hw/display/artist: Refactor x/y coordinat
Quoting Jessica Clarke (2021-08-05 14:25:45)
> This partially reverts commit bbd2d5a8120771ec59b86a80a1f51884e0a26e53.
>
> This commit was misguided and broke using --disable-pie on any distro
> that enables PIE by default in their compiler driver, including Debian
> and its derivatives. Whilst -n
On 10/14/21 3:32 PM, matheus.fe...@eldorado.org.br wrote:
From: Matheus Ferst
We should use cpu_read_xer/cpu_write_xer to save/restore the complete
register since some of its bits are in other fields of CPUPPCState. A
test is added to prevent future regressions.
Fixes: da91a00f191f ("target-pp
On 10/14/21 3:32 PM, matheus.fe...@eldorado.org.br wrote:
From: Matheus Ferst
The value of XER is split in multiple fields of CPUPPCState, like
env->xer and env->so. To get/set the whole register from gdb, we should
use cpu_read_xer/cpu_write_xer.
Fixes: da91a00f191f ("target-ppc: Split out SO,
On 10/14/21 3:32 PM, matheus.fe...@eldorado.org.br wrote:
From: Matheus Ferst
env->xer doesn't hold some bits of XER, like OV and CA. To write the
complete register in the core dump we should read XER value with
cpu_read_xer.
Reported-by: Lucas Mateus Castro (alqotel)
Fixes: da91a00f191f ("targ
On Thu, Oct 14, 2021 at 05:15:48PM +0800, Lin Ma wrote:
> Since kernel v5.11, Unprivileged user (without SYS_CAP_PTRACE capability)
> must pass UFFD_USER_MODE_ONLY to userfaultd in case unprivileged_userfaultfd
> sysctl knob is 0.
> Please refer to https://lwn.net/Articles/819834/ and the kernel co
On 10/14/21 3:32 PM, matheus.fe...@eldorado.org.br wrote:
From: Matheus Ferst
We can't read env->xer directly, as it does not contain some bits of
XER. Instead, we should have a callback that uses cpu_read_xer to read
the complete register.
Fixes: da91a00f191f ("target-ppc: Split out SO, OV, CA
ping?
On Sun, Apr 18, 2021 at 7:57 AM Philippe Mathieu-Daudé wrote:
>
> Since commit 2cdfcf272d ("memory: assign MemoryRegionOps to all
> regions"), all newly created regions are assigned with
> unassigned_mem_ops (which might be then overwritten).
>
> When using aliased container regions, and th
On 10/14/21 4:30 PM, Michael Roth wrote:
Quoting Jessica Clarke (2021-08-05 14:25:45)
This partially reverts commit bbd2d5a8120771ec59b86a80a1f51884e0a26e53.
This commit was misguided and broke using --disable-pie on any distro
that enables PIE by default in their compiler driver, including Deb
On 10/14/21 3:45 PM, Philippe Mathieu-Daudé wrote:
Since gen_mipsdsp_accinsn() got added in commit b53371ed5d4
("target-mips: Add ASE DSP accumulator instructions"), the
'v2_t' TCG temporary has never been used. Remove it.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/tcg/translate.c |
On 15 Oct 2021, at 01:12, Richard Henderson
wrote:
>
> On 10/14/21 4:30 PM, Michael Roth wrote:
>> Quoting Jessica Clarke (2021-08-05 14:25:45)
>>> This partially reverts commit bbd2d5a8120771ec59b86a80a1f51884e0a26e53.
>>>
>>> This commit was misguided and broke using --disable-pie on any dist
On 10/14/21 5:22 PM, Jessica Clarke wrote:
On 15 Oct 2021, at 01:12, Richard Henderson
wrote:
On 10/14/21 4:30 PM, Michael Roth wrote:
Quoting Jessica Clarke (2021-08-05 14:25:45)
This partially reverts commit bbd2d5a8120771ec59b86a80a1f51884e0a26e53.
This commit was misguided and broke us
On 10/14/21 5:05 AM, Michael S. Tsirkin wrote:
On Thu, Oct 14, 2021 at 01:56:40PM +0200, Eric Auger wrote:
This series upgrades the ACPI IORT table up to the E.b
specification revision. One of the goal of this upgrade
is to allow the addition of RMR nodes along with the SMMUv3.
The latest IORT
On 10/14/21 4:56 AM, Eric Auger wrote:
This series upgrades the ACPI IORT table up to the E.b
specification revision. One of the goal of this upgrade
is to allow the addition of RMR nodes along with the SMMUv3.
The latest IORT specification (ARM DEN 0049E.b) can be found at
IO Remapping Table -
On 10/14/21 12:43 PM, Luc Michel wrote:
Until now, int was used as the return type for all the ELF
loader related functions. The returned value is the sum of all loaded
program headers "MemSize" fields.
Because of the overflow check in elf_ops.h, trying to load an ELF bigger
than INT_MAX will fa
The vt82c686b_realize and vt8231_realize methods are almost identical,
factor out the common parts to a via_isa_realize function to avoid
code duplication.
Signed-off-by: BALATON Zoltan
---
hw/isa/vt82c686.c | 67 ---
1 file changed, 29 insertions(+),
Based-on:
This is on top of (v4-hw/usb/vt82c686-uhci-pci: Use ISA instead of
PCI) series and removes usage of isa_get_irq() from the usb and ide
functions. I managed to simplify it so it's not so bad but not sure if
it's much better either but maybe groups things a bit better this way.
Regards,
Use via_isa_set_irq() which better encapsulates irq handling in the
vt82xx model and avoids using isa_get_irq() that has a comment saying
it should not be used.
Signed-off-by: BALATON Zoltan
---
hw/ide/via.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/ide/via.c b/h
Other functions in the VT82xx chips need to raise ISA interrupts. Keep
a reference to them in the device state and add via_isa_set_irq() to
allow setting their state.
Signed-off-by: BALATON Zoltan
---
hw/isa/vt82c686.c | 10 +-
include/hw/isa/vt82c686.h | 4
2 files changed
Use via_isa_set_irq() which better encapsulates irq handling in the
vt82xx model and avoids using isa_get_irq() that has a comment saying
it should not be used.
Signed-off-by: BALATON Zoltan
---
hw/usb/vt82c686-uhci-pci.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/hw/u
On Wed, Jun 30, 2021 at 12:01:17AM +0800, huang...@chinatelecom.cn wrote:
> From: Hyman Huang(黄勇)
>
> v12
> - adjust the order of calculating dirty rate
> let memory_global_dirty_log_sync before calculating as
> v11 version description.
Ping for Yong.
Dave/Juan, any plan to review/merge thi
On Wed, Sep 22, 2021 at 12:20:06PM -0400, Peter Xu wrote:
> v3:
> - Patch 3: in qmp_dump_guest_memory(), keeps the RUN_STATE_INMIGRATE check
> [Marc-Andre]
Ping - More comments?
If to go, should this go via dump or migration? I think it belongs more to
migration more (and I got Marc-Andre's ac
On Wed, Aug 04, 2021 at 09:23:26AM -0400, Peter Xu wrote:
> I didn't squash patch 1 because they fix different things at different places
> (patch 1 removes the "meson" dir warning on master branch already for gtags).
> Patch 2 is the same as posted previous on the list.
>
> Please have a look, th
Excerpts from Cédric Le Goater's message of October 14, 2021 7:40 am:
> From: Nicholas Piggin
>
> This implements a machine check injection framework and defines a
> 'mce' monitor command for ppc.
>
> Signed-off-by: Nicholas Piggin
> [ clg: - moved definition under "hw/ppc/mce.h"
>- ren
在 2021/10/15 9:32, Peter Xu 写道:
On Wed, Jun 30, 2021 at 12:01:17AM +0800, huang...@chinatelecom.cn wrote:
From: Hyman Huang(黄勇)
v12
- adjust the order of calculating dirty rate
let memory_global_dirty_log_sync before calculating as
v11 version description.
Ping for Yong. >
Dave/Juan
On Thu, Oct 14, 2021 at 07:32:31PM -0300, matheus.fe...@eldorado.org.br wrote:
> From: Matheus Ferst
>
> We should use cpu_read_xer/cpu_write_xer to save/restore the complete
> register since some of its bits are in other fields of CPUPPCState. A
> test is added to prevent future regressions.
>
On Thu, Oct 14, 2021 at 07:32:32PM -0300, matheus.fe...@eldorado.org.br wrote:
> From: Matheus Ferst
>
> The value of XER is split in multiple fields of CPUPPCState, like
> env->xer and env->so. To get/set the whole register from gdb, we should
> use cpu_read_xer/cpu_write_xer.
>
> Fixes: da91a0
在 2021/10/14 下午8:00, Eugenio Perez Martin 写道:
On Wed, Oct 13, 2021 at 5:27 AM Jason Wang wrote:
在 2021/10/1 下午3:05, Eugenio Pérez 写道:
Shadow virtqueue notifications forwarding is disabled when vhost_dev
stops, so code flow follows usual cleanup.
Also, host notifiers must be disabled at SVQ
For v5, I've combined the sigsegv and sigbus patch sets, because
they're so very closely modelled. We've got user-only hooks named
record_sigsegv
record_sigbus
While the tlb_fill hook becomes sysemu only, the corresponding
do_unaligned_access hook was always sysemu only and stays that way.
The existing code for safe-syscall.inc.S will compile
without change for riscv32 and riscv64. We may also
drop the meson.build stanza that merges them for tcg/.
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
Signed-off-by: Richard Henderson
---
configure
Split out a function to adjust the raw signal pc into a
value that could be passed to cpu_restore_state.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
v2: Adjust pc in place; return MMUAccessType.
---
include/exec/exec-all.h | 10 ++
accel/tcg/user-exec.c |
Remove the comment about siglongjmp. We do use sigsetjmp
in the main cpu loop, but we do not save the signal mask
as most exits from the cpu loop do not require them.
Signed-off-by: Richard Henderson
---
accel/tcg/user-exec.c | 14 ++
1 file changed, 2 insertions(+), 12 deletions(-)
This is the major portion of handle_cpu_signal which is specific
to tcg, handling the page protections for the translations.
Most of the rest will migrate to linux-user/ shortly.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
v2: Pass guest address to handle_sigsegv_acc
Split host_signal_pc and host_signal_write out of user-exec.c.
Drop the *BSD code, to be re-created under bsd-user/ later.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
linux-user/host/arm/host-signal.h | 30 -
accel/tcg/user-exec.c | 4
Split host_signal_pc and host_signal_write out of user-exec.c.
Drop the *BSD code, to be re-created under bsd-user/ later.
Drop the Solaris code as completely unused.
Signed-off-by: Richard Henderson
---
linux-user/host/sparc/host-signal.h | 54 ++-
linux-user/host/sparc64/
Currently there are only two places that require we reset this
value before exiting to the main loop, but that will change.
Reviewed-by: Warner Losh
Signed-off-by: Richard Henderson
---
accel/tcg/cpu-exec.c | 3 ++-
accel/tcg/user-exec.c | 2 --
2 files changed, 2 insertions(+), 3 deletions(-)
Split host_signal_pc and host_signal_write out of user-exec.c.
Drop the *BSD code, to be re-created under bsd-user/ later.
Reviewed-by: Warner Losh
Signed-off-by: Richard Henderson
---
linux-user/host/ppc/host-signal.h | 25 -
linux-user/host/ppc64/host-signal.h | 2 +-
accel/tcg/use
Split host_signal_pc and host_signal_write out of user-exec.c.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
linux-user/host/mips/host-signal.h | 62 +-
accel/tcg/user-exec.c | 52 +
2 files changed, 62
Split host_signal_pc and host_signal_write out of user-exec.c.
Drop the *BSD code, to be re-created under bsd-user/ later.
Signed-off-by: Richard Henderson
---
linux-user/host/i386/host-signal.h | 25 -
linux-user/host/x32/host-signal.h| 2 +-
linux-user/host/x86_64/host-signal.h |
Add stub host-signal.h for all linux-user hosts.
Add new code replacing cpu_signal_handler.
Full migration will happen one host at a time.
Reviewed-by: Warner Losh
Reviewed-by: Philippe Mathieu-Daudé
Acked-by: Alistair Francis
Signed-off-by: Richard Henderson
---
linux-user/host/aarch64/host-
Add a new user-only interface for updating cpu state before
raising a signal. This will replace tlb_fill for user-only
and should result in less boilerplate for each guest.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
include/hw/core/tcg-cpu-ops.h | 26 +
Now that all of the linux-user hosts have been converted
to host-signal.h, drop the compatibility code.
Reviewed by: Warner Losh
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
include/exec/exec-all.h | 12
linux-user/signal.c | 14 --
2 fi
Split host_signal_pc and host_signal_write out of user-exec.c.
Drop the *BSD code, to be re-created under bsd-user/ later.
Signed-off-by: Richard Henderson
---
linux-user/host/aarch64/host-signal.h | 74 -
accel/tcg/user-exec.c | 94 +--
Split host_signal_pc and host_signal_write out of user-exec.c.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
linux-user/host/alpha/host-signal.h | 41 +
accel/tcg/user-exec.c | 31 +-
2 files changed, 42 in
Because of the complexity of setting ESR, continue to use
arm_deliver_fault. This means we cannot remove the code
within cpu_loop that decodes EXCP_DATA_ABORT and
EXCP_PREFETCH_ABORT.
But using the new hook means that we don't have to do the
page_get_flags check manually, and we'll be able to res
This is a new interface to be provided by the os emulator for
raising SIGSEGV on fault. Use the new record_sigsegv target hook.
Reviewed by: Warner Losh
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
include/exec/exec-all.h | 15 +++
accel/tcg/user-exec.c
Split host_signal_pc and host_signal_write out of user-exec.c.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
linux-user/host/s390/host-signal.h | 93 -
linux-user/host/s390x/host-signal.h | 2 +-
accel/tcg/user-exec.c | 88 +
The named function no longer exists.
Refer to host_signal_handler instead.
Signed-off-by: Richard Henderson
---
target/arm/sve_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
index dab5f1d1cd..07be55b7e1 100644
--- a/
Because the linux-user kuser page handling is currently implemented
by detecting magic addresses in the unnamed 0xaa trap, we cannot
simply remove nios2_cpu_tlb_fill and rely on the fallback code.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/nios2/cpu.h| 6
Split host_signal_pc and host_signal_write out of user-exec.c.
Reviewed-by: Alistair Francis
Signed-off-by: Richard Henderson
---
linux-user/host/riscv/host-signal.h | 85 +-
accel/tcg/user-exec.c | 134
2 files changed, 84 insertions(
The fallback code in cpu_loop_exit_sigsegv is sufficient
for m68k linux-user.
Remove the code from cpu_loop that handled EXCP_ACCESS.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
linux-user/m68k/cpu_loop.c | 10 --
target/m68k/cpu.c | 2 +-
target/
Do not read 4 bytes before we determine the size of the insn.
Simplify triple switches in favor of checking major opcodes.
Include the missing cases of compact fsd and fsdsp.
Reviewed-by: Alistair Francis
Signed-off-by: Richard Henderson
---
linux-user/host/riscv/host-signal.h | 83 ++--
The fallback code in cpu_loop_exit_sigsegv is sufficient
for riscv linux-user.
Remove the code from cpu_loop that raised SIGSEGV.
Reviewed-by: Alistair Francis
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
linux-user/riscv/cpu_loop.c | 7 ---
target/riscv/cpu.c
The fallback code in cpu_loop_exit_sigsegv is sufficient
for mips linux-user.
This means we can remove tcg/user/tlb_helper.c entirely.
Remove the code from cpu_loop that raised SIGSEGV.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/mips/tcg/tcg-internal.h|
Record trap_arg{0,1,2} for the linux-user signal frame.
Fill in the stores to trap_arg{1,2} that were missing
from the previous user-only alpha_cpu_tlb_fill function.
Use maperr to simplify computation of trap_arg1.
Remove the code for EXCP_MMFAULT from cpu_loop, as
that part is now handled by cp
Use the new os interface for raising the exception,
rather than calling arm_cpu_tlb_fill directly.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/arm/mte_helper.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/target/arm/mte_helper.c b
The fallback code in cpu_loop_exit_sigsegv is sufficient
for hexagon linux-user.
Remove the code from cpu_loop that raises SIGSEGV.
Reviewed-by: Taylor Simpson
Signed-off-by: Richard Henderson
---
linux-user/hexagon/cpu_loop.c | 24 +---
target/hexagon/cpu.c | 23 -
Move the masking of the address from cpu_loop into
s390_cpu_record_sigsegv -- this is governed by hw, not linux.
This does mean we have to raise our own exception, rather
than return to the fallback.
Use maperr to choose between PGM_PROTECTION and PGM_ADDRESSING.
Use the appropriate si_code for ea
The fallback code in cpu_loop_exit_sigsegv is sufficient
for sparc linux-user.
This makes all of the code in mmu_helper.c sysemu only, so remove
the ifdefs and move the file to sparc_softmmu_ss. Remove the code
from cpu_loop that handled TT_DFAULT and TT_TFAULT.
Cc: Mark Cave-Ayland
Reviewed-by
The fallback code in cpu_loop_exit_sigsegv is sufficient
for cris linux-user.
Remove the code from cpu_loop that handled the unnamed 0xaa exception.
This makes all of the code in helper.c sysemu only, so remove the
ifdefs and move the file to cris_softmmu_ss.
Reviewed-by: Philippe Mathieu-Daudé
Record cr2, error_code, and exception_index. That last means
that we must exit to cpu_loop ourselves, instead of letting
exception_index being overwritten.
Use the maperr parameter to properly set PG_ERROR_P_MASK.
Reviewed by: Warner Losh
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Rich
The fallback code in cpu_loop_exit_sigsegv is sufficient
for hppa linux-user.
Remove the code from cpu_loop that raised SIGSEGV.
This makes all of the code in mem_helper.c sysemu only,
so remove the ifdefs and move the file to hppa_softmmu_ss.
Signed-off-by: Richard Henderson
---
target/hppa/cp
The fallback code in cpu_loop_exit_sigsegv is sufficient
for xtensa linux-user.
Remove the code from cpu_loop that raised SIGSEGV.
Acked-by: Max Filippov
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/xtensa/cpu.h | 2 +-
linux-user/xtensa/cpu_loop.c
The fallback code in cpu_loop_exit_sigsegv is sufficient
for sh4 linux-user.
Remove the code from cpu_loop that raised SIGSEGV.
Signed-off-by: Richard Henderson
---
target/sh4/cpu.h | 6 +++---
linux-user/sh4/cpu_loop.c | 8
target/sh4/cpu.c | 2 +-
target/sh4/helper.
The fallback code in cpu_loop_exit_sigsegv is sufficient
for microblaze linux-user.
Remove the code from cpu_loop that handled the unnamed 0xaa exception.
Signed-off-by: Richard Henderson
---
target/microblaze/cpu.h | 8
linux-user/microblaze/cpu_loop.c | 10 --
targe
We have replaced tlb_fill with record_sigsegv for user mode.
Move the declaration to restrict it to system emulation.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
include/hw/core/tcg-cpu-ops.h | 22 ++
linux-user/signal.c | 3 ---
2 fil
This reverts commit 1b36e4f5a5de585210ea95f2257839c2312be28f.
Despite a comment saying why cpu_common_props cannot be placed in
a file that is compiled once, it was moved anyway. Revert that.
Since then, Property is not defined in hw/core/cpu.h, so it is now
easier to declare a function to insta
The kernel vectors both of these through unhandled_exception, which
results in force_sig(SIGSEGV). This isn't very useful for userland
when enabling overflow traps or fpu traps, but c'est la vie.
Reviewed-by: Stafford Horne
Signed-off-by: Richard Henderson
---
linux-user/openrisc/cpu_loop.c |
Record trap_arg{0,1,2} for the linux-user signal frame.
Raise SIGBUS directly from cpu_loop_exit_sigbus, which means
we can remove the code for EXCP_UNALIGN in cpu_loop.
Signed-off-by: Richard Henderson
---
target/alpha/cpu.h | 8 +---
linux-user/alpha/cpu_loop.c | 7 ---
tar
By doing this while sending the exception, we will have already
done the unwinding, which makes the ppc_cpu_do_unaligned_access
code a bit cleaner.
Update the comment about the expected instruction format.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/ppc/excp_helper.c
This is a new interface to be provided by the os emulator for
raising SIGBUS on fault. Use the new record_sigbus target hook.
Signed-off-by: Richard Henderson
---
include/exec/exec-all.h | 14 ++
linux-user/signal.c | 14 ++
2 files changed, 28 insertions(+)
diff --
Record DAR, DSISR, and exception_index. That last means
that we must exit to cpu_loop ourselves, instead of letting
exception_index being overwritten.
This is exactly what the user-mode ppc_cpu_tlb_fill does,
so simply rename it as ppc_cpu_record_sigsegv.
Reviewed-by: Philippe Mathieu-Daudé
Sig
Because of the complexity of setting ESR, re-use the existing
arm_cpu_do_unaligned_access function. This means we have to
handle the exception ourselves in cpu_loop, transforming it
to the appropriate signal.
Signed-off-by: Richard Henderson
---
target/arm/internals.h| 2 ++
linux-user
We ought to have been recording the virtual address for reporting
to the guest trap handler.
Cc: qemu-...@nongnu.org
Reviewed-by: Warner Losh
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/ppc/excp_helper.c | 14 ++
1 file changed, 14 insertions(+)
diff --g
Not sure why the user-only code wasn't rewritten to use
probe_access_flags at the same time that the sysemu code
was converted. For the purpose of user-only, this is an
exact replacement.
Signed-off-by: Richard Henderson
---
target/s390x/tcg/mem_helper.c | 18 +-
1 file changed,
This is not used by, nor required by, user-only.
Signed-off-by: Richard Henderson
---
target/ppc/internal.h| 8 +++-
target/ppc/excp_helper.c | 8 +++-
2 files changed, 6 insertions(+), 10 deletions(-)
diff --git a/target/ppc/internal.h b/target/ppc/internal.h
index 339974b7d8..6aa9
We will raise SIGBUS directly from cpu_loop_exit_sigbus.
Signed-off-by: Richard Henderson
---
linux-user/ppc/cpu_loop.c | 8
1 file changed, 8 deletions(-)
diff --git a/linux-user/ppc/cpu_loop.c b/linux-user/ppc/cpu_loop.c
index 840b23736b..483e669300 100644
--- a/linux-user/ppc/cpu_lo
We ought to have been recording the virtual address for reporting
to the guest trap handler. Move the function to mmu_helper.c, so
that we can re-use code shared with get_physical_address_data.
Reviewed-by: Mark Cave-Ayland
Signed-off-by: Richard Henderson
---
target/sparc/ldst_helper.c | 13 -
We ought to have been recording the virtual address for reporting
to the guest trap handler.
Cc: Yoshinori Sato
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/sh4/op_helper.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/target/sh4/op_helper.c b/targ
The fallback code in cpu_loop_exit_sigsegv is sufficient for
openrisc linux-user.
This makes all of the code in mmu.c sysemu only, so remove
the ifdefs and move the file to openrisc_softmmu_ss.
Remove the code from cpu_loop that handled EXCP_DPF.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by
The printf should have been qemu_log_mask, the parameters
themselves no longer compile, and because this is placed
before unwinding the PC is actively wrong.
We get better (and correct) logging on the other side of
raising the exception, in sparc_cpu_do_interrupt.
Reviewed-by: Mark Cave-Ayland
R
To be called from tcg generated code on hosts that support
unaligned accesses natively, in response to an access that
is supposed to be aligned.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
include/tcg/tcg-ldst.h | 5 +
accel/tcg/user-exec.c | 11 +++
2 files ch
Use the new cpu_loop_exit_sigbus for cpu_mmu_lookup.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
accel/tcg/user-exec.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
index 92cbffd7c6..7d50dd54f6 100644
Add a new user-only interface for updating cpu state before
raising a signal. This will take the place of do_unaligned_access
for user-only and should result in less boilerplate for each guest.
Signed-off-by: Richard Henderson
---
include/hw/core/tcg-cpu-ops.h | 23 +++
1 fi
Leave TARGET_ALIGNED_ONLY set, but use the new CPUState
flag to set MO_UNALN for the instructions that the kernel
handles in the unaligned trap.
The Linux kernel does not handle all memory operations: no
floating-point and no MAC.
Signed-off-by: Richard Henderson
---
linux-user/sh4/target_prctl
We will raise SIGBUS directly from cpu_loop_exit_sigbus.
Signed-off-by: Richard Henderson
---
linux-user/hppa/cpu_loop.c | 7 ---
1 file changed, 7 deletions(-)
diff --git a/linux-user/hppa/cpu_loop.c b/linux-user/hppa/cpu_loop.c
index e0a62deeb9..375576c8f0 100644
--- a/linux-user/hppa/cpu
Use the new cpu_loop_exit_sigbus for atomic_mmu_lookup, which
has access to complete alignment info from the TCGMemOpIdx arg.
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
accel/tcg/user-exec.c | 13 -
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/acc
This requires extra work for each target, but adds the
common syscall code, and the necessary flag in CPUState.
Signed-off-by: Richard Henderson
---
include/hw/core/cpu.h | 3 +++
linux-user/generic/target_prctl_unalign.h | 27 +++
cpu.c
Handle BUS_ADRALN via cpu_loop_exit_sigbus, but allow other SIGBUS
si_codes to continue into the host-to-guest signal coversion code.
Signed-off-by: Richard Henderson
---
linux-user/signal.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/linux-user/signal.c b/linux-user/signal.c
index df
The kernel will fix up unaligned accesses, so emulate that
by allowing unaligned accesses to succeed.
Reviewed-by: Edgar E. Iglesias
Signed-off-by: Richard Henderson
---
target/microblaze/translate.c | 16
1 file changed, 16 insertions(+)
diff --git a/target/microblaze/transla
Leave TARGET_ALIGNED_ONLY set, but use the new CPUState
flag to set MO_UNALN for the instructions that the kernel
handles in the unaligned trap.
Signed-off-by: Richard Henderson
---
linux-user/hppa/target_prctl.h | 2 +-
target/hppa/cpu.h | 5 -
target/hppa/translate.c
For s390x, the only unaligned accesses that are signaled are atomic,
and we don't actually want to raise SIGBUS for those, but instead
raise a SPECIFICATION error, which the kernel will report as SIGILL.
Split out a do_unaligned_access function to share between the user-only
s390x_cpu_record_sigbu
Create a list of subcodes that we want to pass on, a list of
subcodes that should not be passed on because they would affect
the running qemu itself, and a list that probably could be
implemented but require extra work. Do not pass on unknown subcodes.
Signed-off-by: Richard Henderson
---
linux-
Leave TARGET_ALIGNED_ONLY set, but use the new CPUState
flag to set MO_UNALN for the instructions that the kernel
handles in the unaligned trap.
Signed-off-by: Richard Henderson
---
linux-user/alpha/target_prctl.h | 2 +-
target/alpha/cpu.h | 5 +
target/alpha/translate.c
在 2021/10/15 上午12:39, Eugenio Perez Martin 写道:
On Wed, Oct 13, 2021 at 5:47 AM Jason Wang wrote:
在 2021/10/1 下午3:05, Eugenio Pérez 写道:
This will make qemu aware of the device used buffers, allowing it to
write the guest memory with its contents if needed.
Since the use of vhost_virtqueue_s
Reviewed-by: Mark Cave-Ayland
Signed-off-by: Richard Henderson
---
target/sparc/mmu_helper.c | 72 +--
1 file changed, 46 insertions(+), 26 deletions(-)
diff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c
index 2ad47391d0..014601e701 100644
---
Since the prctl constants are supposed to be generic, supply
any that are not provided by the host.
Split out subroutines for PR_GET_FP_MODE, PR_SET_FP_MODE,
PR_GET_VL, PR_SET_VL, PR_RESET_KEYS, PR_SET_TAGGED_ADDR_CTRL,
PR_GET_TAGGED_ADDR_CTRL. Return EINVAL for guests that do
not support these o
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