On Sat, Oct 2, 2021 at 5:42 PM BALATON Zoltan wrote:
> On Sat, 2 Oct 2021, Howard Spoelstra wrote:
> > Both have issues communicating with endpoint 4 (the hid controls volume
> > up/down and mute).
> > Endpoint 1 should receive the isochronous audio stream, but never does.
> >
> > After some expe
From: Yanan Wang
To pave the way for the functional improvement in later patches,
make some refactor/cleanup for the smp parsers, including using
local maxcpus instead of ms->smp.max_cpus in the calculation,
defaulting dies to 0 initially like other members, cleanup the
sanity check for dies.
We
From: Yanan Wang
The explanation of @cores should be "number of cores per die" but
not "number of cores per thread". Let's fix it.
Fixes: 1e63fe685804 ("machine: pass QAPI struct to mc->smp_parse")
Signed-off-by: Yanan Wang
Reviewed-by: Daniel P. Berrangé
Message-Id: <20210929025816.21076-2-wa
From: Yanan Wang
We are currently using maxcpus to calculate the omitted sockets
but using cpus to calculate the omitted cores/threads. This makes
cmdlines like:
-smp cpus=8,maxcpus=16
-smp cpus=8,cores=4,maxcpus=16
-smp cpus=8,threads=2,maxcpus=16
work fine but the ones like:
-smp cpus=8
The following changes since commit bb4aa8f59e18412cff0d69f14aee7abba153161a:
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20210930'
into staging (2021-09-30 21:16:54 +0100)
are available in the Git repository at:
https://gitlab.com/bonzini/qemu.git tags/for-upstream
From: Yanan Wang
Currently we directly calculate the omitted cpus based on the given
incomplete collection of parameters. This makes some cmdlines like:
-smp maxcpus=16
-smp sockets=2,maxcpus=16
-smp sockets=2,dies=2,maxcpus=16
-smp sockets=2,cores=4,maxcpus=16
not work. We should probabl
From: Yanan Wang
In the SMP configuration, we should either provide a topology
parameter with a reasonable value (greater than zero) or just
omit it and QEMU will compute the missing value.
The users shouldn't provide a configuration with any parameter
of it specified as zero (e.g. -smp 8,socket
From: Yanan Wang
We have two requirements for a valid SMP configuration:
the product of "sockets * cores * threads" must represent all the
possible cpus, i.e., max_cpus, and then must include the initially
present cpus, i.e., smp_cpus.
So we only need to ensure 1) "sockets * cores * threads == m
From: Yanan Wang
Since commit 80d7835749 (qemu-options: rewrite help for -smp options),
the preference of sockets/cores in -smp parsing is considered liable
to change, and actually we are going to change it in a coming commit.
So it'll be more stable to use detailed -smp CLIs in testing if we
hav
From: Yanan Wang
Now that all the possible topology parameters are integrated in struct
CpuTopology, tweak the order of topology members to be "cpus/sockets/
dies/cores/threads/maxcpus" for readability and consistency. We also
tweak the comment by adding explanation of dies parameter.
Signed-off
From: Yanan Wang
Now we have a generic smp parser for all arches, and there will
not be any other arch specific ones, so let's remove the callback
from MachineClass and call the parser directly.
Signed-off-by: Yanan Wang
Reviewed-by: Andrew Jones
Reviewed-by: Daniel P. Berrangé
Message-Id: <2
From: Yanan Wang
Since commit 80d7835749 (qemu-options: rewrite help for -smp options),
the preference of sockets/cores in -smp parsing is considered liable
to change, and actually we are going to change it in a coming commit.
So it'll be more stable to use detailed -smp CLIs in the testcases
tha
From: Yanan Wang
In the real SMP hardware topology world, it's much more likely that
we have high cores-per-socket counts and few sockets totally. While
the current preference of sockets over cores in smp parsing results
in a virtual cpu topology with low cores-per-sockets counts and a
large numb
From: Yanan Wang
Put both sanity-check of the input SMP configuration and sanity-check
of the output SMP configuration uniformly in the generic parser. Then
machine_set_smp() will become cleaner, also all the invalid scenarios
can be tested only by calling the parser.
Signed-off-by: Yanan Wang
Signed-off-by: Paolo Bonzini
---
hw/core/machine.c | 7 ++-
1 file changed, 2 insertions(+), 5 deletions(-)
diff --git a/hw/core/machine.c b/hw/core/machine.c
index 54f04a5ac6..d49ebc24e2 100644
--- a/hw/core/machine.c
+++ b/hw/core/machine.c
@@ -897,7 +897,7 @@ static void machine_set_smp(O
From: Yanan Wang
In the sanity-check of smp_cpus and max_cpus against mc in function
machine_set_smp(), we are now using ms->smp.max_cpus for the check
but using current_machine->smp.max_cpus in the error message.
Tweak this by uniformly using the local ms.
Signed-off-by: Yanan Wang
Reviewed-by
From: Yanan Wang
Currently the only difference between smp_parse and pc_smp_parse
is the support of dies parameter and the related error reporting.
With some arch compat variables like "bool dies_supported", we can
make smp_parse generic enough for all arches and the PC specific
one can be remove
From: David Hildenbrand
As we might not always have a device id, it is impossible to always
match MEMORY_DEVICE_SIZE_CHANGE events to an actual device. Let's
include the qom-path in the event, which allows for reliable mapping of
events to devices.
Fixes: 722a3c783ef4 ("virtio-pci: Send qapi eve
From: nia
As discussed in issue 614, we're shipping GCC 7.4.0 as the
system compiler in NetBSD 9, the most recent stable branch,
and are still actively interested in QEMU on this platform.
The differences between GCC 7.5.0 and 7.4.0 are trivial.
Signed-off-by: Nia Alarie
Reviewed-by: Richard H
From: Yanan Wang
Now we have a common structure SMPCompatProps used to store information
about SMP compatibility stuff, so we can also move smp_prefer_sockets
there for cleaner code.
No functional change intended.
Signed-off-by: Yanan Wang
Acked-by: David Gibson
Reviewed-by: Andrew Jones
Rev
From: Vitaly Kuznetsov
By default, KVM allows the guest to use all currently supported PV features
even when they were not announced in guest visible CPUIDs. Introduce a new
"kvm-pv-enforce-cpuid" flag to limit the supported feature set to the
exposed features. The feature is supported by Linux >
From: David Hildenbrand
virtio-mem logically plugs/unplugs memory within a sparse memory region
and notifies via the RamDiscardManager interface when parts become
plugged (populated) or unplugged (discarded).
Currently, we end up (via the two users)
1) zeroing all logically unplugged/discarded m
From: Vitaly Kuznetsov
In preparation to enabling Hyper-V + APICv/AVIC move
HV_APIC_ACCESS_RECOMMENDED setting out of kvm_hyperv_properties[]: the
'real' feature bit for the vAPIC features is HV_APIC_ACCESS_AVAILABLE,
HV_APIC_ACCESS_RECOMMENDED is a recommendation to use the feature which
we may
From: David Hildenbrand
We want to rate-limit MEMORY_DEVICE_SIZE_CHANGE events per device,
otherwise we can lose some events for devices. We can now use the
qom-path to reliably map an event to a device and make rate-limiting
device-aware.
This was noticed by starting a VM with two virtio-mem de
From: Vitaly Kuznetsov
By default, KVM allows the guest to use all currently supported Hyper-V
enlightenments when Hyper-V CPUID interface was exposed, regardless of if
some features were not announced in guest visible CPUIDs. hv-enforce-cpuid
feature alters this behavior and only allows the gues
From: Vitaly Kuznetsov
KVM implements some Hyper-V 2016 functions so providing WS2008R2 version
is somewhat incorrect. While generally guests shouldn't care about it
and always check feature bits, it is known that some tools in Windows
actually check version info.
For compatibility reasons make
From: David Hildenbrand
Let's factor out adding a MemoryRegionSection to the list, to be reused in
RamDiscardManager context next.
Reviewed-by: Stefan Berger
Reviewed-by: Peter Xu
Cc: Marc-André Lureau
Cc: Paolo Bonzini
Cc: "Michael S. Tsirkin"
Cc: Eduardo Habkost
Cc: Alex Williamson
Cc:
From: David Hildenbrand
We might not start at the beginning of the memory region. Let's
calculate the offset into the memory region via the difference in the
host addresses.
Acked-by: Stefan Berger
Fixes: ffab1be70692 ("tpm: clear RAM when "memory overwrite" requested")
Cc: Marc-André Lureau
C
From: Vitaly Kuznetsov
Currently, we hardcode Hyper-V version id (CPUID 0x4002) to
WS2008R2 and it is known that certain tools in Windows check this. It
seems useful to provide some flexibility by making it possible to change
this info at will. CPUID information is defined in TLFS as:
EAX: B
From: David Hildenbrand
Let's make sure to not merge when different memory regions are involved.
Unlikely, but theoretically possible.
Acked-by: Stefan Berger
Reviewed-by: Peter Xu
Cc: Marc-André Lureau
Cc: Paolo Bonzini
Cc: "Michael S. Tsirkin"
Cc: Eduardo Habkost
Cc: Alex Williamson
Cc:
From: Vitaly Kuznetsov
The enlightenment allows to use Hyper-V SynIC with hardware APICv/AVIC
enabled. Normally, Hyper-V SynIC disables these hardware features and
suggests the guest to use paravirtualized AutoEOI feature. Linux-4.15
gains support for conditional APICv/AVIC disablement, the featu
From: David Hildenbrand
Apparently, we don't have to duplicate the string.
Fixes: 722a3c783ef4 ("virtio-pci: Send qapi events when the virtio-mem size
changes")
Cc: qemu-sta...@nongnu.org
Signed-off-by: David Hildenbrand
Reviewed-by: Markus Armbruster
Message-Id: <20210929162445.64060-2-da...
On Sun, 3 Oct 2021, Howard Spoelstra wrote:
On Sat, Oct 2, 2021 at 5:42 PM BALATON Zoltan wrote:
I'm also not sure where's the problem (maybe we have multiple problems).
It also does not work with an emulated usb-audio device but that also
doesn't work with EHCI so it may have a problem by itse
mconfigptr is an mandatory CSR as per the priv spec.
This csr holds the physical address of the configuration
data structure if this data structure is implemented
Its an readonly csr set to zero making configuration
data structure not supported.
Signed-off-by: Rahul Pathak
---
target/riscv/cpu_b
On 10/2/21 7:30 PM, Philippe Mathieu-Daudé wrote:
Instead of using a temporary for $zero, keep a reference to the
constant pool.
Signed-off-by: Philippe Mathieu-Daudé
---
target/nios2/translate.c | 17 ++---
1 file changed, 2 insertions(+), 15 deletions(-)
Reviewed-by: Richard H
On 10/2/21 7:30 PM, Philippe Mathieu-Daudé wrote:
We already have a register holding the zero value in the constant
pool, use it instead of a temporary.
Signed-off-by: Philippe Mathieu-Daudé
---
target/nios2/translate.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
Reviewed-by: R
On 10/2/21 7:30 PM, Philippe Mathieu-Daudé wrote:
Replace uses of tcg_const_* with the allocate and free close together.
Signed-off-by: Philippe Mathieu-Daudé
---
target/nios2/translate.c | 14 --
1 file changed, 4 insertions(+), 10 deletions(-)
Reviewed-by: Richard Henderson
Hello Peter
( Please fix the From: p...@fbc.om :)
On 10/2/21 23:44, p...@fbc.om wrote:
From: Andrew Jeffery
This model implements enough behaviour to do basic functionality tests
such as device initialisation and read out of dummy sample values. The
sample value generation strategy is similar
On 10/2/21 8:25 PM, Philippe Mathieu-Daudé wrote:
MSA 2R/2RF instructions don't use any target vector register.
Remove the unused TCG temporaries.
Fixes: cbe50b9a8e7 ("target-mips: add MSA VEC/2R format instructions")
Fixes: 3bdeb68866e ("target-mips: add MSA 2RF format instructions")
Signed-off
On 10/2/21 23:44, p...@fbc.om wrote:
From: Peter Delevoryas
Following up from
https://lore.kernel.org/qemu-devel/20210930004235.1656003-1-p...@fb.com/
This is a resubmission of Andrew Jeffery's ADC model, but with the
registers converted from typed-member-fields to a regs[] array.
Otherwise,
On Sun, Oct 3, 2021 at 12:00 PM BALATON Zoltan wrote:
> On Sun, 3 Oct 2021, Howard Spoelstra wrote:
> > On Sat, Oct 2, 2021 at 5:42 PM BALATON Zoltan
> wrote:
> >> I'm also not sure where's the problem (maybe we have multiple problems).
> >> It also does not work with an emulated usb-audio devic
On 10/2/21 8:47 PM, Philippe Mathieu-Daudé wrote:
Replace uses of tcg_const_* with the allocate and free close together.
Inspired-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
target/hexagon/gen_tcg.h| 6 ++---
target/hexagon/macros.h | 3 +--
target/hexag
On 10/2/21 8:47 PM, Philippe Mathieu-Daudé wrote:
The gen_pred_cancel() function, introduced in commit a646e99cb90
(Hexagon macros) doesn't use the 'one' TCG temporary; remove it.
Signed-off-by: Philippe Mathieu-Daudé
---
target/hexagon/macros.h | 2 --
1 file changed, 2 deletions(-)
Review
Replace temporary TCG registers by tcg_constant_*() when possible.
Philippe Mathieu-Daudé (2):
target/ppc: Use tcg_constant_i32() in gen_setb()
target/ppc: Use tcg_constant_i64() in gen_brh()
target/ppc/translate.c | 16 +---
1 file changed, 5 insertions(+), 11 deletions(-)
--
The mask of the Byte-Reverse Halfword opcode is a read-only
constant. We can avoid using a TCG temporary by moving the
mask to the constant pool.
Signed-off-by: Philippe Mathieu-Daudé
---
target/ppc/translate.c | 8 +++-
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/target/pp
Avoid using TCG temporaries for the -1 and 8 constant values.
Signed-off-by: Philippe Mathieu-Daudé
---
target/ppc/translate.c | 8 ++--
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index b985e9e55bc..193d8e89152 100644
--- a/t
When running the scripts/coccinelle/tcg_gen_extract.cocci
Coccinelle semantic patch on target/avr/, we get:
[DBG] candidate at target/avr/translate.c:228
[DBG] candidate at target/avr/translate.c:266
[DBG] candidate at target/avr/translate.c:885
[DBG] candidate at target/avr/translate.c:92
When running the scripts/coccinelle/tcg_gen_extract.cocci
Coccinelle semantic patch on target/m68k/, we get:
[DBG] candidate at target/m68k/translate.c:3668
Manually inspect and replace combinations of (shri, andi)
and (movi, andi) opcodes by the extract opcode.
Signed-off-by: Philippe Mathi
When running the scripts/coccinelle/tcg_gen_extract.cocci
Coccinelle semantic patch on target/s390x/, we get:
[DBG] candidate at target/s390x/tcg/translate.c:1560
Manually inspect and replace combinations of (shri, andi)
opcodes by the extract opcode.
Signed-off-by: Philippe Mathieu-Daudé
-
Avoid using a TCG temporary for a read-only constant.
Signed-off-by: Philippe Mathieu-Daudé
---
target/arm/translate.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index f7086c66a59..b41e0f50dfe 100644
--- a/target/arm/tran
Introduce store_cpu_field_constant() helper to avoid using temporary
when the value is constant (and read-only).
Philippe Mathieu-Daudé (3):
target/arm: Use tcg_constant_i32() in op_smlad()
target/arm: Introduce store_cpu_field_constant() helper
target/arm: Use the constant variant of store_
Similarly to the store_cpu_field() helper which takes a TCG
temporary, store its value to the CPUState, introduce the
store_cpu_field_constant() helper which store a constant to
CPUState (without using any TCG temporary).
Signed-off-by: Philippe Mathieu-Daudé
---
target/arm/translate-a32.h | 11
When using a constant variable, we can replace the store_cpu_field()
call by store_cpu_field_constant() which avoid using TCG temporaries.
Signed-off-by: Philippe Mathieu-Daudé
---
target/arm/translate.c | 21 ++---
1 file changed, 6 insertions(+), 15 deletions(-)
diff --git a/t
On 10/3/21 09:42, Paolo Bonzini wrote:
> The following changes since commit bb4aa8f59e18412cff0d69f14aee7abba153161a:
>
> Merge remote-tracking branch
> 'remotes/pmaydell/tags/pull-target-arm-20210930' into staging (2021-09-30
> 21:16:54 +0100)
>
> are available in the Git repository at:
>
>
On 10/3/21 3:42 AM, Paolo Bonzini wrote:
The following changes since commit bb4aa8f59e18412cff0d69f14aee7abba153161a:
Merge remote-tracking branch
'remotes/pmaydell/tags/pull-target-arm-20210930' into staging (2021-09-30
21:16:54 +0100)
are available in the Git repository at:
https://g
On 10/3/21 10:17 AM, Philippe Mathieu-Daudé wrote:
Avoid using TCG temporaries for the -1 and 8 constant values.
Signed-off-by: Philippe Mathieu-Daudé
---
target/ppc/translate.c | 8 ++--
1 file changed, 2 insertions(+), 6 deletions(-)
Reviewed-by: Richard Henderson
r~
On 10/3/21 10:17 AM, Philippe Mathieu-Daudé wrote:
The mask of the Byte-Reverse Halfword opcode is a read-only
constant. We can avoid using a TCG temporary by moving the
mask to the constant pool.
Signed-off-by: Philippe Mathieu-Daudé
---
target/ppc/translate.c | 8 +++-
1 file changed, 3
On 10/3/21 10:21 AM, Philippe Mathieu-Daudé wrote:
When running the scripts/coccinelle/tcg_gen_extract.cocci
Coccinelle semantic patch on target/avr/, we get:
[DBG] candidate at target/avr/translate.c:228
[DBG] candidate at target/avr/translate.c:266
[DBG] candidate at target/avr/transl
On 10/3/21 10:24 AM, Philippe Mathieu-Daudé wrote:
When running the scripts/coccinelle/tcg_gen_extract.cocci
Coccinelle semantic patch on target/m68k/, we get:
[DBG] candidate at target/m68k/translate.c:3668
Manually inspect and replace combinations of (shri, andi)
and (movi, andi) opcodes
On 10/3/21 10:29 AM, Philippe Mathieu-Daudé wrote:
-tcg_gen_shri_i64(t, psw_mask, 16);
-tcg_gen_andi_i64(t, t, 0x0f00);
+tcg_gen_extract_i64(t, psw_mask, 40, 4);
No, the result should not be at bit 0, but bit 24.
r~
On 10/3/21 10:38 AM, Philippe Mathieu-Daudé wrote:
Avoid using a TCG temporary for a read-only constant.
Signed-off-by: Philippe Mathieu-Daudé
---
target/arm/translate.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
Reviewed-by: Richard Henderson
r~
On 10/3/21 10:39 AM, Philippe Mathieu-Daudé wrote:
-static inline void store_cpu_offset(TCGv_i32 var, int offset)
+static inline void store_cpu_offset(TCGv_i32 var, int offset, bool is_temp)
{
tcg_gen_st_i32(var, cpu_env, offset);
-tcg_temp_free_i32(var);
+if (is_temp) {
+
On 10/3/21 10:39 AM, Philippe Mathieu-Daudé wrote:
When using a constant variable, we can replace the store_cpu_field()
call by store_cpu_field_constant() which avoid using TCG temporaries.
Signed-off-by: Philippe Mathieu-Daudé
---
target/arm/translate.c | 21 ++---
1 file cha
On 10/3/21 17:31, Richard Henderson wrote:
> On 10/3/21 10:29 AM, Philippe Mathieu-Daudé wrote:
>> - tcg_gen_shri_i64(t, psw_mask, 16);
>> - tcg_gen_andi_i64(t, t, 0x0f00);
>> + tcg_gen_extract_i64(t, psw_mask, 40, 4);
>
> No, the result should not be at bit 0, but bit 24.
Good catch
On 10/3/21 17:35, Richard Henderson wrote:
> On 10/3/21 10:39 AM, Philippe Mathieu-Daudé wrote:
>> -static inline void store_cpu_offset(TCGv_i32 var, int offset)
>> +static inline void store_cpu_offset(TCGv_i32 var, int offset, bool
>> is_temp)
>> {
>> tcg_gen_st_i32(var, cpu_env, offset);
This device is part of a sperio/ISA bridge chip and IRQs from it are
routed to an ISA interrupt set by the Interrupt Line PCI config
register. Change uhci_update_irq() to allow this and use it from
vt82c686-uhci-pci.
Signed-off-by: BALATON Zoltan
---
Maybe bit of a hack but fixes USB interrupts o
在 2021/10/3 17:12, BALATON Zoltan 写道:
This device is part of a sperio/ISA bridge chip and IRQs from it are
routed to an ISA interrupt set by the Interrupt Line PCI config
register. Change uhci_update_irq() to allow this and use it from
vt82c686-uhci-pci.
Signed-off-by: BALATON Zoltan
Review
Just like we can control the enablement of the highmem PCIe region
using highmem_ecam, let's add a control for the highmem GICv3
redistributor region.
Similarily to highmem_ecam, these redistributors are disabled when
highmem is off.
Signed-off-by: Marc Zyngier
---
hw/arm/virt-acpi-build.c | 2
The highmem attribute is nothing but another way to express the
PA range of a VM. To support HW that has a smaller PA range then
what QEMU assumes, pass this PA range to the virt_set_memmap()
function, allowing it to correctly exclude highmem devices
if they are outside of the PA range.
Signed-off
Currently, the highmem PCIe region is oddly keyed on the highmem
attribute instead of highmem_ecam. Move the enablement of this PCIe
region over to highmem_ecam.
Signed-off-by: Marc Zyngier
---
hw/arm/virt-acpi-build.c | 10 --
hw/arm/virt.c| 4 ++--
2 files changed, 6 inser
Here's another stab at enabling QEMU on systems with pathologically
reduced IPA ranges such as the Apple M1 (original version at [1]).
Eventually, we're able to run a KVM guest with more than just 3GB of
RAM on a system with a 36bit IPA space, and at most 123 vCPUs.
This series does a few things:
Make sure both the highmem PCIe and GICv3 regions are disabled when
they don't fully fit in the PA range.
Signed-off-by: Marc Zyngier
---
hw/arm/virt.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index a572e0c9d9..756f67b6c8 100644
--- a/hw/arm/virt.c
+++
Even when the VM is configured with highmem=off, the highest_gpa
field includes devices that are above the 4GiB limit.
Similarily, nothing seem to check that the memory is within
the limit set by the highmem=off option.
This leads to failures in virt_kvm_type() on systems that have
a crippled IPA
> On Oct 3, 2021, at 6:56 AM, Cédric Le Goater wrote:
>
> On 10/2/21 23:44, p...@fbc.om wrote:
>> From: Peter Delevoryas
>> Following up from
>> https://lore.kernel.org/qemu-devel/20210930004235.1656003-1-p...@fb.com/
>> This is a resubmission of Andrew Jeffery's ADC model, but with the
>> regi
> On Oct 3, 2021, at 6:53 AM, Cédric Le Goater wrote:
>
> Hello Peter
>
> ( Please fix the From: p...@fbc.om :)
Oh dang it, yes I’ll fix that.
>
> On 10/2/21 23:44, p...@fbc.om wrote:
>> From: Andrew Jeffery
>> This model implements enough behaviour to do basic functionality tests
>> such
On 9/28/21 4:54 PM, Philipp Tomsich wrote:
dup_const always generates a uint64_t, which may exceed the size of a
target_long (generating warnings with recent-enough compilers).
To ensure that we can use dup_const both for 64bit and 32bit targets,
this adds dup_const_tl, which wraps dup_const and
On 9/28/21 4:54 PM, Philipp Tomsich wrote:
We need to use the newly introduced dup_const_tl in orc.b to legalise
the truncation (to target_long) of the constant generated with dup_const.
Signed-off-by: Philipp Tomsich
---
target/riscv/insn_trans/trans_rvb.c.inc | 2 +-
1 file changed, 1 inse
+static void aspeed_adc_instance_init(Object *obj)
+{
+AspeedADCState *s = ASPEED_ADC(obj);
+AspeedADCClass *aac = ASPEED_ADC_GET_CLASS(obj);
+uint32_t nr_channels = ASPEED_ADC_NR_CHANNELS / aac->nr_engines;
+
+for (int i = 0; i < aac->nr_engines; i++) {
+AspeedADCEngine
> On Oct 3, 2021, at 10:34 AM, Cédric Le Goater wrote:
>
+static void aspeed_adc_instance_init(Object *obj)
+{
+AspeedADCState *s = ASPEED_ADC(obj);
+AspeedADCClass *aac = ASPEED_ADC_GET_CLASS(obj);
+uint32_t nr_channels = ASPEED_ADC_NR_CHANNELS / aac-
On 10/2/21 20:45, Jiaxun Yang wrote:
> Generate FDT on our own if no dtb argument supplied.
> Avoid introducing unused device in FDT with user supplied dtb.
>
> Signed-off-by: Jiaxun Yang
> --
> v2: Address f4bug cmments (Thanks!)
> ---
> hw/mips/boston.c | 234 ++
Commits cbe50b9a8e7 ("target-mips: add MSA VEC/2R format instructions")
and 3bdeb68866e ("target-mips: add MSA 2RF format instructions") added
the MSA 2R/2RF instructions. However these instructions don't use any
target vector register, so remove the unused TCG temporaries.
Reviewed-by: Richard He
Avoid using a TCG temporary by moving Data Format to the constant pool.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/tcg/msa_translate.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index 5e8f8
Replace temporary TCG registers by tcg_constant_*() when possible.
Philippe Mathieu-Daudé (8):
target/mips: Remove unused register from MSA 2R/2RF instruction format
target/mips: Use tcg_constant_i32() in gen_msa_elm_df()
target/mips: Use tcg_constant_i32() in gen_msa_2rf()
target/mips: Us
Avoid using a TCG temporary by moving Data Format to the constant pool.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/tcg/msa_translate.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index 20036ae4
Avoid using a TCG temporary by moving Data Format to the constant pool.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/tcg/msa_translate.c | 23 ++-
1 file changed, 14 insertions(+), 9 deletions(-)
diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_tra
Data Format is a 2-bit constant value.
Avoid using a TCG temporary by moving it to the constant pool.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/tcg/msa_translate.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/
We already use sextract32(), use extract32() for completeness
instead of open-coding it.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/tcg/msa_translate.c | 11 ---
1 file changed, 4 insertions(+), 7 deletions(-)
diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa
Avoid using a TCG temporary by moving Data Format to the constant pool.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/tcg/msa_translate.c | 40 -
1 file changed, 24 insertions(+), 16 deletions(-)
diff --git a/target/mips/tcg/msa_translate.c b/target/mips/
The offset is constant and read-only: move it to the constant pool.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/tcg/translate.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
index 148afec9dc0..d4e0fbd35b
On Freitag, 1. Oktober 2021 13:21:23 CEST Christian Schoenebeck wrote:
> Hi Michael,
>
> while testing the following kernel patches I realized there is currently a
> size limitation of 4 MB with virtio on QEMU side:
> https://lore.kernel.org/netdev/cover.1632327421.git.linux_...@crudebyte.com/
>
VIRTQUEUE_MAX_SIZE reflects the absolute theoretical maximum
queue size possible, which is actually the maximum queue size
allowed by the virtio protocol. The appropriate value for
VIRTQUEUE_MAX_SIZE is therefore 32768:
https://docs.oasis-open.org/virtio/virtio/v1.1/cs01/virtio-v1.1-cs01.html#x1-2
From: Peter Delevoryas
v1: https://lore.kernel.org/qemu-devel/20211002214414.2858382-1-p...@fbc.om/
v2:
- Added summary of changes above signed-off-by in commit message.
- Added #define's for ADC and ADC engine memory region sizes.
- Fixed "From: p...@fbc.com"
Thanks,
Peter
Andrew Jeffery (2):
From: Andrew Jeffery
This model implements enough behaviour to do basic functionality tests
such as device initialisation and read out of dummy sample values. The
sample value generation strategy is similar to the STM ADC already in
the tree.
Signed-off-by: Andrew Jeffery
[clg : support for mul
From: Andrew Jeffery
Signed-off-by: Andrew Jeffery
Signed-off-by: Cédric Le Goater
Signed-off-by: Peter Delevoryas
---
hw/arm/aspeed_ast2600.c | 11 +++
hw/arm/aspeed_soc.c | 11 +++
include/hw/arm/aspeed_soc.h | 2 ++
3 files changed, 24 insertions(+)
diff --git
On 10/3/21 1:57 PM, Philippe Mathieu-Daudé wrote:
Data Format is a 2-bit constant value.
Avoid using a TCG temporary by moving it to the constant pool.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/tcg/msa_translate.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
Reviewed-
On 10/3/21 1:57 PM, Philippe Mathieu-Daudé wrote:
Avoid using a TCG temporary by moving Data Format to the constant pool.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/tcg/msa_translate.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
Reviewed-by: Richard Henderson
r~
On 10/3/21 1:57 PM, Philippe Mathieu-Daudé wrote:
Avoid using a TCG temporary by moving Data Format to the constant pool.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/tcg/msa_translate.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
Reviewed-by: Richard Henderson
r~
On 10/3/21 1:57 PM, Philippe Mathieu-Daudé wrote:
/* adjust df value for floating-point instruction */
-tcg_gen_movi_i32(tdf, df + 2);
+switch (MASK_MSA_3RF(ctx->opcode)) {
+case OPC_MUL_Q_df:
+case OPC_MADD_Q_df:
+case OPC_MSUB_Q_df:
+case OPC_MULR_Q_df:
+case O
On 10/3/21 1:57 PM, Philippe Mathieu-Daudé wrote:
We already use sextract32(), use extract32() for completeness
instead of open-coding it.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/tcg/msa_translate.c | 11 ---
1 file changed, 4 insertions(+), 7 deletions(-)
Reviewed-by:
On 10/3/21 1:57 PM, Philippe Mathieu-Daudé wrote:
+switch (MASK_MSA_I5(ctx->opcode)) {
+case OPC_ADDVI_df:
+case OPC_MAXI_U_df:
+case OPC_MINI_U_df:
+case OPC_CLTI_U_df:
+case OPC_CLEI_U_df:
+timm = tcg_constant_i32(extract32(ctx->opcode, 16, 5));
+break;
+
1 - 100 of 113 matches
Mail list logo
