Peter Maydell writes:
> On Fri, 24 Sept 2021 at 15:43, Daniel P. Berrangé wrote:
>>
>> On Fri, Sep 24, 2021 at 03:35:52PM +0200, Markus Armbruster wrote:
>> > Peter Maydell writes:
>> > > Side side note: the JSON event doesn't seem to contemplate
>> > > the possibility that a machine might have
Peter Maydell writes:
> This patchset moves RTC_CHANGE back to misc.json, effectively
> reverting commit 183e4281a30962, which moved the RTC_CHANGE event to
> the target schema. That change was an attempt to make the event
> target-specific to improve introspection, but the event isn't really
>
On Sat, 25 Sept 2021 at 07:25, Markus Armbruster wrote:
>
> The following changes since commit 11a11998460ed84d9a127c025f50f7234e5a483f:
>
> Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20210921' into
> staging (2021-09-24 13:21:18 -0400)
>
> are available in the Git repository at:
>
On 9/24/21 19:25, WANG Xuerui wrote:
Signed-off-by: WANG Xuerui
Reviewed-by: Richard Henderson
---
tcg/loongarch64/tcg-target-con-str.h | 28 +++
tcg/loongarch64/tcg-target.c.inc | 52
2 files changed, 80 insertions(+)
create mode 100644 tcg/lo
On 9/24/21 19:25, WANG Xuerui wrote:
Signed-off-by: WANG Xuerui
Reviewed-by: Richard Henderson
---
tcg/loongarch64/tcg-target.c.inc | 32
1 file changed, 32 insertions(+)
Reviewed-by: Philippe Mathieu-Daudé
On 9/24/21 19:25, WANG Xuerui wrote:
Signed-off-by: WANG Xuerui
Reviewed-by: Richard Henderson
---
tcg/loongarch64/tcg-target.c.inc | 109 +++
1 file changed, 109 insertions(+)
+/* Loads a 32-bit immediate into rd, sign-extended. */
+static void tcg_out_movi_i
On 9/24/21 19:25, WANG Xuerui wrote:
Signed-off-by: WANG Xuerui
Reviewed-by: Richard Henderson
---
tcg/loongarch64/tcg-target-con-set.h | 1 +
tcg/loongarch64/tcg-target.c.inc | 82
tcg/loongarch64/tcg-target.h | 24
3 files changed, 95 in
On 9/24/21 19:25, WANG Xuerui wrote:
Signed-off-by: WANG Xuerui
Reviewed-by: Richard Henderson
---
tcg/loongarch64/tcg-target-con-set.h | 2 +
tcg/loongarch64/tcg-target.c.inc | 88
tcg/loongarch64/tcg-target.h | 16 ++---
3 files changed, 98 inser
On 9/24/21 19:25, WANG Xuerui wrote:
The neg_i{32,64} ops is fully expressible with sub, so omitted for
simplicity.
Signed-off-by: WANG Xuerui
Reviewed-by: Richard Henderson
---
tcg/loongarch64/tcg-target-con-set.h | 2 ++
tcg/loongarch64/tcg-target.c.inc | 38 +
On 9/24/21 19:25, WANG Xuerui wrote:
Signed-off-by: WANG Xuerui
Reviewed-by: Richard Henderson
---
tcg/loongarch64/tcg-target-con-set.h | 1 +
tcg/loongarch64/tcg-target.c.inc | 91
tcg/loongarch64/tcg-target.h | 4 +-
3 files changed, 94 insertio
On 9/24/21 19:25, WANG Xuerui wrote:
Signed-off-by: WANG Xuerui
Reviewed-by: Richard Henderson
---
tcg/loongarch64/tcg-target-con-set.h | 1 +
tcg/loongarch64/tcg-target.c.inc | 65
tcg/loongarch64/tcg-target.h | 16 +++
3 files changed, 74 ins
On 9/24/21 19:25, WANG Xuerui wrote:
Signed-off-by: WANG Xuerui
Reviewed-by: Richard Henderson
---
tcg/loongarch64/tcg-target-con-set.h | 1 +
tcg/loongarch64/tcg-target.c.inc | 53
2 files changed, 54 insertions(+)
diff --git a/tcg/loongarch64/tcg-targe
On 9/24/21 19:25, WANG Xuerui wrote:
Signed-off-by: WANG Xuerui
Reviewed-by: Richard Henderson
---
tcg/loongarch64/tcg-target-con-set.h | 1 +
tcg/loongarch64/tcg-target.c.inc | 131 +++
2 files changed, 132 insertions(+)
Reviewed-by: Philippe Mathieu-Daudé
On 9/24/21 19:25, WANG Xuerui wrote:
Signed-off-by: WANG Xuerui
Reviewed-by: Richard Henderson
---
accel/tcg/user-exec.c | 73 +++
1 file changed, 73 insertions(+)
diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
index 8fed542622..38d4ad8a7d
On 9/24/21 19:25, WANG Xuerui wrote:
Could you add an 'uname -a' here as example?
Signed-off-by: WANG Xuerui
Reviewed-by: Richard Henderson
---
configure | 7 ++-
meson.build | 2 +-
2 files changed, 7 insertions(+), 2 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
On 9/22/21 08:14, Warner Losh wrote:
Signed-off-by: Warner Losh
---
bsd-user/i386/target_arch_cpu.h | 2 --
bsd-user/x86_64/target_arch_cpu.h | 2 --
2 files changed, 4 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
On 9/22/21 08:14, Warner Losh wrote:
Make get_errno and is_error global so files other than syscall.c can use
them.
Signed-off-by: Warner Losh
---
bsd-user/qemu.h| 4
bsd-user/syscall.c | 10 +-
2 files changed, 9 insertions(+), 5 deletions(-)
diff --git a/bsd-user/qemu.h
On 9/22/21 08:14, Warner Losh wrote:
Move TARGET_MC_GET_CLEAR_RET to freebsd/target_os_signal.h since it's
FreeBSD-wide.
"architecture agnostic (on FreeBSD)" instead?
Signed-off-by: Warner Losh
---
bsd-user/freebsd/target_os_signal.h | 3 +++
bsd-user/i386/target_arch_signal.h | 2 --
On 9/22/21 08:14, Warner Losh wrote:
All architectures have a ELF_HWCAP, so remove the fallback ifdef.
Place ELF_HWCAP in the same order as on native FreeBSD.
Signed-off-by: Warner Losh
---
bsd-user/freebsd/target_os_elf.h | 8 ++--
1 file changed, 2 insertions(+), 6 deletions(-)
Revie
On 9/22/21 08:14, Warner Losh wrote:
Some architecutres publish AT_HWCAP2 as well as AT_HWCAP. Those
Typo "architectures"
architectures will define this in their target_arch_elf.h files. If it
is defined, then publish it.
Signed-off-by: Warner Losh
---
bsd-user/freebsd/target_os_elf.h |
On 9/22/21 08:14, Warner Losh wrote:
The used field of TaskState is write only. Eliminate it.
The 'used' field ...
Signed-off-by: Warner Losh
---
bsd-user/main.c | 1 -
bsd-user/qemu.h | 1 -
2 files changed, 2 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
On 9/22/21 08:14, Warner Losh wrote:
To avoid a name clash with FreeBSD's sigqueue data structure in
signalvar.h, rename sigqueue to qemu_sigqueue. This sturcture
is currently defined, but unused.
Signed-off-by: Warner Losh
---
bsd-user/qemu.h | 14 +++---
1 file changed, 7 insertion
Hi Warner,
On 9/22/21 08:14, Warner Losh wrote:
Add the missing glue to pull in do_freebsd_sysarch to call
do_freebsd_arch_sysarch. Put it in os-sys.c, which will be used for
sysctl and sysarch system calls because they are mostly arch specific.
Signed-off-by: Stacey Son
Signed-off-by: Warner
On 9/22/21 08:14, Warner Losh wrote:
Create dummy signal queueing function so we can start to integrate other
architectures (at the cost of signals remaining broken) to tame the
dependency graph a bit and to bring in signals in a more controlled
fashion.
Signed-off-by: Warner Losh
---
bsd-use
On 9/22/21 06:56, Warner Losh wrote:
From: Mikaël Urankar
Simmilar to the equivalent linux-user: commit fb7e378cf9c, which added
checking to pread's return value.
Signed-off-by: Mikaël Urankar
Signed-off-by: Warner Losh
---
bsd-user/mmap.c | 6 --
1 file changed, 4 insertions(+), 2 de
On 9/22/21 06:56, Warner Losh wrote:
mmap should return ENOMEM on len overflow rather than EINVAL. Return
EINVAL when len == 0 and ENOMEM when the rounded to a page length is 0.
Found by make check-tcg.
Signed-off-by: Warner Losh
---
bsd-user/mmap.c | 9 -
1 file changed, 8 insertion
On 9/22/21 06:56, Warner Losh wrote:
Similar to the equivalent linux-user change 86abac06c14. All error
conditions that target_mprotect checks are also checked by target_mmap.
EACCESS cannot happen because we are just removing PROT_WRITE. ENOMEM
should not happen because we are modifying a whole
Hi Peter,
On 9/24/21 08:19, p...@fb.com wrote:
From: Peter Delevoryas
The gpio array is declared as a dense array:
...
qemu_irq gpios[ASPEED_GPIO_NR_PINS];
(AST2500 has 228, AST2400 has 216, AST2600 has 208)
However, this array is used like a matrix of GPIO sets
(e.g. gpio[NR_SETS][NR_PINS_
On 9/23/21 18:11, Willian Rampazzo wrote:
Add instructions to the Acceptance tests section about running a
single test file or a test within the test file.
Signed-off-by: Willian Rampazzo
---
docs/devel/testing.rst | 28
1 file changed, 28 insertions(+)
Reviewe
On 9/23/21 18:11, Willian Rampazzo wrote:
Although it is possible to run a specific test using the avocado
command-line, a user may want to use a specific tag while running the
``make check-acceptance`` during the development or debugging.
This allows using the AVOCADO_TAGS environment variable
On 9/23/21 18:11, Willian Rampazzo wrote:
Add the possibility of running all the tests from a single file, or
multiple files, running a single test within a file or multiple tests
within multiple files using `make check-acceptance` and the
AVOCADO_TESTS environment variable.
Suggested-by: Daniel
El lun., 9 ago. 2021 12:40, Peter Maydell
escribió:
> Is it right, or is this its "looks like this is returning an error
> indication" heuristic misfiring again ?
>
> My guess is the latter and it's caused by a mismatch
> between the prototype of visit_optional() (returns a
> status both by setti
Hi Bin,
On 9/23/21 12:29, Philippe Mathieu-Daudé wrote:
On 9/23/21 07:16, Bin Meng wrote:> On Sun, Sep 19, 2021 at 2:07 AM
Philippe Mathieu-Daudé wrote:
- Embed SerialMM in MchpPfSoCMMUartState and QOM-initialize it
- Alias SERIAL_MM 'chardev' property on MCHP_PFSOC_UART
- Forward SerialMM sy
Hi,
This series QOM'ify the PolarFire UART (the project
would get ride of non-QOM devices).
Since v1:
- Simplify MCHP_PFSOC_MMUART_REG_SIZE
- Use MemoryRegion container
- Mention qdev_set_legacy_instance_id() is not needed (Bin)
- Properly map the 16550 (Bin)
- Add DeviceReset() method (Peter)
-
The current MCHP_PFSOC_MMUART_REG_SIZE definition represent the
size occupied by all the registers. However all registers are
32-bit wide, and the MemoryRegionOps handlers are restricted to
32-bit:
static const MemoryRegionOps mchp_pfsoc_mmuart_ops = {
.read = mchp_pfsoc_mmuart_read,
- Embed SerialMM in MchpPfSoCMMUartState and QOM-initialize it
- Alias SERIAL_MM 'chardev' property on MCHP_PFSOC_UART
- Forward SerialMM sysbus IRQ in mchp_pfsoc_mmuart_realize()
- Add DeviceReset() method
- Add vmstate structure for migration
- Register device in 'input' category
- Keep mchp_pfso
Our device have 2 different I/O regions:
- a 16550 UART mapped for 32-bit accesses
- 13 extra registers
Instead of mapping each region on the main bus, introduce
a container, map the 2 devices regions on the container,
and map the container on the main bus.
Before:
(qemu) info mtree
...
On 9/25/21 5:54 AM, Philippe Mathieu-Daudé wrote:
+ /* High bits must be set; load with lu12i.w + optional ori. */
+ tcg_target_long hi12 = sextreg(val, 12, 20);
Please declare variables in function prologue.
Ah, true. Officially, that's qemu coding style. I tend to overlook it becau
On 9/25/21 6:05 AM, Philippe Mathieu-Daudé wrote:
+ case INDEX_op_shl_i32:
+ if (c2) {
Why can't we use:
tcg_debug_assert(a2 <= 0x1f);
tcg_out_opc_slli_w(s, a0, a1, a2);
?
Because tcg/optimize.c can produce out-of-range values.
We have this same mas
On 9/25/21 6:13 AM, Philippe Mathieu-Daudé wrote:
+static const struct {
+ LoongArchInsn op;
+ bool swap;
+} tcg_brcond_to_loongarch[] = {
Richard, TCGCond is 4-bit, shouldn't we explicit this array
size to 16, and even better define TCG_COND_COUNT = 16 in
"tcg/tcg-cond.h"?
Perhaps. No
On 9/25/21 16:09, Richard Henderson wrote:
On 9/25/21 6:05 AM, Philippe Mathieu-Daudé wrote:
+ case INDEX_op_shl_i32:
+ if (c2) {
Why can't we use:
tcg_debug_assert(a2 <= 0x1f);
tcg_out_opc_slli_w(s, a0, a1, a2);
?
Because tcg/optimize.c can produc
On 9/24/21 11:51 PM, WANG Xuerui wrote:
Hi all,
On 9/25/21 01:25, WANG Xuerui wrote:
Signed-off-by: WANG Xuerui
Acked-by: Richard Henderson
---
tcg/loongarch64/tcg-insn-defs.c.inc | 979
1 file changed, 979 insertions(+)
create mode 100644 tcg/loongarch64/tcg
On 9/24/21 11:38, Philippe Mathieu-Daudé wrote:
CPU has_work() is a per-accelerator handler. This series is organized
in 2 parts:
- Patches 1-15: Move has_work() from CPUClass to AccelOpsClass
- Patches 16-40: Move remainging has_work() to TCGCPUOps
target/arm: Explicit v7M cores use arm_c
> On Sep 25, 2021, at 4:03 AM, Philippe Mathieu-Daudé wrote:
>
> Hi Peter,
>
>> On 9/24/21 08:19, p...@fb.com wrote:
>> From: Peter Delevoryas
>> The gpio array is declared as a dense array:
>> ...
>> qemu_irq gpios[ASPEED_GPIO_NR_PINS];
>> (AST2500 has 228, AST2400 has 216, AST2600 has 208)
On 9/25/21 16:20, Richard Henderson wrote:
On 9/24/21 11:51 PM, WANG Xuerui wrote:
Hi all,
On 9/25/21 01:25, WANG Xuerui wrote:
Signed-off-by: WANG Xuerui
Acked-by: Richard Henderson
---
tcg/loongarch64/tcg-insn-defs.c.inc | 979
1 file changed, 979 insertions
On 9/25/21 16:12, Richard Henderson wrote:
On 9/25/21 6:13 AM, Philippe Mathieu-Daudé wrote:
+static const struct {
+ LoongArchInsn op;
+ bool swap;
+} tcg_brcond_to_loongarch[] = {
Richard, TCGCond is 4-bit, shouldn't we explicit this array
size to 16, and even better define TCG_COND_CO
On 9/24/21 3:53 PM, Helge Deller wrote:
Changes in seabios-hppa:
* Include all latest upstream SeaBIOS patches
* add support for the qemu "bootindex" parameter
* add support for the qemu "-boot order=g-m" parameter to choose
SCSI ID
Signed-off-by: Helge Deller
Thanks, queued.
r~
Hi,
CPU has_work() is a per-accelerator handler. This series is organized
in 2 parts:
- Patches 1-15: Move has_work() from CPUClass to AccelOpsClass
- Patches 16-40: Move remainging has_work() to TCGCPUOps
I prefer to send as a single big series to be sure it is merged
at once, since the 2nd part
Implement WHPX has_work() handler in AccelOpsClass and
remove it from cpu_thread_is_idle() since cpu_has_work()
is already called.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
softmmu/cpus.c| 4 +---
target/i386/whpx/whpx-accel-ops.c | 6 ++
2
cpus_register_accel() already checks for ops->create_vcpu_thread
being non-NULL, so it is pointless to re-check for it in
qemu_init_vcpu().
Signed-off-by: Philippe Mathieu-Daudé
---
softmmu/cpus.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/softmmu/cpus.c b/softmmu
Restrict has_work() to sysemu.
Signed-off-by: Philippe Mathieu-Daudé
---
target/alpha/cpu.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c
index 93e16a2ffb4..1ca601cac5b 100644
--- a/target/alpha/cpu.c
+++ b/target/alpha/cpu.c
@@ -3
We want to make cpu_has_work() per-accelerator. Only declare its
prototype and move its definition to softmmu/cpus.c.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/core/cpu.h | 8 +---
softmmu/cpus.c| 8
2 files changed, 9 insertions(+)
Since there is no specific Xen handling for cpu_has_work() in
cpu_thread_is_idle(), implement Xen has_work() handler as a
simple 'return false' code.
Acked-by: Paul Durrant
Signed-off-by: Philippe Mathieu-Daudé
---
accel/xen/xen-all.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/ac
cpu_has_work() is only called from system emulation code.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/core/cpu.h | 32
1 file changed, 16 insertions(+), 16 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core
Restrict has_work() to sysemu.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
target/cris/cpu.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/target/cris/cpu.c b/target/cris/cpu.c
index c2e7483f5bd..b2761f8b110 100644
--- a/target/cris/cpu.c
+
Introduce an accelerator-specific has_work() handler.
Eventually call it from cpu_has_work().
Suggested-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
include/sysemu/accel-ops.h | 5 +
softmmu/cpus.c | 3 +++
2 files changed, 8 insertions(+)
diff --git a/includ
Now that all accelerators implement a has_work() handler, we can
simplify cpu_has_work() by removing the non-NULL handler check.
Add an assertion in cpus_register_accel() for future accelerators.
Suggested-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
softmmu/cpus.c | 6 ++---
has_work() is sysemu specific, and Hexagon target only provides
a linux-user implementation. Remove the unused hexagon_cpu_has_work().
Reviewed-by: Richard Henderson
Reviewed-by: Taylor Simpson
Signed-off-by: Philippe Mathieu-Daudé
---
target/hexagon/cpu.c | 6 --
1 file changed, 6 deletio
Implement KVM has_work() handler in AccelOpsClass and
remove it from cpu_thread_is_idle() since cpu_has_work()
is already called.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
accel/kvm/kvm-accel-ops.c | 6 ++
softmmu/cpus.c| 2 +-
2 files changed, 7 i
cpu_class_init() always register cpu_common_has_work() as
CPUClass::has_work() handler, so the assertion check in
cpu_has_work() is pointless.
Since cpu_common_has_work() simply returns 'false', we can
inline it in cpu_has_work(), improving the function readability.
Suggested-by: Richard Henderson
Restrict has_work() to TCG sysemu.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
target/i386/cpu.c | 6 --
target/i386/tcg/tcg-cpu.c | 8 +++-
2 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 6b
Restrict has_work() to sysemu.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
target/hppa/cpu.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c
index 89cba9d7a2c..000c2e7793a 100644
--- a/target/hppa/cpu.c
++
Since there is no specific HVF handling for cpu_has_work() in
cpu_thread_is_idle(), implement HVF has_work() handler as a
simple 'return false' code.
Signed-off-by: Philippe Mathieu-Daudé
---
accel/hvf/hvf-accel-ops.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/accel/hvf/hvf-accel-
Since there is no specific HAX handling for cpu_has_work() in
cpu_thread_is_idle(), implement HAX has_work() handler as a
simple 'return false' code.
Signed-off-by: Philippe Mathieu-Daudé
---
target/i386/hax/hax-accel-ops.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/target/i386/ha
Restrict has_work() to sysemu.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
target/microblaze/cpu.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
index 15db277925f..36e6e540483 100644
---
Restrict has_work() to TCG sysemu.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/cpu.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index 00e0c55d0e4..3639c03f8ea 100644
--- a/target/mips/cpu.
Restrict has_work() to sysemu.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
target/openrisc/cpu.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
index 27cb04152f9..3c368a1bde7 100644
--- a/target/o
Since there is no specific NVMM handling for cpu_has_work() in
cpu_thread_is_idle(), implement NVMM has_work() handler as a
simple 'return false' code.
Signed-off-by: Philippe Mathieu-Daudé
---
target/i386/nvmm/nvmm-accel-ops.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/target/i38
Implement QTest has_work() handler in AccelOpsClass.
Since no CPU are available under QTest accelerator,
this function is not reachable.
Signed-off-by: Philippe Mathieu-Daudé
---
accel/qtest/qtest.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/accel/qtest/qtest.c b/accel/qtest/qtest
Restrict has_work() to sysemu.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
target/nios2/cpu.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c
index 947bb09bc1e..9938d7c2919 100644
--- a/target/nios2/cpu.
All accelerators but TCG implement their AccelOpsClass::has_work()
handler, meaning all the remaining CPUClass::has_work() ones are
only reachable from TCG accelerator; and these has_work() handlers
belong to TCGCPUOps.
We will gradually move each target CPUClass::has_work() to
TCGCPUOps in the fo
We're moving the hook from CPUState to TCGCPUOps. TCGCPUOps is
a const structure, so to avoid creating multiple versions of
the same structure, simply changing the has_work() handler,
introduce yet another indirection with a has_work() handler in
PowerPCCPUClass, and ppc_cpu_has_work() method which
On Sat, Sep 25, 2021, 4:50 AM Philippe Mathieu-Daudé
wrote:
> On 9/22/21 08:14, Warner Losh wrote:
> > Create dummy signal queueing function so we can start to integrate other
> > architectures (at the cost of signals remaining broken) to tame the
> > dependency graph a bit and to bring in signal
Introduce a target-specific has_work() handler for TCG.
Eventually call it from tcg_cpu_has_work(), our
AccelOpsClass::has_work() handler.
Inspired-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/core/tcg-cpu-ops.h | 4
accel/tcg/tcg-accel-ops.c | 4
2 f
Restrict PowerPCCPUClass::has_work() and ppc_cpu_has_work()
- SysemuCPUOps::has_work() implementation - to TCG sysemu.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
target/ppc/cpu-qom.h | 4 +++-
target/ppc/cpu_init.c | 24 ++--
2 files changed,
Restrict has_work() to sysemu.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
target/xtensa/cpu.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
index c1cbd03595e..5cb19a88819 100644
--- a/ta
Restrict has_work() to sysemu.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
target/rx/cpu.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/rx/cpu.c b/target/rx/cpu.c
index 25a4aa2976d..ac6b40b2716 100644
--- a/target/rx/cpu.c
+++ b/targ
ARM v7M cores inherit TYPE_ARM_CPU, so TYPE_ARM_CPU's class_init runs
first and sets up most of the class fields, setting in particular the
has_work handler to the generic arm_cpu_has_work(). Thus M-profile
and A-profile share the same arm_cpu_has_work() function. Some of the
checks the code there
Restrict has_work() to TCG sysemu.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
hw/intc/s390_flic.c | 15 ---
target/s390x/cpu.c | 4 +++-
2 files changed, 15 insertions(+), 4 deletions(-)
diff --git a/hw/intc/s390_flic.c b/hw/intc/s390_flic.c
index 74
Restrict has_work() to sysemu.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
target/sparc/cpu.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
index 0d252cb5bdc..8d61bf15f6c 100644
--- a/target/sparc/cpu.
Restrict arm_cpu_has_work() and has_work() handler to TCG sysemu.
Signed-off-by: Philippe Mathieu-Daudé
---
target/arm/internals.h | 4 +++-
target/arm/cpu.c | 7 +--
target/arm/cpu_tcg.c | 2 +-
3 files changed, 9 insertions(+), 4 deletions(-)
diff --git a/target/arm/internals.h b/
Adding Alex to the Cc list re docker testing.
On 9/25/21 10:31 AM, Philippe Mathieu-Daudé wrote:
Xuerui said on the cover 1/ we can buy a board on Taobao and 2/ Loongson
might help the community with hardware.
I tried 1/, spend more than 2h to read a translated version of the EULA,
succeeded at
Restrict has_work() to sysemu.
Reviewed-by: Richard Henderson
Reviewed-by: Bastian Koppelmann
Signed-off-by: Philippe Mathieu-Daudé
---
target/tricore/cpu.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c
index b95682b7f04..4
Now that all TCG targets converted their CPUClass::has_work()
handler to a TCGCPUOps::has_work() one, we can remove has_work
from CPUClass.
Suggested-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/core/cpu.h | 2 --
accel/tcg/tcg-accel-ops.c | 3 ---
2 files chan
Restrict has_work() to sysemu.
Reviewed-by: Richard Henderson
Reviewed-by: Michael Rolnik
Signed-off-by: Philippe Mathieu-Daudé
---
target/avr/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/avr/cpu.c b/target/avr/cpu.c
index 5d70e34dd54..6d51f91ca2c 100644
---
Restrict has_work() to sysemu.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
target/m68k/cpu.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c
index 66d22d11895..ad5d26b5c9e 100644
--- a/target/m68k/cpu.c
++
Restrict has_work() to TCG sysemu.
Reviewed-by: Richard Henderson
Acked-by: Alistair Francis
Signed-off-by: Philippe Mathieu-Daudé
---
target/riscv/cpu.c | 8 +++-
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 7c626d89cd7..ca76b
+Igor
On 9/25/21 16:50, Philippe Mathieu-Daudé wrote:
Implement QTest has_work() handler in AccelOpsClass.
Since no CPU are available under QTest accelerator,
this function is not reachable.
Signed-off-by: Philippe Mathieu-Daudé
---
accel/qtest/qtest.c | 6 ++
1 file changed, 6 insertio
On 9/25/21 10:50 AM, Philippe Mathieu-Daudé wrote:
Philippe Mathieu-Daudé (40):
accel: Simplify qemu_init_vcpu()
hw/core: Restrict cpu_has_work() to sysemu
hw/core: Un-inline cpu_has_work()
hw/core: Move cpu_common_has_work() to cpu_has_work()
accel: Introduce AccelOpsClass::has_wo
On 9/25/21 11:27 AM, Philippe Mathieu-Daudé wrote:
+static bool qtest_cpu_has_work(CPUState *cpu)
+{
+ g_assert_not_reached();
+}
Sigh, this triggers:
Running test qtest-i386/cpu-plug-test
**
ERROR:../accel/qtest/qtest.c:52:qtest_cpu_has_work: code should not be reached
ERROR qtest-i386/cpu
Restrict has_work() to sysemu.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
target/sh4/cpu.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c
index 2047742d03c..fb2116dc52e 100644
--- a/target/sh4/cpu.c
+++
The SPARC target only support TCG acceleration. Remove the CONFIG_TCG
definition introduced by mistake in commit 78271684719 ("cpu: tcg_ops:
move to tcg-cpu-ops.h, keep a pointer in CPUClass").
Reported-by: Richard Henderson
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
-
All TCG targets implement the TCGCPUOps::has_work() handler.
We can remove the non-NULL handler check in tcg_cpu_has_work().
Add an assertion in tcg_exec_realizefn() for future TCG targets.
Signed-off-by: Philippe Mathieu-Daudé
---
accel/tcg/cpu-exec.c | 6 ++
accel/tcg/tcg-accel-ops.c
On 9/25/21 10:50 AM, Philippe Mathieu-Daudé wrote:
cpus_register_accel() already checks for ops->create_vcpu_thread
being non-NULL, so it is pointless to re-check for it in
qemu_init_vcpu().
Signed-off-by: Philippe Mathieu-Daudé
---
softmmu/cpus.c | 7 +--
1 file changed, 5 insertions(+),
On 9/25/21 17:28, Richard Henderson wrote:
On 9/25/21 10:50 AM, Philippe Mathieu-Daudé wrote:
Philippe Mathieu-Daudé (40):
accel: Simplify qemu_init_vcpu()
hw/core: Restrict cpu_has_work() to sysemu
hw/core: Un-inline cpu_has_work()
hw/core: Move cpu_common_has_work() to cpu_has_work
On 9/25/21 17:32, Richard Henderson wrote:
On 9/25/21 11:27 AM, Philippe Mathieu-Daudé wrote:
+static bool qtest_cpu_has_work(CPUState *cpu)
+{
+ g_assert_not_reached();
+}
Sigh, this triggers:
Running test qtest-i386/cpu-plug-test
**
ERROR:../accel/qtest/qtest.c:52:qtest_cpu_has_work: cod
Hi Richard,
On 9/25/21 22:20, Richard Henderson wrote:
On 9/24/21 11:51 PM, WANG Xuerui wrote:
Hi all,
On 9/25/21 01:25, WANG Xuerui wrote:
Signed-off-by: WANG Xuerui
Acked-by: Richard Henderson
---
tcg/loongarch64/tcg-insn-defs.c.inc | 979
1 file changed,
Hi Philippe,
On 9/25/21 17:54, Philippe Mathieu-Daudé wrote:
On 9/24/21 19:25, WANG Xuerui wrote:
Signed-off-by: WANG Xuerui
Reviewed-by: Richard Henderson
---
tcg/loongarch64/tcg-target.c.inc | 109 +++
1 file changed, 109 insertions(+)
+/* Loads a 32-bit im
On 9/25/21 16:04, Richard Henderson wrote:
On 9/25/21 5:54 AM, Philippe Mathieu-Daudé wrote:
+ /* High bits must be set; load with lu12i.w + optional ori. */
+ tcg_target_long hi12 = sextreg(val, 12, 20);
+ tcg_out_opc_lu12i_w(s, rd, hi12);
+ if (lo != 0) {
+ tcg_out_opc_o
Hi Richard,
On 9/25/21 23:20, Richard Henderson wrote:
Adding Alex to the Cc list re docker testing.
On 9/25/21 10:31 AM, Philippe Mathieu-Daudé wrote:
Xuerui said on the cover 1/ we can buy a board on Taobao and 2/ Loongson
might help the community with hardware.
I tried 1/, spend more than
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