Re: [PATCH v2] hw/intc/sifive_clint: Fix expiration time logic

On Sun, Aug 29, 2021 at 12:27 PM s101062801 wrote: > > After timecmp is modified, the value is converted into nanosecond, > and pass to timer_mod. However, timer_mod perceives the value as > a signed integer. An example that goes wrong is as follows: > > OpenSBI v0.9 initializes the cold boot ha

[PATCH 42/48] tcg/optimize: Add more simplifications for orc

Two simplifications that were missing from before the split to fold functions, and are now easy to provide. Signed-off-by: Richard Henderson --- tcg/optimize.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/tcg/optimize.c b/tcg/optimize.c index a66ac77c29..6feaf905e7 100644 --- a/tcg/opti

[PATCH 38/48] tcg/optimize: Split out fold_masks

Move all of the known-zero optimizations into the per-opcode functions. Use fold_masks when there is a possibility of the result being determined, and simply set ctx->z_mask otherwise. Signed-off-by: Richard Henderson --- tcg/optimize.c | 545 ++--- 1

[PATCH 41/48] tcg/optimize: Sink commutative operand swapping into fold functions

Most of these are handled by creating a fold_const2_commutative to handle all of the binary operators. The rest were already handled on a case-by-case basis in the switch, and have their own fold function in which to place the call. We now have only one major switch on TCGOpcode. Signed-off-by:

[PATCH 46/48] tcg/optimize: Propagate sign info for setcond

The result is either 0 or 1, which means that we have a 2 bit signed result, and thus 62 bits of sign. For clarity, use the smask_from_zmask function. Signed-off-by: Richard Henderson --- tcg/optimize.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/tcg/optimize.c b/tcg/optimize.c index c

[PATCH 40/48] tcg/optimize: Expand fold_addsub2_i32 to 64-bit ops

Rename to fold_addsub2. Use Int128 to implement the wider operation. Signed-off-by: Richard Henderson --- tcg/optimize.c | 64 +- 1 file changed, 43 insertions(+), 21 deletions(-) diff --git a/tcg/optimize.c b/tcg/optimize.c index ae464339b4..ba1e

Re: QEMU-KVM offers OPAL firmware interface? OpenBSD guest support?

On Sun, Aug 29, 2021 at 04:09:54AM +, Joseph wrote: > Hi Mark, Cédric, Greg at the openbsd-ppc ML, > > It is great to talk to you. Thank you for taking on the conversation. > > Right, OpenBSD implements powernv meaning it runs on bare metal on > Power9, that is great. > > What I wanted to as

[PATCH 47/48] tcg/optimize: Propagate sign info for bit counting

The results are generally 6 bit unsigned values, though the count leading and trailing bits may produce any value for a zero input. Signed-off-by: Richard Henderson --- tcg/optimize.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/tcg/optimize.c b/tcg/optimize.c index 788a5acf10..dad72b2f

[PATCH 48/48] tcg/optimize: Propagate sign info for shifting

For constant shifts, we can simply shift the s_mask. For variable shifts, we know that sar does not reduce the s_mask, which helps for sequences like ext32s_i64 t, in sar_i64 t, t, v ext32s_i64 out, t allowing the final extend to be eliminated. Signed-off-by: Richard Henderson

Re: [PATCH 01/26] ppc: Add a POWER10 DD2 CPU

On 8/20/21 3:40 PM, Greg Kurz wrote: > On Mon, 9 Aug 2021 15:45:22 +0200 > Cédric Le Goater wrote: > >> The POWER10 DD2 CPU adds an extra LPCR[HAIL] bit. DD1 doesn't have >> HAIL but since it does not break the modeling and that we don't plan >> to support DD1, modify the LPCR mask of all the POW

Re: [PATCH 04/26] ppc/pnv: Use a simple incrementing index for the chip-id

On 8/20/21 3:51 PM, Greg Kurz wrote: > On Mon, 9 Aug 2021 15:45:25 +0200 > Cédric Le Goater wrote: > >> When the QEMU PowerNV machine was introduced, multi chip support >> modeled a two socket system with dual chip modules as found on some P8 >> Tuleta systems (8286-42A). But this is hardly used

Re: [PATCH 06/26] ppc/pnv: add a chip topology index for POWER10

On 8/20/21 4:12 PM, Greg Kurz wrote: > On Mon, 9 Aug 2021 15:45:27 +0200 > Cédric Le Goater wrote: > >> Signed-off-by: Cédric Le Goater > > Maybe add a short description of its purpose in the changelog > for the records ? What's the difference with "ibm,chip-id" ? yep. I will add a comment.

Re: [PATCH 10/26] ppc/xive2: Introduce a presenter matching routine

On 8/25/21 8:01 AM, David Gibson wrote: > On Mon, Aug 09, 2021 at 03:45:31PM +0200, Cédric Le Goater wrote: >> The VP space is larger in XIVE2 (P10), 24 bits instead of 19bits on >> XIVE (P9), and the CAM line can use a 7bits or 8bits thread id. >> >> For now, we only use 7bits thread ids, same as

Re: [PATCH 2/3] escc: fix R_STATUS channel reset value

On 29/08/2021 14:17, Peter Maydell wrote: On Sun, 29 Aug 2021 at 11:07, Mark Cave-Ayland wrote: According to the "Z80X30 Register Reset Values" table in the ESCC datasheet bits 2 and 6 are set whilst bits 0 and 1 are cleared during channel reset. All other bits should be left unaltered. Sign

Re: [PATCH 05/26] ppc/pnv: Distribute RAM among the chips

On 8/20/21 4:08 PM, Greg Kurz wrote: > On Mon, 9 Aug 2021 15:45:26 +0200 > Cédric Le Goater wrote: > >> But always give the first 1GB to chip 0 as skiboot requires it. >> >> Signed-off-by: Cédric Le Goater >> --- >> hw/ppc/pnv.c | 33 + >> 1 file changed, 25 inse

Re: [PATCH 09/26] ppc/xive2: Introduce a XIVE2 core framework

On 8/23/21 5:15 PM, Greg Kurz wrote: > On Mon, 9 Aug 2021 15:45:30 +0200 > Cédric Le Goater wrote: > >> The XIVE2 interrupt controller of the POWER10 processor as the same >> logic as on POWER9 but its SW interface has been largely reworked. The >> interrupt controller has a new register interfac

Re: [PATCH 0/3] escc: fix R_STATUS when SDLC mode is enabled

On 29/08/2021 14:19, Peter Maydell wrote: On Sun, 29 Aug 2021 at 11:05, Mark Cave-Ayland wrote: Here is another small set of ESCC fixes from my attempts to boot MacOS on the q800 machine. When MacOS loads the OpenTransport extension on boot it attempts to enable SDLC mode on the ESCC. QEMU'

Re: [PATCH v4 1/5] hw, spapr: add 6.2 compat pseries machine

On Fri, 27 Aug 2021 06:24:51 -0300 Daniel Henrique Barboza wrote: > Signed-off-by: Daniel Henrique Barboza > --- We usually introduce the compat machine types for all archs in a single patch. One was already posted for 6.2 : https://patchwork.ozlabs.org/project/qemu-devel/patch/20210823122804.

Re: [PATCH 5/5] qmp: Added qemu-ebpf-rss-path command.

On Mon, Aug 30, 2021 at 9:10 AM Markus Armbruster wrote: > > Yuri Benditovich writes: > > > On Tue, Aug 24, 2021 at 9:41 AM Markus Armbruster wrote: > >> > >> Andrew Melnichenko writes: > >> > >> > Hi, > >> > > >> >> The helper may or may not be installed at the path compiled into QEMU. > >> >>

Re: [PATCH 5/5] qmp: Added qemu-ebpf-rss-path command.

Yuri Benditovich writes: > On Mon, Aug 30, 2021 at 9:10 AM Markus Armbruster wrote: >> >> Yuri Benditovich writes: >> >> > On Tue, Aug 24, 2021 at 9:41 AM Markus Armbruster >> > wrote: >> >> >> >> Andrew Melnichenko writes: >> >> >> >> > Hi, >> >> > >> >> >> The helper may or may not be inst

[PATCH v5 1/3] target-arm: Add support for Fujitsu A64FX

Add a definition for the Fujitsu A64FX processor. The A64FX processor does not implement the AArch32 Execution state, so there are no associated AArch32 Identification registers. For SVE, the A64FX processor supports only 128,256 and 512bit vector lengths. Signed-off-by: Shuuichirou Ishii ---

[PATCH v5 0/3] Add support for Fujitsu A64FX processor

This is the v5 patch series. v5: A64FX supports only 128, 256, and 512bit SVE vector lengths, but the QEMU implementation prior to v4 did not have an API to specify a specific vector length. Andrew has implemented an API (cpu->sve_vq_supported, commit:5401b1e08d etc) to solve this, so we have chan

[PATCH v5 3/3] tests/arm-cpu-features: Add A64FX processor related

Signed-off-by: Shuuichirou Ishii --- tests/qtest/arm-cpu-features.c | 13 + 1 file changed, 13 insertions(+) diff --git a/tests/qtest/arm-cpu-features.c b/tests/qtest/arm-cpu-features.c index 8252b85bb8..90a87f0ea9 100644 --- a/tests/qtest/arm-cpu-features.c +++ b/tests/qtest/arm-cpu

[PATCH v5 2/3] hw/arm/virt: target-arm: Add A64FX processor support to virt machine

Add -cpu a64fx to use A64FX processor when -machine virt option is specified. In addition, add a64fx to the Supported guest CPU types in the virt.rst document. Signed-off-by: Shuuichirou Ishii --- docs/system/arm/virt.rst | 1 + hw/arm/virt.c| 1 + 2 files changed, 2 insertions(+)

Re: [PATCH v5 1/3] target-arm: Add support for Fujitsu A64FX

On Mon, Aug 30, 2021 at 05:28:18PM +0900, Shuuichirou Ishii wrote: > Add a definition for the Fujitsu A64FX processor. > > The A64FX processor does not implement the AArch32 Execution state, > so there are no associated AArch32 Identification registers. > > For SVE, the A64FX processor supports o

Re: [PATCH v5 3/3] tests/arm-cpu-features: Add A64FX processor related

On Mon, Aug 30, 2021 at 05:28:20PM +0900, Shuuichirou Ishii wrote: nit: A commit message would be nice, even if it's just a simple sentence expanding on the summary. > Signed-off-by: Shuuichirou Ishii > --- > tests/qtest/arm-cpu-features.c | 13 + > 1 file changed, 13 insertions(+)

Re: [PATCH v5 2/3] hw/arm/virt: target-arm: Add A64FX processor support to virt machine

On Mon, Aug 30, 2021 at 05:28:19PM +0900, Shuuichirou Ishii wrote: > Add -cpu a64fx to use A64FX processor when -machine virt option is specified. > In addition, add a64fx to the Supported guest CPU types in the virt.rst > document. > > Signed-off-by: Shuuichirou Ishii > --- > docs/system/arm/v

RE: [PATCH v5 1/3] target-arm: Add support for Fujitsu A64FX

Thank you for your quick comments. > Question: For testing, did you dump all the ID registers on this > model and compare them with a dump of ID registers from real > hardware? If so, that would be good info to put in the commit > message or at least the cover letter. Yes, it has been tested and

[Bug 1819289] Re: Windows 95 and Windows 98 will not install or run

Brad said later after testing v6.1 it was fixed so please disregard previous comment ¯\_(ツ)_/¯ -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1819289 Title: Windows 95 and Windows 98 will not instal

Re: [PATCH 0/3] Use meson_options.txt in the configure script

On 8/30/21 7:11 AM, Thomas Huth wrote: > On 29/08/2021 23.22, Marc-André Lureau wrote: >> Hi Thomas >> >> On Sun, Aug 29, 2021 at 9:32 PM Thomas Huth > > wrote: >> >>     It's cumbersome to maintain the build options twice, one time in the >>     configure script and one ti

Re: [PATCH 01/48] tcg/optimize: Rename "mask" to "z_mask"

On 8/30/21 8:24 AM, Richard Henderson wrote: > Prepare for tracking different masks by renaming this one. > > Signed-off-by: Richard Henderson > --- > tcg/optimize.c | 142 + > 1 file changed, 72 insertions(+), 70 deletions(-) Reviewed-by: Philipp

Re: [PATCH 06/48] tcg/optimize: Split out init_arguments

On 8/30/21 8:24 AM, Richard Henderson wrote: > There was no real reason for calls to have separate code here. > Unify init for calls vs non-calls using the call path, which > handles TCG_CALL_DUMMY_ARG. > > Signed-off-by: Richard Henderson > --- > tcg/optimize.c | 25 +++-- >

Re: [PATCH v2 10/18] target/arm: Implement MVE FP max/min across vector

On Thu, 26 Aug 2021 at 14:17, Peter Maydell wrote: > > Implement the MVE VMAXNMV, VMINNMV, VMAXNMAV, VMINNMAV insns. These > calculate the maximum or minimum of floating point elements across a > vector, starting with a value in a general purpose register and > returning the result there. > > @@

Re: [PATCH 07/48] tcg/optimize: Split out copy_propagate

On 8/30/21 8:24 AM, Richard Henderson wrote: > Continue splitting tcg_optimize. > > Signed-off-by: Richard Henderson > --- > tcg/optimize.c | 22 ++ > 1 file changed, 14 insertions(+), 8 deletions(-) Reviewed-by: Philippe Mathieu-Daudé

Re: [PATCH 11/48] tcg/optimize: Return true from tcg_opt_gen_{mov,movi}

On 8/30/21 8:24 AM, Richard Henderson wrote: > This will allow callers to tail call to these functions > and return true indicating processing complete. > > Signed-off-by: Richard Henderson > --- > tcg/optimize.c | 9 + > 1 file changed, 5 insertions(+), 4 deletions(-) Reviewed-by: Phil

Re: [PATCH 0/3] Use meson_options.txt in the configure script

On Mon, 30 Aug 2021 at 10:14, Philippe Mathieu-Daudé wrote: > IIRC while Perl is perfect for parsing, the maintenance cost is too > high. The git-forge / meson switch proved next-gen contributors are > more at ease with Python. That seems a bit strong to me. But I would say that for code where mo

Re: [PATCH 13/48] tcg/optimize: Use a boolean to avoid a mass of continues

On 8/30/21 8:24 AM, Richard Henderson wrote: > Signed-off-by: Richard Henderson > --- > tcg/optimize.c | 9 ++--- > 1 file changed, 6 insertions(+), 3 deletions(-) Can we order patches 12 11 13 instead? Reviewed-by: Philippe Mathieu-Daudé

Re: [PATCH 0/2] s390x: ccw: A simple test device for virtio CCW

On 27.08.21 12:50, Pierre Morel wrote: Hello All, This series presents a VIRTIO test device which receives data on its input channel and sends back a simple checksum for the data it received on its output channel. The goal is to allow a simple VIRTIO device driver to check the VIRTIO ini

Re: [PATCH v2 0/5] s390x: CPU Topology

On 26.08.21 11:22, Pierre Morel wrote: a gentle ping :) I would like if you have time, comments on the architecture I propose, if the handling is done at the right level, KVM vs QEMU. Do we expect changes in this series due to the discussed changes of PTF interpretion? Therefor I added

Re: [PATCH v4 00/21] target/riscv: Use tcg_constant_*

On Sat, Aug 21, 2021 at 3:43 AM Richard Henderson wrote: > > Replace use of tcg_const_*, which makes a copy into a temp which must > be freed, with direct use of the constant. Reorg handling of $zero, > with different accessors for source and destination. Reorg handling > of csrs, passing the ac

[PATCH 00/12] mac_via: remove MAC_VIA device and prepare for Nubus IRQs

This is the VIA part of the next set of patches to enable QEMU's q800 machine to boot MacOS. Currently there are 2 separate VIA devices which are contained within a pseudo MAC_VIA device and the main aim of this patchset is to remove it so that the separate VIA1 and VIA2 devices are accessed direc

[PATCH 03/12] mac_via: move PRAM contents and block backend to MOS6522Q800VIA1State

The PRAM contents are accessed using clock and data pins on q800 VIA1 port B and so can be moved to MOS6522Q800VIA1State. Signed-off-by: Mark Cave-Ayland --- hw/misc/mac_via.c | 59 --- include/hw/misc/mac_via.h | 7 +++-- 2 files changed, 34 insertio

[PATCH 01/12] mac_via: introduce new VMStateDescription for q800 VIA1 and VIA2

Move the parent mos6522 objects from vmstate_mac_via into the new VMStateDescription structures to begin the process of splitting MacVIAState into separate VIA1 and VIA2 devices. Signed-off-by: Mark Cave-Ayland --- hw/misc/mac_via.c | 28 1 file changed, 24 insertio

[PATCH 06/12] mac_via: move q800 VIA1 timer variables to q800 VIA1 VMStateDescription

These variables are already present in MOS6522Q800VIA1State and so it is just the VMStateDescription move that is needed. With this change the mac_via VMStateDescription is now empty and can be removed completely. Signed-off-by: Mark Cave-Ayland --- hw/misc/mac_via.c | 20 +---

[PATCH 09/12] mac_via: remove mac_via device

Remove the mac_via device and wire up both q800 VIA1 and VIA2 directly for the m68k q800 machine. Signed-off-by: Mark Cave-Ayland --- hw/m68k/q800.c| 34 + hw/misc/mac_via.c | 78 +++ include/hw/misc/mac_via.h | 21 +++--

[PATCH 05/12] mac_via: move ADB variables to MOS6522Q800VIA1State

The ADB is accessed using clock and data pins on q800 VIA1 port B and so can be moved to MOS6522Q800VIA1State. Signed-off-by: Mark Cave-Ayland --- hw/m68k/q800.c| 6 +- hw/misc/mac_via.c | 169 +++--- include/hw/misc/mac_via.h | 20 ++--- 3

[PATCH 02/12] mac_via: move last_b variable into q800 VIA1 VMStateDescription

This variable is already present in MOS6522Q800VIA1State and can be moved immediately into the q800 VIA1 VMStateDescription. Signed-off-by: Mark Cave-Ayland --- hw/misc/mac_via.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/misc/mac_via.c b/hw/misc/mac_via.c index 46e65

[PATCH 08/12] mac_via: move VIA1 realize logic from mac_via_realize() to mos6522_q800_via1_realize()

Signed-off-by: Mark Cave-Ayland --- hw/misc/mac_via.c | 86 --- 1 file changed, 44 insertions(+), 42 deletions(-) diff --git a/hw/misc/mac_via.c b/hw/misc/mac_via.c index a2df17d9be..bb8d682ce9 100644 --- a/hw/misc/mac_via.c +++ b/hw/misc/mac_via.c @@

[PATCH 10/12] mac_via: remove explicit viaN prefix from VIA IRQ gpios

Now that q800 VIA1 and VIA2 are completely separate devices there is no need to add a specific device prefix to ensure that the IRQ lines remain separate. Signed-off-by: Mark Cave-Ayland --- hw/m68k/q800.c| 10 -- hw/misc/mac_via.c | 9 +++-- 2 files changed, 7 insertions(+), 12

[PATCH 04/12] mac_via: move PRAM/RTC variables to MOS6522Q800VIA1State

The PRAM/RTC is accessed using clock and data pins on q800 VIA1 port B and so can be moved to MOS6522Q800VIA1State. Signed-off-by: Mark Cave-Ayland --- hw/misc/mac_via.c | 135 +++--- include/hw/misc/mac_via.h | 21 +++--- 2 files changed, 77 insertions(+

[PATCH 07/12] mac_via: move VIA1 reset logic from mac_via_reset() to mos6522_q800_via1_reset()

After this change mac_via_reset() is now empty and can be removed. Signed-off-by: Mark Cave-Ayland --- hw/misc/mac_via.c | 22 -- 1 file changed, 8 insertions(+), 14 deletions(-) diff --git a/hw/misc/mac_via.c b/hw/misc/mac_via.c index 47e221dd88..a2df17d9be 100644 --- a/hw/

[PATCH 11/12] mac_via: rename VIA2_IRQ_SLOT_BIT to VIA2_IRQ_NUBUS_BIT

Also improve the alignment of the shifted constants. Signed-off-by: Mark Cave-Ayland --- include/hw/misc/mac_via.h | 22 +++--- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/include/hw/misc/mac_via.h b/include/hw/misc/mac_via.h index 9a8bca056e..5168e3ce66 10064

[PATCH 12/12] mac_via: add qdev gpios for nubus slot interrupts to VIA2

These will soon be required to enable nubus devices to support interrupts. Signed-off-by: Mark Cave-Ayland --- hw/misc/mac_via.c | 23 +++ include/hw/misc/mac_via.h | 10 ++ 2 files changed, 33 insertions(+) diff --git a/hw/misc/mac_via.c b/hw/misc/mac_via.c

[PATCH v7 06/14] target/riscv: Reassign instructions to the Zbs-extension

The following instructions are part of Zbs: - b{set,clr,ext,inv} - b{set,clr,ext,inv}i Signed-off-by: Philipp Tomsich Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- (no changes since v3) Changes in v3: - The changes to the Zbs instructions (i.e. the REQUIRE_ZBS macro) and

[PATCH v7 01/14] target/riscv: Add x-zba, x-zbb, x-zbc and x-zbs properties

The bitmanipulation ISA extensions will be ratified as individual small extension packages instead of a large B-extension. The first new instructions through the door (these have completed public review) are Zb[abcs]. This adds new 'x-zba', 'x-zbb', 'x-zbc' and 'x-zbs' properties for these in tar

[PATCH v7 00/14] target/riscv: Update QEmu for Zb[abcs] 1.0.0

The Zb[abcs] extensions have complete public review and are nearing ratifications. These individual extensions are one part of what was previously though of as the "BitManip" (B) extension, leaving the final details of future Zb* extensions open as they will undergo further public discourse. Thi

[PATCH v7 02/14] target/riscv: Reassign instructions to the Zba-extension

The following instructions are part of Zba: - add.uw (RV64 only) - sh[123]add (RV32 and RV64) - sh[123]add.uw (RV64-only) - slli.uw (RV64-only) Signed-off-by: Philipp Tomsich Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- (no changes since v3) Changes in v3: - The change

[PATCH v7 03/14] target/riscv: slli.uw is only a valid encoding if shamt first in 64 bits

For RV64, the shamt field in slli.uw is 6 bits wide. While the encoding space currently reserves a wider shamt-field (for use is a future RV128 ISA), setting the additional bit to 1 will not map to slli.uw for RV64 and needs to be treated as an illegal instruction. Note that this encoding being re

[PATCH v7 09/14] target/riscv: Add orc.b instruction for Zbb, removing gorc/gorci

The 1.0.0 version of Zbb does not contain gorc/gorci. Instead, a orc.b instruction (equivalent to the orc.b pseudo-instruction built on gorci from pre-0.93 draft-B) is available, mainly targeting string-processing workloads. This commit adds the new orc.b instruction and removed gorc/gorci. Sign

[PATCH v7 08/14] target/riscv: Reassign instructions to the Zbb-extension

This reassigns the instructions that are part of Zbb into it, with the notable exceptions of the instructions (rev8, zext.w and orc.b) that changed due to gorci, grevi and pack not being part of Zb[abcs]. Signed-off-by: Philipp Tomsich Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis

[PATCH v7 04/14] target/riscv: Remove the W-form instructions from Zbs

Zbs 1.0.0 (just as the 0.93 draft-B before) does no provide for W-form instructions for Zbs (single-bit instructions). Remove them. Note that these instructions had already been removed for the 0.93 version of the draft-B extenstion and have not been present in the binutils patches circulating in

[PATCH v7 05/14] target/riscv: Remove shift-one instructions (proposed Zbo in pre-0.93 draft-B)

The Zb[abcs] ratification package does not include the proposed shift-one instructions. There currently is no clear plan to whether these (or variants of them) will be ratified as Zbo (or a different extension) or what the timeframe for such a decision could be. Signed-off-by: Philipp Tomsich Rev

[PATCH v7 14/14] disas/riscv: Add Zb[abcs] instructions

With the addition of Zb[abcs], we also need to add disassembler support for these new instructions. Signed-off-by: Philipp Tomsich --- (no changes since v2) Changes in v2: - Fix missing ';' from last-minute whitespace cleanups. disas/riscv.c | 157

[PATCH v7 10/14] target/riscv: Add a REQUIRE_32BIT macro

With the changes to Zb[abcs], there's some encodings that are different in RV64 and RV32 (e.g., for rev8 and zext.h). For these, we'll need a helper macro allowing us to select on RV32, as well. Signed-off-by: Philipp Tomsich Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- (no

[PATCH v7 11/14] target/riscv: Add rev8 instruction, removing grev/grevi

The 1.0.0 version of Zbb does not contain grev/grevi. Instead, a rev8 instruction (equivalent to the rev8 pseudo-instruction built on grevi from pre-0.93 draft-B) is available. This commit adds the new rev8 instruction and removes grev/grevi. Note that there is no W-form of this instruction (bot

[PATCH v7 07/14] target/riscv: Add instructions of the Zbc-extension

The following instructions are part of Zbc: - clmul - clmulh - clmulr Note that these instructions were already defined in the pre-0.93 and the 0.93 draft-B proposals, but had not been omitted in the earlier addition of draft-B to QEmu. Signed-off-by: Philipp Tomsich Reviewed-by: Richard Hend

[PATCH v7 13/14] target/riscv: Remove RVB (replaced by Zb[abcs]

With everything classified as Zb[abcs] and pre-0.93 draft-B instructions that are not part of Zb[abcs] removed, we can remove the remaining support code for RVB. Note that RVB has been retired for good and misa.B will neither mean 'some' or 'all of' Zb*: https://lists.riscv.org/g/tech-bitmanip/m

[PATCH v7 12/14] target/riscv: Add zext.h instructions to Zbb, removing pack/packu/packh

The 1.0.0 version of Zbb does not contain pack/packu/packh. However, a zext.h instruction is provided (built on pack/packh from pre-0.93 draft-B) is available. This commit adds zext.h and removes the pack* instructions. Note that the encodings for zext.h are different between RV32 and RV64, which

KVM call for agenda for 2021-09-07

Hi Please, send any topic that you are interested in covering. At the end of Monday I will send an email with the agenda or the cancellation of the call, so hurry up. After discussions on the QEMU Summit, we are going to have always open a KVM call where you can add topics. Call details: B

Re: [PATCH v2 0/5] s390x: CPU Topology

On 8/30/21 11:54 AM, Christian Borntraeger wrote: On 26.08.21 11:22, Pierre Morel wrote: a gentle ping :) I would like if you have time, comments on the architecture I propose, if the handling is done at the right level, KVM vs QEMU. Do we expect changes in this series due to the discus

Re: [PATCH 0/2] s390x: ccw: A simple test device for virtio CCW

On 8/30/21 11:51 AM, Christian Borntraeger wrote: On 27.08.21 12:50, Pierre Morel wrote: Hello All, This series presents a VIRTIO test device which receives data on its input channel and sends back a simple checksum for the data it received on its output channel. The goal is to allow a si

Re: [PATCH v2 09/16] PPC64/TCG: Implement 'rfebb' instruction

On 24/08/2021 13:30, Daniel Henrique Barboza wrote: [E-MAIL EXTERNO] Não clique em links ou abra anexos, a menos que você possa confirmar o remetente e saber que o conteúdo é seguro. Em caso de e-mail suspeito entre imediatamente em contato com o DTI. An Event-Based Branch (EBB) allows applica

[PATCH] docs/devel: be consistent about example plugin names

Some plugins were prefixed with `.c`, some were not. Since the name is essentially the full-name of the plugin file, it's logical to include the extension. Signed-off-by: Mahmoud Mandour --- docs/devel/tcg-plugins.rst | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/docs/d

Re: [PULL 5/6] docs: split the CI docs into two files

Hi Thomas, On 8/25/21 1:00 PM, Thomas Huth wrote: > From: Daniel P. Berrangé > > This splits the CI docs into one file talking about job setup and usage > and another file describing provisioning of custom runners. > > Signed-off-by: Daniel P. Berrangé > Reviewed-by: Philippe Mathieu-Daudé >

Re: [PATCH 2/2] docs: add definitions of terms for CI/testing

On 8/20/21 11:09 PM, Willian Rampazzo wrote: > To understand the current state of QEMU CI/testing and have a base to > discuss the plans for the future, it is important to define some usual > terms. This patch defines the terms for "Automated tests", "Unit > testing", "Functional testing", "System

[PATCH v2] Report any problems with loading the VGA driver for Macintosh targets

I was having a problem with missing video resolutions in my Mac OS 9 VM. When I ran QEMU it gave no indication as to why these resolutions were missing. I found out that the OpenFirmware VGA driver was not being loaded. To prevent anyone from going thru the same trouble I went thru I added message

[PATCH] hw/virtio: fix crash on kill then start vhost backend

Add flatview update in vhost_user_cleanup() to avoid access unmapped memory which may cause a qemu crash. Signed-off-by: Yuwei Zhang --- hw/virtio/vhost-user.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/hw/virtio/vhost-user.c b/hw/virtio/vhost-user.c index 2407836fac..b6e76985b7 10064

[PATCH v3 4/5] hw/intc: sifive_plic: Convert the PLIC to use RISC-V CPU GPIO lines

From: Alistair Francis Instead of using riscv_cpu_update_mip() let's instead use the new RISC-V CPU GPIO lines to set the external MIP bits. Signed-off-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Bin Meng Tested-by: Bin Meng --- incl

[PATCH v3 5/5] hw/intc: ibex_timer: Convert the timer to use RISC-V CPU GPIO lines

From: Alistair Francis Instead of using riscv_cpu_update_mip() let's instead use the new RISC-V CPU GPIO lines to set the timer MIP bits. Signed-off-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- include/hw/timer/ibex_timer.h | 2 ++ hw/riscv/ope

[PATCH v3 1/5] target/riscv: Expose interrupt pending bits as GPIO lines

From: Alistair Francis Expose the 12 interrupt pending bits in MIP as GPIO lines. Signed-off-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Bin Meng Tested-by: Bin Meng --- target/riscv/cpu.c | 30 ++ 1 file

[PATCH] hw/virtio: Add flatview update in vhost_user_cleanup()

Qemu will crash on vhost backend unexpected exit and re-connect │ in some case due to access released memory. Signed-off-by: Yuwei Zhang --- hw/virtio/vhost-user.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) d

[PATCH v3 2/5] hw/intc: sifive_clint: Use RISC-V CPU GPIO lines

From: Alistair Francis Instead of using riscv_cpu_update_mip() let's instead use the new RISC-V CPU GPIO lines to set the timer and soft MIP bits. Signed-off-by: Alistair Francis Reviewed-by: Bin Meng Tested-by: Bin Meng Reviewed-by: LIU Zhiwei --- include/hw/intc/sifive_clint.h | 2 + hw/

[PATCH v3 3/5] hw/intc: ibex_plic: Convert the PLIC to use RISC-V CPU GPIO lines

From: Alistair Francis Instead of using riscv_cpu_update_mip() let's instead use the new RISC-V CPU GPIO lines to set the external MIP bits. Signed-off-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- include/hw/intc/ibex_plic.h | 2 ++ hw/intc/ibe

Re: [PATCH 1/2] Use EGL device extension in display initialization.

On Wed, Aug 25, 2021 at 2:22 AM Eugene Huang wrote: > Signed-off-by: Eugene Huang > --- > ui/egl-helpers.c | 41 + > 1 file changed, 37 insertions(+), 4 deletions(-) > > diff --git a/ui/egl-helpers.c b/ui/egl-helpers.c > index 6d0cb2b5cb..ce0971422b 10064

Re: [PATCH v2 01/23] MAINTAINERS: Add Connor Kuehl as reviewer for AMD SEV

On 6/16/21 10:43 PM, Philippe Mathieu-Daudé wrote: > From: Connor Kuehl > > It may not be appropriate for me to take over as a maintainer at this time, > but I would consider myself familiar with AMD SEV and what this code is > meant to be doing as part of a VMM for launching SEV-protected guests

Re: [PATCH v2 01/23] MAINTAINERS: Add Connor Kuehl as reviewer for AMD SEV

On 8/30/21 9:18 AM, Philippe Mathieu-Daudé wrote: >> >> +AMD Secure Encrypted Virtualization (SEV) >> +R: Connor Kuehl > > Is this patch still valid? Thank you for championing it, but due to recent changes, no, it is no longer valid. Thank you, Connor

Re: [PATCH 1/3] configure: Add the possibility to read options from meson_options.txt

On Sun, Aug 29, 2021 at 07:32:08PM +0200, Thomas Huth wrote: > To avoid double maintenance between the configure script and > meson_options.txt, add some simple logic in the configure script > to read the options from meson_options.txt. > > Signed-off-by: Thomas Huth > --- > configure | 24 +

Re: [PATCH 2/3] configure: Remove options that can be handled via meson_options.txt instead

On Sun, Aug 29, 2021 at 07:32:09PM +0200, Thomas Huth wrote: > These trivial options can now be handled via the new generic code > that parses meson_options.txt > > Signed-off-by: Thomas Huth > --- > configure | 316 +- > meson_options.txt |

Re: [PATCH v2 02/23] qapi/misc-target: Wrap long 'SEV Attestation Report' long lines

Philippe Mathieu-Daudé writes: > Wrap long lines before 70 characters for legibility. > > Suggested-by: Markus Armbruster > Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Markus Armbruster > --- > Note: it would be nice if checkpatch enforce 70 char for json > (or at least QAPI jso

Re: [PATCH v2 02/23] qapi/misc-target: Wrap long 'SEV Attestation Report' long lines

Markus Armbruster writes: > Philippe Mathieu-Daudé writes: > >> Wrap long lines before 70 characters for legibility. >> >> Suggested-by: Markus Armbruster >> Signed-off-by: Philippe Mathieu-Daudé > > Reviewed-by: Markus Armbruster With the typo spotted by Dave fixed, of course. > >> --- >>

Re: [PATCH v2 03/23] qapi/misc-target: Group SEV QAPI definitions

Philippe Mathieu-Daudé writes: > There is already a section with various SEV commands / types, > so move the SEV guest attestation together. > > Signed-off-by: Philippe Mathieu-Daudé > --- > qapi/misc-target.json | 81 +-- > 1 file changed, 40 insertions(

Re: [PATCH v4 00/21] target/riscv: Use tcg_constant_*

On 8/30/21 3:12 AM, Alistair Francis wrote: On Sat, Aug 21, 2021 at 3:43 AM Richard Henderson wrote: Replace use of tcg_const_*, which makes a copy into a temp which must be freed, with direct use of the constant. Reorg handling of $zero, with different accessors for source and destination.

Re: [PATCH 3/3] configure: Get help text from meson_options.txt

On Sun, Aug 29, 2021 at 07:32:10PM +0200, Thomas Huth wrote: > It's cumbersome to maintain the option help texts twice, once in the > "configure" script and once in meson_options.txt. So let's add some logic to > the configure script to read most of the help texts from meson_options.txt. > > Signe

Re: [PATCH 2/3] configure: Remove options that can be handled via meson_options.txt instead

On 8/30/21 8:06 AM, Eric Blake wrote: Does meson treat -Dbrlapi=auto and the absence of any mention of brlapi identically? I believe the default is right there in meson_options.txt: option('brlapi', type : 'feature', value : 'auto', description: 'brlapi character device driver') with v

block/curl: should we be checking curl_easy_setopt() for errors?

Coverity complains (CID 1460331, 1459482, 1459336, 1458895) that we call curl_easy_setopt(), which can return an error value, but we never check the return value. Is it correct? Looking at the libcurl documentation, the function does return an error status, and there's nothing that says it's ok to

Re: [PULL 8/9] qapi: introduce forwarding visitor

On Mon, 9 Aug 2021 at 11:40, Peter Maydell wrote: > > On Sat, 24 Jul 2021 at 10:00, Paolo Bonzini wrote: > > > > This new adaptor visitor takes a single field of the adaptee, and exposes it > > with a different name. > > > > This will be used for QOM alias properties. Alias targets can of course

Re: [PATCH v8 0/3] Add support for ipv6 host forwarding

Ping. On Fri, Aug 13, 2021 at 4:44 PM Doug Evans wrote: > This patchset takes the original patch from Maxim, > https://www.mail-archive.com/qemu-devel@nongnu.org/msg569573.html > and updates it. > > Option hostfwd is extended to support ipv6 addresses. > Commands hostfwd_add, hostfwd_remove are

Re: QEMU-KVM offers OPAL firmware interface? OpenBSD guest support?

On Mon, 30 Aug 2021, David Gibson wrote: On Sun, Aug 29, 2021 at 04:09:54AM +, Joseph wrote: Hi Mark, Cédric, Greg at the openbsd-ppc ML, It is great to talk to you. Thank you for taking on the conversation. Right, OpenBSD implements powernv meaning it runs on bare metal on Power9, that is

Re: [PATCH v0] kvm: unsigned datatype in ioctl wrapper

On Sun, Aug 29, 2021 at 10:09:19PM +0100, Peter Maydell wrote: > On Thu, 5 Aug 2021 at 21:34, johannst wrote: > > > > Dear all, > > > > in my opinion the `type` argument in the kvm ioctl wrappers should be of > > type unsigned. Please correct me if I am wrong. > > (Ccing Eric as our resident POSI

9pfs: Twalk crash

Apparently commit 8d6cb100731c4d28535adbf2a3c2d1f29be3fef4 '9pfs: reduce latency of Twalk' has introduced occasional crashes. My first impression after looking at the backtrace: looks like the patch itself is probably not causing this, but rather unmasked this issue (i.e. increased the chance t

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