On 8/23/21 11:11 AM, Philipp Tomsich wrote:
+/* ... then shift the result 1 bit to the right. */
+TCGv dst = tcg_temp_new();
+gen_get_gpr(dst, a->rd);
+tcg_gen_shri_tl(dst, dst, 1);
+gen_set_gpr(a->rd, dst);
+tcg_temp_free(dst);
Missed review changes from v3:
static voi
+Markus
On Thu, Aug 19, 2021 at 07:15:46PM +0200, Philippe Mathieu-Daudé wrote:
> Do not ignore eventual error if we failed at setting the 'host'
> property of the TYPE_XHCI model.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> hw/usb/hcd-xhci-pci.c | 2 +-
> 1 file changed, 1 insertion(+),
On Mon, Aug 23, 2021 at 06:41:55PM +0200, Philippe Mathieu-Daudé wrote:
> +/* Permission to restrict bus memory accesses. See MemTxAttrs::bus_perm */
> +enum {
> +MEMTXPERM_UNSPECIFIED = 0,
> +MEMTXPERM_UNRESTRICTED = 1,
> +MEMTXPERM_RAM_DEVICE= 2,
> +};
Is there a difference be
The bitmanipulation ISA extensions will be ratified as individual
small extension packages instead of a large B-extension. The first
new instructions through the door (these have completed public review)
are Zb[abcs].
This adds new 'x-zba', 'x-zbb', 'x-zbc' and 'x-zbs' properties for
these in tar
The Zb[abcs] ratification package does not include the proposed
shift-one instructions. There currently is no clear plan to whether
these (or variants of them) will be ratified as Zbo (or a different
extension) or what the timeframe for such a decision could be.
Signed-off-by: Philipp Tomsich
Rev
The Zb[abcs] extensions have complete public review and are nearing
ratifications. These individual extensions are one part of what was
previously though of as the "BitManip" (B) extension, leaving the
final details of future Zb* extensions open as they will undergo
further public discourse.
Thi
With the changes to Zb[abcs], there's some encodings that are
different in RV64 and RV32 (e.g., for rev8 and zext.h). For these,
we'll need a helper macro allowing us to select on RV32, as well.
Signed-off-by: Philipp Tomsich
Reviewed-by: Richard Henderson
---
(no changes since v3)
Changes in
Zbs 1.0.0 (just as the 0.93 draft-B before) does no provide for W-form
instructions for Zbs (single-bit instructions). Remove them.
Note that these instructions had already been removed for the 0.93
version of the draft-B extenstion and have not been present in the
binutils patches circulating in
For RV64, the shamt field in slli.uw is 6 bits wide. While the encoding
space currently reserves a wider shamt-field (for use is a future RV128
ISA), setting the additional bit to 1 will not map to slli.uw for RV64
and needs to be treated as an illegal instruction.
Note that this encoding being re
The following instructions are part of Zbs:
- b{set,clr,ext,inv}
- b{set,clr,ext,inv}i
Signed-off-by: Philipp Tomsich
Reviewed-by: Richard Henderson
---
(no changes since v3)
Changes in v3:
- The changes to the Zbs instructions (i.e. the REQUIRE_ZBS macro) and
its use for qualifying the Zb
With everything classified as Zb[abcs] and pre-0.93 draft-B
instructions that are not part of Zb[abcs] removed, we can remove the
remaining support code for RVB.
Note that RVB has been retired for good and misa.B will neither mean
'some' or 'all of' Zb*:
https://lists.riscv.org/g/tech-bitmanip/m
The following instructions are part of Zba:
- add.uw (RV64 only)
- sh[123]add (RV32 and RV64)
- sh[123]add.uw (RV64-only)
- slli.uw (RV64-only)
Signed-off-by: Philipp Tomsich
Reviewed-by: Richard Henderson
---
(no changes since v3)
Changes in v3:
- The changes to the Zba instructions (i.e.
The following instructions are part of Zbc:
- clmul
- clmulh
- clmulr
Note that these instructions were already defined in the pre-0.93 and
the 0.93 draft-B proposals, but had not been omitted in the earlier
addition of draft-B to QEmu.
Signed-off-by: Philipp Tomsich
---
Changes in v5:
- Int
The 1.0.0 version of Zbb does not contain pack/packu/packh. However, a
zext.h instruction is provided (built on pack/packh from pre-0.93
draft-B) is available.
This commit adds zext.h and removes the pack* instructions.
Note that the encodings for zext.h are different between RV32 and
RV64, which
The 1.0.0 version of Zbb does not contain grev/grevi. Instead, a
rev8 instruction (equivalent to the rev8 pseudo-instruction built on
grevi from pre-0.93 draft-B) is available.
This commit adds the new rev8 instruction and removes grev/grevi.
Note that there is no W-form of this instruction (bot
On Mon, Aug 23, 2021 at 06:41:56PM +0200, Philippe Mathieu-Daudé wrote:
> Introduce flatview_access_allowed() to check bus permission
> before running any bus transaction. For now this is a simple
> stub.
>
> Signed-off-by: Philippe Mathieu-Daudé
Shall we squash this patch into the next one? It
This reassigns the instructions that are part of Zbb into it, with the
notable exceptions of the instructions (rev8, zext.w and orc.b) that
changed due to gorci, grevi and pack not being part of Zb[abcs].
Signed-off-by: Philipp Tomsich
Reviewed-by: Richard Henderson
---
(no changes since v3)
C
On Mon, Aug 23, 2021 at 06:41:53PM +0200, Philippe Mathieu-Daudé wrote:
> Remove unuseful local 'result' variables.
>
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Peter Xu
--
Peter Xu
The 1.0.0 version of Zbb does not contain gorc/gorci. Instead, a
orc.b instruction (equivalent to the orc.b pseudo-instruction built on
gorci from pre-0.93 draft-B) is available, mainly targeting
string-processing workloads.
This commit adds the new orc.b instruction and removed gorc/gorci.
Sign
On Mon, Aug 23, 2021 at 06:41:57PM +0200, Philippe Mathieu-Daudé wrote:
> @@ -2772,7 +2772,22 @@ static inline bool
> flatview_access_allowed(MemoryRegion *mr, MemTxAttrs attrs,
> hwaddr addr, hwaddr len,
> Mem
With the addition of Zb[abcs], we also need to add disassembler
support for these new instructions.
Signed-off-by: Philipp Tomsich
---
(no changes since v2)
Changes in v2:
- Fix missing ';' from last-minute whitespace cleanups.
disas/riscv.c | 157
On Wed, Aug 18, 2021 at 03:43:18PM -0400, Peter Xu wrote:
> QEMU creates -device objects in order as specified by the user's cmdline.
> However that ordering may not be the ideal order. For example, some platform
> devices (vIOMMUs) may want to be created earlier than most of the rest
> devices (e
On Mon, Aug 23, 2021 at 06:41:54PM +0200, Philippe Mathieu-Daudé wrote:
> We are going to introduce more MemTxResult bits, so it is
> safer to check for !MEMTX_OK rather than MEMTX_ERROR.
>
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Peter Xu
--
Peter Xu
On 23.08.21 18:41, Philippe Mathieu-Daudé wrote:
Remove unuseful local 'result' variables.
Signed-off-by: Philippe Mathieu-Daudé
---
Reviewed-by: David Hildenbrand
--
Thanks,
David / dhildenb
On Mon, Aug 23, 2021 at 12:31 PM G S Niteesh Babu
wrote:
> Added AQMP TUI.
>
> Implements the follwing basic features:
> 1) Command transmission/reception.
> 2) Shows events asynchronously.
> 3) Shows server status in the bottom status bar.
> 4) Automatic retries on disconnects and error conditio
On 23.08.21 18:41, Philippe Mathieu-Daudé wrote:
We are going to introduce more MemTxResult bits, so it is
safer to check for !MEMTX_OK rather than MEMTX_ERROR.
Signed-off-by: Philippe Mathieu-Daudé
---
Reviewed-by: David Hildenbrand
--
Thanks,
David / dhildenb
On 23.08.21 20:43, Peter Xu wrote:
On Mon, Aug 23, 2021 at 06:41:56PM +0200, Philippe Mathieu-Daudé wrote:
Introduce flatview_access_allowed() to check bus permission
before running any bus transaction. For now this is a simple
stub.
Signed-off-by: Philippe Mathieu-Daudé
Shall we squash this
On 23.08.21 20:41, Peter Xu wrote:
On Mon, Aug 23, 2021 at 06:41:55PM +0200, Philippe Mathieu-Daudé wrote:
+/* Permission to restrict bus memory accesses. See MemTxAttrs::bus_perm */
+enum {
+MEMTXPERM_UNSPECIFIED = 0,
+MEMTXPERM_UNRESTRICTED = 1,
+MEMTXPERM_RAM_DEVICE= 2,
+};
On Mon, 23 Aug 2021 at 17:42, Philippe Mathieu-Daudé wrote:
>
> We are going to introduce more MemTxResult bits, so it is
> safer to check for !MEMTX_OK rather than MEMTX_ERROR.
>
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Peter Maydell
but note that these MEMTX_* aren't from the mem
On 23.08.21 18:41, Philippe Mathieu-Daudé wrote:
Check bus permission in flatview_access_allowed() before
running any bus transaction.
There is not change for the default case (MEMTXPERM_UNSPECIFIED).
s/not/no/
The MEMTXPERM_UNRESTRICTED case works as an allow list. Devices
using it won't b
On Mon, 23 Aug 2021 at 17:42, Philippe Mathieu-Daudé wrote:
>
> This series aim to kill a recent class of bug, the infamous
> "DMA reentrancy" issues found by Alexander while fuzzing.
>
> Introduce the 'bus_perm' field in MemTxAttrs, defining 3 bits:
>
> - MEMTXPERM_UNSPECIFIED (current default, u
On Mon, Aug 23, 2021 at 02:49:12PM -0400, Eduardo Habkost wrote:
> On Wed, Aug 18, 2021 at 03:43:18PM -0400, Peter Xu wrote:
> > QEMU creates -device objects in order as specified by the user's cmdline.
> > However that ordering may not be the ideal order. For example, some
> > platform
> > devic
On 23.08.21 12:34, Philippe Mathieu-Daudé wrote:
On 8/23/21 12:24 PM, David Hildenbrand wrote:
On 23.08.21 12:12, Philippe Mathieu-Daudé wrote:
On 8/23/21 11:29 AM, David Hildenbrand wrote:
On 23.08.21 11:23, Peter Maydell wrote:
On Mon, 23 Aug 2021 at 09:40, David Hildenbrand
wrote:
Not op
On 8/10/2021 1:06 PM, Alex Williamson wrote:
> On Fri, 6 Aug 2021 14:43:53 -0700
> Steve Sistare wrote:
>
>> Enable vfio-pci devices to be saved and restored across an exec restart
>> of qemu.
>>
>> At vfio creation time, save the value of vfio container, group, and device
>> descriptors in cpr
On Sun, Aug 22, 2021 at 10:18 PM Peter Maydell wrote:
>
> On Sun, 22 Aug 2021 at 15:37, Gautam Bhat wrote:
> >
> > Hi,
> >
> > I am to implement a very simple microcontroller for my understanding
> > of Qemu development. This microcontroller runs its code from
> > programmable flash which is bit-
On 8/22/21 9:54 PM, Bin Meng wrote:
On Sat, Aug 21, 2021 at 1:43 AM Richard Henderson
wrote:
Introduce csrr and csrw helpers, for read-only and write-only insns.
Note that we do not properly implement this in riscv_csrrw, in that
we cannot distinguish true read-only (rs1 == 0) from any other
Replace use of tcg_const_*, which makes a copy into a temp which must
be freed, with direct use of the constant. Reorg handling of $zero,
with different accessors for source and destination. Reorg handling
of csrs, passing the actual write_mask instead of a regno. Use more
helpers for RVH expans
Replace uses of tcg_const_* with the allocate and free close together.
Reviewed-by: Bin Meng
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
Signed-off-by: Richard Henderson
---
target/riscv/translate.c| 36 --
target/riscv/insn_trans/trans_rvf.c.
Introduce get_gpr, dest_gpr, temp_new -- new helpers that do not force
tcg globals into temps, returning a constant 0 for $zero as source and
a new temp for $zero as destination.
Introduce ctx->w for simplifying word operations, such as addw.
Reviewed-by: Bin Meng
Reviewed-by: Alistair Francis
Utilize the condition in the movcond more; this allows some of
the setcond that were feeding into movcond to be removed.
Do not write into source1 and source2. Re-name "condN" to "tempN"
and use the temporaries for more than holding conditions.
Tested-by: Bin Meng
Reviewed-by: Bin Meng
Reviewed
Tested-by: Bin Meng
Reviewed-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Richard Henderson
---
tests/tcg/riscv64/test-div.c | 58 +++
tests/tcg/riscv64/Makefile.target | 5 +++
2 files changed, 63 insertions(+)
create mode 100644 tests/tcg/riscv
We will require the context to handle RV64 word operations.
Reviewed-by: Alistair Francis
Reviewed-by: Bin Meng
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/riscv/translate.c| 58 -
target/riscv/insn_trans/trans_rva.c.
Use ctx->w and the enhanced gen_arith function.
Reviewed-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Richard Henderson
---
target/riscv/translate.c| 42 -
target/riscv/insn_trans/trans_rvm.c.inc | 16 +-
2 files changed, 8 insertion
These operations are greatly simplified by ctx->w, which allows
us to fold gen_shiftw into gen_shift. Split gen_shifti into
gen_shift_imm_{fn,tl} like we do for gen_arith_imm_{fn,tl}.
Reviewed-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Richard Henderson
---
target/riscv/transla
Split out gen_mulh and gen_mulhu and use the common helper.
Reviewed-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Richard Henderson
---
target/riscv/insn_trans/trans_rvm.c.inc | 40 +++--
1 file changed, 18 insertions(+), 22 deletions(-)
diff --git a/target/ri
Reviewed-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Richard Henderson
---
target/riscv/insn_trans/trans_rvi.c.inc | 36 +
1 file changed, 19 insertions(+), 17 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc
b/target/riscv/insn_trans/tra
Most arithmetic does not require extending the inputs.
Exceptions include division, comparison and minmax.
Begin using ctx->w, which allows elimination of gen_addw,
gen_subw, gen_mulw.
Reviewed-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Richard Henderson
---
target/riscv/transl
We distinguish write-only by passing ret_value as NULL.
Signed-off-by: Richard Henderson
---
target/riscv/csr.c | 23 +++
1 file changed, 15 insertions(+), 8 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 9a4ed18ac5..d900f96dc1 100644
--- a/target/ri
Use ctx->w for ctpopw, which is the only one that can
re-use the generic algorithm for the narrow operation.
Reviewed-by: Alistair Francis
Signed-off-by: Richard Henderson
---
target/riscv/translate.c| 14 ++
target/riscv/insn_trans/trans_rvb.c.inc | 24 +
Move these helpers near their use by the trans_*
functions within insn_trans/trans_rvb.c.inc.
Reviewed-by: Bin Meng
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
Signed-off-by: Richard Henderson
---
target/riscv/translate.c| 233 ---
tar
Narrow the scope of t0 in trans_jalr.
Reviewed-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Richard Henderson
---
target/riscv/insn_trans/trans_rvi.c.inc | 25 ++---
1 file changed, 10 insertions(+), 15 deletions(-)
diff --git a/target/riscv/insn_trans/trans_r
Reviewed-by: Bin Meng
Signed-off-by: Richard Henderson
---
target/riscv/insn_trans/trans_rvf.c.inc | 146
1 file changed, 70 insertions(+), 76 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvf.c.inc
b/target/riscv/insn_trans/trans_rvf.c.inc
index fb9f7f9c00..
Move these helpers near their use by the trans_*
functions within insn_trans/trans_rvm.c.inc.
Reviewed-by: Bin Meng
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
Signed-off-by: Richard Henderson
---
target/riscv/translate.c| 127
ta
Exit early if check_access fails.
Split out do_hlv, do_hsv, do_hlvx subroutines.
Use dest_gpr, get_gpr in the new subroutines.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/riscv/insn32.decode | 1 +
target/riscv/insn_trans/trans_rvh.c.inc | 266
These operations can be done in one instruction on some hosts.
Signed-off-by: Richard Henderson
---
target/riscv/insn_trans/trans_rvi.c.inc | 14 --
1 file changed, 12 insertions(+), 2 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc
b/target/riscv/insn_trans/trans
We failed to write into *val for these read functions;
replace them with read_zero. Only warn about unsupported
non-zero value when writing a non-zero value.
Signed-off-by: Richard Henderson
---
target/riscv/csr.c | 26 --
1 file changed, 8 insertions(+), 18 deletions(-)
Reviewed-by: Bin Meng
Signed-off-by: Richard Henderson
---
target/riscv/insn_trans/trans_rva.c.inc | 47 ++---
1 file changed, 19 insertions(+), 28 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rva.c.inc
b/target/riscv/insn_trans/trans_rva.c.inc
index 3cc3c3b073..
Always use tcg_gen_deposit_z_tl; the special case for
shamt >= 32 is handled there.
Signed-off-by: Richard Henderson
---
target/riscv/insn_trans/trans_rvb.c.inc | 19 ++-
1 file changed, 6 insertions(+), 13 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc
b/tar
Introduce csrr and csrw helpers, for read-only and write-only insns.
Note that we do not properly implement this in riscv_csrrw, in that
we cannot distinguish true read-only (rs1 == 0) from any other zero
write_mask another source register -- this should still raise an
exception for read-only regi
Reviewed-by: Bin Meng
Signed-off-by: Richard Henderson
---
target/riscv/insn_trans/trans_rvd.c.inc | 125
1 file changed, 60 insertions(+), 65 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvd.c.inc
b/target/riscv/insn_trans/trans_rvd.c.inc
index 11b9b3f90b..
Remove gen_get_gpr, as the function becomes unused.
Signed-off-by: Richard Henderson
---
target/riscv/translate.c| 13 ++---
target/riscv/insn_trans/trans_rvv.c.inc | 74 +++--
2 files changed, 26 insertions(+), 61 deletions(-)
diff --git a/target/riscv/trans
On Mon, Aug 23, 2021 at 08:10:50PM +0100, Peter Maydell wrote:
> On Mon, 23 Aug 2021 at 17:42, Philippe Mathieu-Daudé
> wrote:
> >
> > This series aim to kill a recent class of bug, the infamous
> > "DMA reentrancy" issues found by Alexander while fuzzing.
> >
> > Introduce the 'bus_perm' field i
On Mon, Aug 23, 2021 at 03:18:51PM -0400, Peter Xu wrote:
> On Mon, Aug 23, 2021 at 02:49:12PM -0400, Eduardo Habkost wrote:
> > On Wed, Aug 18, 2021 at 03:43:18PM -0400, Peter Xu wrote:
> > > QEMU creates -device objects in order as specified by the user's cmdline.
> > > However that ordering may
On Mon, Aug 23, 2021 at 05:07:03PM -0400, Eduardo Habkost wrote:
> To give just one example:
>
> $ (echo 'info pci';echo quit;) | qemu-system-x86_64 -device virtio-net-pci
> -device e1000e -monitor stdio | tail -n 20
> Bus 0, device 4, function 0:
> Ethernet controller: PCI device 1af4:1
Hi Zheng, testing aarch64 is on our todo list. We will run this case and try to
reproduce the failure. Thanks for the report.
- Steve
On 8/21/2021 4:54 AM, Zheng Chuan wrote:
> Hi, steve
>
> It seems the VM will stuck after cpr-load on AArch64 environment？
>
> My AArch64 environment and test
On Mon, Aug 23, 2021 at 05:31:46PM -0400, Peter Xu wrote:
> On Mon, Aug 23, 2021 at 05:07:03PM -0400, Eduardo Habkost wrote:
> > To give just one example:
> >
> > $ (echo 'info pci';echo quit;) | qemu-system-x86_64 -device virtio-net-pci
> > -device e1000e -monitor stdio | tail -n 20
> > Bus 0
On Mon, Aug 23, 2021 at 05:31:46PM -0400, Peter Xu wrote:
> On Mon, Aug 23, 2021 at 05:07:03PM -0400, Eduardo Habkost wrote:
> > To give just one example:
> >
> > $ (echo 'info pci';echo quit;) | qemu-system-x86_64 -device virtio-net-pci
> > -device e1000e -monitor stdio | tail -n 20
> > Bus 0
On Mon, Aug 23, 2021 at 03:18:51PM -0400, Peter Xu wrote:
> On Mon, Aug 23, 2021 at 02:49:12PM -0400, Eduardo Habkost wrote:
> > On Wed, Aug 18, 2021 at 03:43:18PM -0400, Peter Xu wrote:
> > > QEMU creates -device objects in order as specified by the user's cmdline.
> > > However that ordering may
On 210823 1650, Peter Xu wrote:
> On Mon, Aug 23, 2021 at 08:10:50PM +0100, Peter Maydell wrote:
> > On Mon, 23 Aug 2021 at 17:42, Philippe Mathieu-Daudé
> > wrote:
> > >
> > > This series aim to kill a recent class of bug, the infamous
> > > "DMA reentrancy" issues found by Alexander while fuzzi
Add syntax highlighting for the incoming and outgoing QMP messages.
This is achieved using the pygments module which was added in a
previous commit.
The current implementation is a really simple one which doesn't
allow for any configuration. In future this has to be improved
to allow for easier th
Added dependencies for the upcoming AQMP TUI under the optional
'tui' group.
The same dependencies have also been added under the devel group
since no work around has been found for optional groups to imply
other optional groups.
Signed-off-by: G S Niteesh Babu
---
python/Pipfile.lock | 12
On Mon, Aug 23, 2021 at 06:05:07PM -0400, Michael S. Tsirkin wrote:
> On Mon, Aug 23, 2021 at 03:18:51PM -0400, Peter Xu wrote:
> > On Mon, Aug 23, 2021 at 02:49:12PM -0400, Eduardo Habkost wrote:
> > > On Wed, Aug 18, 2021 at 03:43:18PM -0400, Peter Xu wrote:
> > > > QEMU creates -device objects i
Added pygments as optional dependency for AQMP TUI.
This is required for the upcoming syntax highlighting feature
in AQMP TUI.
The dependency has also been added in the devel optional group.
Added mypy 'ignore_missing_imports' for pygments since it does
not have any type stubs.
Signed-off-by: G S
Add an entry point for aqmp-tui. This will allow it to be run from
the command line using "aqmp-tui localhost:1234"
More options available in the TUI can be found using "aqmp-tui -h"
Signed-off-by: G S Niteesh Babu
---
python/setup.cfg | 1 +
1 file changed, 1 insertion(+)
diff --git a/python/s
Added AQMP TUI.
Implements the follwing basic features:
1) Command transmission/reception.
2) Shows events asynchronously.
3) Shows server status in the bottom status bar.
4) Automatic retries on disconnects and error conditions.
Also added type annotations and necessary pylint/mypy configuration
Gitlab: https://gitlab.com/niteesh.gs/qemu/-/commits/aqmp-tui-prototype-v6
Based-on: <20210803182941.504537-1-js...@redhat.com> [v3,00/25] python:
introduce Asynchronous QMP package
CI: https://gitlab.com/niteesh.gs/qemu/-/pipelines/358117062
Updates since v5:
1) Moved all docstrings under init t
On Mon, Aug 23, 2021 at 05:21:07PM +0200, Philippe Mathieu-Daudé wrote:
> On 8/23/21 4:20 PM, Changbin Du wrote:
> > To resolve the issue to debug switchable targets, this serias introduces
> > basic infrastructure for gdbstub and enable support for ARM and RISC-V
> > targets.
> >
> > For example,
On Tue, Aug 24, 2021 at 4:12 AM Philipp Tomsich
wrote:
>
> The bitmanipulation ISA extensions will be ratified as individual
> small extension packages instead of a large B-extension. The first
> new instructions through the door (these have completed public review)
> are Zb[abcs].
>
> This adds
On Mon, Aug 23, 2021 at 05:54:44PM -0400, Michael S. Tsirkin wrote:
> > I can use a custom sort to replace qsort() to guarantee that.
> You don't have to do that. Simply use the device position on the command
> line for comparisons when priority is the same.
Indeed. :) Thanks,
--
Peter Xu
On Mon, Aug 23, 2021 at 05:56:23PM -0400, Eduardo Habkost wrote:
> I don't have any other example, but I assume address assignment
> based on ordering is a common pattern in device code.
>
> I would take a very close and careful look at the devices with
> non-default vmsd priority. If you can pro
On Sat, Aug 21, 2021 at 08:35:35PM +0530, Ani Sinha wrote:
> Bsel property of the pci bus indicates whether the bus supports acpi hotplug.
> We need to validate the presence of this property before performing any
> hotplug
> related callback operations. Currently validation of the existence of thi
On Mon, Aug 23, 2021 at 04:30:05PM +0100, Peter Maydell wrote:
> On Mon, 23 Aug 2021 at 16:21, Philippe Mathieu-Daudé
> wrote:
> >
> > On 8/23/21 4:20 PM, Changbin Du wrote:
> > > To resolve the issue to debug switchable targets, this serias introduces
> > > basic infrastructure for gdbstub and e
On Mon, Aug 09, 2021 at 07:13:42PM +0200, Laurent Vivier wrote:
> If the guest driver doesn't support the STANDBY feature, by default
> we keep the virtio-net device and don't hotplug the VFIO device,
> but in some cases, user can prefer to use the VFIO device rather
> than the virtio-net one. We c
On Thu, Aug 05, 2021 at 08:39:21PM +0800, Yanan Wang wrote:
> From: Andrew Jones
>
> Add the Processor Properties Topology Table (PPTT) to expose
> CPU topology information defined by users to ACPI guests.
>
> Note, a DT-boot Linux guest with a non-flat CPU topology will
> see socket and core ID
On Thu, Aug 05, 2021 at 08:39:16PM +0800, Yanan Wang wrote:
> Hi,
>
> This is a new version (v5) of the series [1] that I posted to introduce
> support for generating cpu topology descriptions to virt machine guest.
>
> Once the view of an accurate virtual cpu topology is provided to guest,
> wit
On Mon, Aug 23, 2021 at 02:20:18PM +0200, Klaus Jensen wrote:
> From: Klaus Jensen
>
> Address 0x0 is a valid address. Fix the admin submission and completion
> queue address validation to not error out on this.
Indeed, there are environments that can use that address. It's a host error if
the c
From: LCM
. Add sid-map property to store non PCI/PCIe devices SID
. Create IOMMU memory regions for non PCI/PCIe devices based on their SID
. Update SID getting strategy for PCI/PCIe and non PCI/PCIe devices
Signed-off-by: Chunming Li
Signed-off-by: Renwei Liu
---
hw/arm/smmuv3.c
From: LCM
"smmu_iommu_mr" function can't get MR according to SID for non PCI/PCIe devices.
So we replace "smmuv3_flush_config" with "g_hash_table_foreach_remove" based on
devices SID.
Signed-off-by: Chunming Li
Signed-off-by: Renwei Liu
---
hw/arm/smmuv3.c | 35 ++---
From: LCM
. Add sid-map property to store non PCI/PCIe devices SID
. Create IOMMU memory regions for non PCI/PCIe devices based on their SID
. Update SID getting strategy for PCI/PCIe and non PCI/PCIe devices
Signed-off-by: Chunming Li
Signed-off-by: Renwei Liu
---
hw/arm/smmuv3.c
From: LCM
Add PL330 DMA controller to test SMMU v3 connection and function.
The default SID for PL330 is 1 but we test other values, it works well.
Signed-off-by: Chunming Li
Signed-off-by: Renwei Liu
---
hw/arm/virt.c | 92 ++-
include/hw/arm/v
On Tue, Aug 24, 2021 at 3:18 AM Peter Xu wrote:
>
> On Mon, Aug 23, 2021 at 02:49:12PM -0400, Eduardo Habkost wrote:
> > On Wed, Aug 18, 2021 at 03:43:18PM -0400, Peter Xu wrote:
> > > QEMU creates -device objects in order as specified by the user's cmdline.
> > > However that ordering may not be
On Tue, Aug 24, 2021 at 6:37 AM Peter Xu wrote:
>
> On Mon, Aug 23, 2021 at 06:05:07PM -0400, Michael S. Tsirkin wrote:
> > On Mon, Aug 23, 2021 at 03:18:51PM -0400, Peter Xu wrote:
> > > On Mon, Aug 23, 2021 at 02:49:12PM -0400, Eduardo Habkost wrote:
> > > > On Wed, Aug 18, 2021 at 03:43:18PM -0
On 2021/8/24 7:53, Michael S. Tsirkin wrote:
On Thu, Aug 05, 2021 at 08:39:16PM +0800, Yanan Wang wrote:
Hi,
This is a new version (v5) of the series [1] that I posted to introduce
support for generating cpu topology descriptions to virt machine guest.
Once the view of an accurate virtual cp
On 2021/8/24 7:52, Michael S. Tsirkin wrote:
On Thu, Aug 05, 2021 at 08:39:21PM +0800, Yanan Wang wrote:
From: Andrew Jones
Add the Processor Properties Topology Table (PPTT) to expose
CPU topology information defined by users to ACPI guests.
Note, a DT-boot Linux guest with a non-flat CPU
On 2021/8/23 21:17, Philippe Mathieu-Daudé wrote:
On 8/23/21 2:27 PM, Yanan Wang wrote:
We have two requirements for a valid SMP configuration:
the product of "sockets * cores * threads" must represent all the
possible cpus, i.e., max_cpus, and then must include the initially
present cpus, i.e
Thomas Huth writes:
> On 14/08/2021 01.36, Jose R. Ziviani wrote:
>> If users try to add an isa-vga device that was already registered,
>> still in command line, qemu will crash:
>> $ qemu-system-mips64el -M pica61 -device isa-vga
>> RAMBlock "vga.vram" already registered, abort!
>> Aborted (core
On Mon, 23 Aug 2021, Michael S. Tsirkin wrote:
> On Sat, Aug 21, 2021 at 08:35:35PM +0530, Ani Sinha wrote:
> > Bsel property of the pci bus indicates whether the bus supports acpi
> > hotplug.
> > We need to validate the presence of this property before performing any
> > hotplug
> > related
On Aug 23 19:47, Keith Busch wrote:
> On Mon, Aug 23, 2021 at 02:20:18PM +0200, Klaus Jensen wrote:
> > From: Klaus Jensen
> >
> > Address 0x0 is a valid address. Fix the admin submission and completion
> > queue address validation to not error out on this.
>
> Indeed, there are environments tha
Peter Maydell writes:
> On Thu, 19 Aug 2021 at 09:54, Daniel P. Berrangé wrote:
>> We've especially not had "how many users
>> are there" as a criteria for acceptance or removal of a device.
>
> ...not least because we have no accurate way to determine
> the answer to that question!
I'd like to
Daniel P. Berrangé writes:
> On Wed, Aug 18, 2021 at 03:42:23PM +0200, Thomas Huth wrote:
>>
>> Hi all,
>>
>> I recently noticed that we have quite a bunch of tickets against the vmxnet3
>> device in our bug trackers, which indicate that this device could be used to
>> crash QEMU in various wa
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