Re: [PATCH v3 00/16] tcg/mips: Unaligned access and other cleanup

Hi, Jiaxun, I'm not familiar with TCG, please review, thanks. Huacai On Thu, Aug 19, 2021 at 6:09 AM Philippe Mathieu-Daudé wrote: > > Sorry, use Huacai's newer email . > > On Thu, Aug 19, 2021 at 12:07 AM Philippe Mathieu-Daudé > wrote: > > > > Cc'ing Jiaxun & Huacai. > > > > On 8/18/21 10:1

qemu-devel@nongnu.org

On 8/20/21 8:07 AM, Gerd Hoffmann wrote: > Hi, > >> This also seems to me to be the tail wagging the dog. If we think >> 'info mtree' has too much duplicate information (which it certainly >> does) then we should make mtree_info() smarter about reducing that >> duplication. Off the top of my hea

Re: [PATCH 3/4] target/arm/cpu64: Replace kvm_supported with sve_vq_supported

On 8/19/21 9:37 PM, Andrew Jones wrote: > Now that we have an ARMCPU member sve_vq_supported we no longer > need the local kvm_supported bitmap for KVM's supported vector > lengths. > > Signed-off-by: Andrew Jones > --- > target/arm/cpu64.c | 19 +++ > 1 file changed, 11 insertio

Re: [PATCH 4/7] hw/adc: Make adci[*] R/W in NPCM7XX ADC

On 8/14/21 1:33 AM, Hao Wu wrote: > Our sensor test requires both reading and writing from a sensor's > QOM property. So we need to make the input of ADC module R/W instead > of read only for that to work. > > Signed-off-by: Hao Wu > Reviewed-by: Titus Rwantare > --- > hw/adc/npcm7xx_adc.c | 2

Re: [PATCH] hw/arm/smmuv3: Support non-PCI/PCIe devices connection

On 8/20/21 4:36 AM, Li, Chunming wrote: > The current SMMU V3 device model only support PCI/PCIe devices, > so we update it to support non-PCI/PCIe devices. > > hw/arm/smmuv3: > . Create IOMMU memory regions for non-PCI/PCIe devices based on their > SID > . Add sid-map propert

RE: [PATCH] hw/arm/smmuv3: Support non-PCI/PCIe devices connection

> On 8/20/21 4:36 AM, Li, Chunming wrote: > > The current SMMU V3 device model only support PCI/PCIe devices, > > so we update it to support non-PCI/PCIe devices. > > > > hw/arm/smmuv3: > > . Create IOMMU memory regions for non-PCI/PCIe devices based > on their SID > > . Add si

Re: [qemu-web PATCH] Add a blog post about FUSE block exports

On 19.08.21 18:23, Stefan Hajnoczi wrote: On Thu, Aug 19, 2021 at 12:25:01PM +0200, Hanna Reitz wrote: This post explains when FUSE block exports are useful, how they work, and that it is fun to export an image file on its own path so it looks like your image file (in whatever format it was) is

Re: [PATCH] hw/arm/smmuv3: Support non-PCI/PCIe devices connection

On 8/20/21 9:42 AM, Li, Chunming wrote: > >> On 8/20/21 4:36 AM, Li, Chunming wrote: >>> The current SMMU V3 device model only support PCI/PCIe devices, >>> so we update it to support non-PCI/PCIe devices. >>> >>> hw/arm/smmuv3: >>> . Create IOMMU memory regions for non-PCI/PCIe device

[PATCH] .mailmap: Fix more contributor entries

These authors have some incorrect author email field. For each of them, there is one commit with the replaced entry. Cc: Alex Chen Cc: Bibo Mao Cc: Guoyi Tu Cc: Haibin Zhang Cc: Hyman Huang Cc: Lichang Zhao Cc: Yuanjun Gong Signed-off-by: Philippe Mathieu-Daudé --- If you are Cc'ed and agr

[PATCH v2] hw/arm/smmuv3: Support non-PCI/PCIe devices connection

The current SMMU V3 device model only support PCI/PCIe devices, so we update it to support non-PCI/PCIe devices. hw/arm/smmuv3: . Create IOMMU memory regions for non-PCI/PCIe devices based on their SID . Add sid-map property to store non-PCI/PCIe devices SID . Update i

Re: [PATCH] .mailmap: Fix more contributor entries

On 2021/8/20 16:04, Philippe Mathieu-Daudé wrote: > These authors have some incorrect author email field. > For each of them, there is one commit with the replaced > entry. > > Cc: Alex Chen > Cc: Bibo Mao > Cc: Guoyi Tu > Cc: Haibin Zhang > Cc: Hyman Huang > Cc: Lichang Zhao > Cc: Yuanjun G

Re: [PATCH] hw/arm/smmuv3: Support non-PCI/PCIe devices connection

On Fri, 20 Aug 2021 at 03:36, Li, Chunming wrote: > > The current SMMU V3 device model only support PCI/PCIe devices, > so we update it to support non-PCI/PCIe devices. > > hw/arm/smmuv3: > . Create IOMMU memory regions for non-PCI/PCIe devices based on their > SID > . Add sid

Re: [PATCH] .mailmap: Fix more contributor entries

On Fri, Aug 20, 2021 at 10:25 AM Hyman Huang wrote: > 在 2021/8/20 16:04, Philippe Mathieu-Daudé 写道: > > These authors have some incorrect author email field. > > For each of them, there is one commit with the replaced > > entry. > > > > Cc: Alex Chen > > Cc: Bibo Mao > > Cc: Guoyi Tu > > Cc: Ha

Re: [PATCH v2 3/4] hw/dma/xlnx_csu_dma: Always expect 'dma' link property to be set

On Thu, 19 Aug 2021 at 17:34, Philippe Mathieu-Daudé wrote: > > Simplify by always passing a MemoryRegion property to the device. > Doing so we can move the AddressSpace field to the device struct, > removing need for heap allocation. > > Update the Xilinx ZynqMP SoC model to pass the default syst

Re: [PATCH v2 4/4] hw/dma/xlnx-zdma Always expect 'dma' link property to be set

On Thu, 19 Aug 2021 at 17:34, Philippe Mathieu-Daudé wrote: > > Simplify by always passing a MemoryRegion property to the device. > Doing so we can move the AddressSpace field to the device struct, > removing need for heap allocation. > > Update the Xilinx ZynqMP / Versal SoC models to pass the de

Re: [qemu-web PATCH] Add a blog post about FUSE block exports

On 19.08.21 20:22, Klaus Kiwi wrote: On Thu, Aug 19, 2021 at 7:27 AM Hanna Reitz > wrote: This post explains when FUSE block exports are useful, how they work, and that it is fun to export an image file on its own path so it looks like your image file (in

RE: [PATCH] hw/arm/smmuv3: Support non-PCI/PCIe devices connection

> On Fri, 20 Aug 2021 at 03:36, Li, Chunming > wrote: > > > > The current SMMU V3 device model only support PCI/PCIe devices, > > so we update it to support non-PCI/PCIe devices. > > > > hw/arm/smmuv3: > > . Create IOMMU memory regions for non-PCI/PCIe devices based > on their SID > >

Re: [PATCH] hw/arm/smmuv3: Support non-PCI/PCIe devices connection

On Fri, 20 Aug 2021 at 10:04, Li, Chunming wrote: > > > On Fri, 20 Aug 2021 at 03:36, Li, Chunming > > wrote: > > > > > > The current SMMU V3 device model only support PCI/PCIe devices, > > > so we update it to support non-PCI/PCIe devices. > > > > > > hw/arm/smmuv3: > > > . Create IO

Re: [qemu-web PATCH] Add a blog post about FUSE block exports

On Fri, Aug 20, 2021 at 09:56:54AM +0200, Hanna Reitz wrote: > On 19.08.21 18:23, Stefan Hajnoczi wrote: > > On Thu, Aug 19, 2021 at 12:25:01PM +0200, Hanna Reitz wrote: > > > This post explains when FUSE block exports are useful, how they work, > > > and that it is fun to export an image file on i

RE: [PATCH RFC v6 08/12] target/riscv: Handle KVM_EXIT_RISCV_SBI exit

> -Original Message- > From: Qemu-riscv > [mailto:qemu-riscv-bounces+jiangyifei=huawei@nongnu.org] On Behalf Of > Alistair Francis > Sent: Thursday, August 19, 2021 2:14 PM > To: Jiangyifei > Cc: Anup Patel ; open list:RISC-V > ; open list:Overall ; > limingwang (A) ; libvir-l...@redh

Re: [PATCH v3 53/66] target/alpha: Reorg integer memory operations

On Wed, 18 Aug 2021 at 21:11, Richard Henderson wrote: > > Pass in the MemOp instead of a callback. > Drop the fp argument; add a locked argument. > > Signed-off-by: Richard Henderson > --- > target/alpha/translate.c | 104 +++ > 1 file changed, 40 insertions(

Re: [PATCH v3 59/66] accel/tcg: Handle SIGBUS in handle_cpu_signal

On Wed, 18 Aug 2021 at 21:13, Richard Henderson wrote: > > We've been registering host SIGBUS, but then treating it > exactly like SIGSEGV. > > Handle BUS_ADRALN via cpu_unaligned_access, but allow other > SIGBUS si_codes to continue into the host-to-guest signal > coversion code in host_signal_ha

Re: [PATCH v3 60/66] tcg/aarch64: Support raising sigbus for user-only

On Wed, 18 Aug 2021 at 20:56, Richard Henderson wrote: > > Use load-acquire / store-release for the normal case of > alignment matching the access size. Otherwise, emit a > test + branch sequence invoking helper_unaligned_mmu. I don't think this trick will work for a CPU that implements the FEAT

Re: [PATCH v3 61/66] tcg/ppc: Support raising sigbus for user-only

On Wed, 18 Aug 2021 at 20:46, Richard Henderson wrote: > > Signed-off-by: Richard Henderson > --- > tcg/ppc/tcg-target.h | 2 - > tcg/ppc/tcg-target.c.inc | 102 --- > 2 files changed, 94 insertions(+), 10 deletions(-) > Reviewed-by: Peter Maydell tha

Re: [PATCH v3 62/66] tcg/s390: Support raising sigbus for user-only

On Wed, 18 Aug 2021 at 20:49, Richard Henderson wrote: > > Signed-off-by: Richard Henderson > --- > tcg/s390/tcg-target.h | 2 -- > tcg/s390/tcg-target.c.inc | 63 +-- > 2 files changed, 61 insertions(+), 4 deletions(-) Reviewed-by: Peter Maydell thank

Re: [PATCH v3 63/66] tcg/tci: Support raising sigbus for user-only

On Wed, 18 Aug 2021 at 21:15, Richard Henderson wrote: > > Signed-off-by: Richard Henderson > --- > tcg/tci.c | 18 +- > 1 file changed, 13 insertions(+), 5 deletions(-) > > diff --git a/tcg/tci.c b/tcg/tci.c > index e76087ccac..985c8a91cb 100644 > --- a/tcg/tci.c > +++ b/tcg/tci

Re: [PATCH 2/2] docs/about: Unify the subject format

On Fri, Aug 20 2021, Yanan Wang wrote: > Unify the subject format in deprecated.rst to "since X.Y". > Unify the subject format in removed-features.rst to "removed in X.Y". It seems unlikely that we will ever deprecate something in a stable release, and even more unlikely that we'll remove someth

Re: [PATCH 1/2] hw/9pfs: avoid 'path' copy in v9fs_walk()

On Tue, 17 Aug 2021 14:38:24 +0200 Christian Schoenebeck wrote: > The v9fs_walk() function resolves all client submitted path nodes to the > local 'pathes' array. Using a separate string scalar variable 'path' > inside the background worker thread loop and copying that local 'path' > string scala

Re: [PATCH v3 01/14] tcg/arm: Remove fallback definition of __ARM_ARCH

On Wed, 18 Aug 2021 at 22:32, Richard Henderson wrote: > > GCC since 4.8 provides the definition and we now require 7.5. > > Signed-off-by: Richard Henderson I assume clang provides this too... Reviewed-by: Peter Maydell thanks -- PMM

Re: [PATCH 2/2] hw/9pfs: use g_autofree in v9fs_walk() where possible

On Tue, 17 Aug 2021 15:46:50 +0200 Christian Schoenebeck wrote: > Suggested-by: Greg Kurz > Signed-off-by: Christian Schoenebeck > --- > hw/9pfs/9p.c | 7 +++ > 1 file changed, 3 insertions(+), 4 deletions(-) > > diff --git a/hw/9pfs/9p.c b/hw/9pfs/9p.c > index 4d642ab12a..c857b31321 1006

Re: [PATCH v3 02/14] tcg/arm: Standardize on tcg_out__{reg, imm}

On Wed, 18 Aug 2021 at 22:41, Richard Henderson wrote: > > Some of the functions specified _reg, some _imm, and some > left it blank. Make it clearer to which we are referring. > > Split tcg_out_b_reg from tcg_out_bx_reg, to indicate when > we do not actually require BX semantics. > > Signed-off-

Re: [PATCH v3 04/14] tcg/arm: Support armv4t in tcg_out_goto and tcg_out_call

On Wed, 18 Aug 2021 at 22:38, Richard Henderson wrote: > > ARMv4T has BX as its only interworking instruction. In order > to support testing of different architecture revisions with a > qemu binary that may have been built for, say ARMv6T2, fill in > the blank required to make calls to helpers in

[PATCH] memory: Have 'info mtree' remove duplicated Address Space information

Per Peter Maydell [*]: 'info mtree' monitor command was designed on the assumption that there's really only one or two interesting address spaces, and with more recent developments that's just not the case any more. Similarly about how the FlatView are sorted using a GHashTable, sort the Ad

Re: [PATCH] memory: Have 'info mtree' remove duplicated Address Space information

On 8/20/21 12:54 PM, Philippe Mathieu-Daudé wrote: > Per Peter Maydell [*]: > > 'info mtree' monitor command was designed on the assumption that > there's really only one or two interesting address spaces, and > with more recent developments that's just not the case any more. > > Similarly

Re: [PATCH v3 03/14] tcg/arm: Simplify use_armvt5_instructions

On Wed, 18 Aug 2021 at 22:32, Richard Henderson wrote: > > According to the Arm ARM DDI 0406C, section A1.3, the valid variants > are ARMv5T, ARMv5TE, ARMv5TEJ -- there is no ARMv5 without Thumb. > Therefore simplify the test from preprocessor ifdefs to base > architecture revision. Retain the "t

Re: [PATCH v3 05/14] tcg/arm: Examine QEMU_TCG_DEBUG environment variable

On Wed, 18 Aug 2021 at 22:42, Richard Henderson wrote: > > Use the environment variable to test an older ISA from > the one supported by the host. > > Signed-off-by: Richard Henderson I think we should document this environment variable somewhere... > +/* > + * For debugging/testing p

Re: [PATCH 2/3] qcow2: refactor handle_dependencies() loop body

On 24.07.21 15:38, Vladimir Sementsov-Ogievskiy wrote: No logic change, just prepare for the following commit. Signed-off-by: Vladimir Sementsov-Ogievskiy --- block/qcow2-cluster.c | 49 --- 1 file changed, 28 insertions(+), 21 deletions(-) Reviewed-

Re: [PATCH 0/1] uas: add stream number sanity checks (maybe 6.1)

On 8/18/21 2:05 PM, Gerd Hoffmann wrote: > Security fix. Sorry for the last-minute patch, I had completely > forgotten this one until the CVE number for it arrived today. > > Given that the classic usb storage device is way more popular than > the uas (usb attached scsi) device the impact should

Re: [PATCH v3 07/14] tcg/arm: Split out tcg_out_ldstm

On Wed, 18 Aug 2021 at 22:36, Richard Henderson wrote: > > Expand these hard-coded instructions symbolically. > > Signed-off-by: Richard Henderson > --- > tcg/arm/tcg-target.c.inc | 19 +-- > 1 file changed, 17 insertions(+), 2 deletions(-) Reviewed-by: Peter Maydell thanks --

Re: [PATCH v3 08/14] tcg/arm: Simplify usage of encode_imm

On Wed, 18 Aug 2021 at 22:38, Richard Henderson wrote: > > We have already computed the rotated value of the imm8 > portion of the complete imm12 encoding. No sense leaving > the combination of rot + rotation to the caller. > > Create an encode_imm12_nofail helper that performs an assert. > > Thi

Re: [PATCH v3 13/14] tcg/arm: Reserve a register for guest_base

On Wed, 18 Aug 2021 at 22:33, Richard Henderson wrote: > > Reserve a register for the guest_base using aarch64 for reference. > By doing so, we do not have to recompute it for every memory load. > > Signed-off-by: Richard Henderson > --- > tcg/arm/tcg-target.c.inc | 39 ++

Re: [Patch 1/2] hw/arm/xlnx-versal: Add unimplemented APU mmio

On Wed, Aug 18, 2021 at 08:15:24PM -0700, Tong Ho wrote: > Add unimplemented APU mmio region to xlnx-versal for booting > bare-metal guests built with standalone bsp published at: > > https://github.com/Xilinx/embeddedsw/tree/master/lib/bsp/standalone/src/arm/ARMv8/64bit Reviewed-by: Edgar E.

Re: [PATCH 0/1] uas: add stream number sanity checks (maybe 6.1)

On Wed, 18 Aug 2021 at 13:10, Gerd Hoffmann wrote: > > Security fix. Sorry for the last-minute patch, I had completely > forgotten this one until the CVE number for it arrived today. > > Given that the classic usb storage device is way more popular than > the uas (usb attached scsi) device the im

Re: [PATCH 1/2] hw/9pfs: avoid 'path' copy in v9fs_walk()

On Freitag, 20. August 2021 12:35:49 CEST Greg Kurz wrote: > On Tue, 17 Aug 2021 14:38:24 +0200 > > Christian Schoenebeck wrote: > > The v9fs_walk() function resolves all client submitted path nodes to the > > local 'pathes' array. Using a separate string scalar variable 'path' > > inside the bac

Re: [Patch 2/2] hw/arm/xlnx-zynqmp: Add unimplemented APU mmio

On Wed, Aug 18, 2021 at 08:15:25PM -0700, Tong Ho wrote: > Add unimplemented APU mmio region to xlnx-zynqmp for booting > bare-metal guests built with standalone bsp published at: > > https://github.com/Xilinx/embeddedsw/tree/master/lib/bsp/standalone/src/arm/ARMv8/64bit > > Signed-off-by: Tong

Re: [PATCH 2/2] hw/9pfs: use g_autofree in v9fs_walk() where possible

On Freitag, 20. August 2021 12:40:31 CEST Greg Kurz wrote: > On Tue, 17 Aug 2021 15:46:50 +0200 > > Christian Schoenebeck wrote: > > Suggested-by: Greg Kurz > > Signed-off-by: Christian Schoenebeck > > --- > > > > hw/9pfs/9p.c | 7 +++ > > 1 file changed, 3 insertions(+), 4 deletions(-) >

Re: [PATCH 2/2] hw/9pfs: use g_autofree in v9fs_walk() where possible

On Fri, 20 Aug 2021 14:23:26 +0200 Christian Schoenebeck wrote: > On Freitag, 20. August 2021 12:40:31 CEST Greg Kurz wrote: > > On Tue, 17 Aug 2021 15:46:50 +0200 > > > > Christian Schoenebeck wrote: > > > Suggested-by: Greg Kurz > > > Signed-off-by: Christian Schoenebeck > > > --- > > > >

Re: [PATCH 2/2] hw/9pfs: use g_autofree in v9fs_walk() where possible

On Freitag, 20. August 2021 14:34:11 CEST Greg Kurz wrote: > On Fri, 20 Aug 2021 14:23:26 +0200 > > Christian Schoenebeck wrote: > > On Freitag, 20. August 2021 12:40:31 CEST Greg Kurz wrote: > > > On Tue, 17 Aug 2021 15:46:50 +0200 > > > > > > Christian Schoenebeck wrote: > > > > Suggested-by:

Re: [PATCH 0/1] uas: add stream number sanity checks (maybe 6.1)

Cc'ing Mauro to double-check. On 8/20/21 2:12 PM, Peter Maydell wrote: > On Wed, 18 Aug 2021 at 13:10, Gerd Hoffmann wrote: >> >> Security fix. Sorry for the last-minute patch, I had completely >> forgotten this one until the CVE number for it arrived today. >> >> Given that the classic usb stor

Re: [Patch 1/2] hw/arm/xlnx-versal: Add unimplemented APU mmio

On 8/19/21 5:15 AM, Tong Ho wrote: > Add unimplemented APU mmio region to xlnx-versal for booting > bare-metal guests built with standalone bsp published at: > > https://github.com/Xilinx/embeddedsw/tree/master/lib/bsp/standalone/src/arm/ARMv8/64bit This link is not very useful. This one is: h

Re: [Patch 2/2] hw/arm/xlnx-zynqmp: Add unimplemented APU mmio

On 8/19/21 5:15 AM, Tong Ho wrote: > Add unimplemented APU mmio region to xlnx-zynqmp for booting > bare-metal guests built with standalone bsp published at: > > https://github.com/Xilinx/embeddedsw/tree/master/lib/bsp/standalone/src/arm/ARMv8/64bit Again, please point to something more useful:

Re: [PATCH 3/3] qcow2: handle_dependencies(): relax conflict detection

On 24.07.21 15:38, Vladimir Sementsov-Ogievskiy wrote: There is no conflict and no dependency if we have parallel writes to different subclusters of one cluster when cluster itself is already allocated. So, relax extra dependency. Measure performance: First, prepare build/qemu-img-old and build/

Re: [PATCH v3 06/14] tcg/arm: Support unaligned access for softmmu

On Wed, 18 Aug 2021 at 22:32, Richard Henderson wrote: > > From armv6, the architecture supports unaligned accesses. > All we need to do is perform the correct alignment check > in tcg_out_tlb_read and not use LDRD/STRD when the access > is not aligned. > > Signed-off-by: Richard Henderson > @@ -

Re: [PATCH 01/26] ppc: Add a POWER10 DD2 CPU

On Mon, 9 Aug 2021 15:45:22 +0200 Cédric Le Goater wrote: > The POWER10 DD2 CPU adds an extra LPCR[HAIL] bit. DD1 doesn't have > HAIL but since it does not break the modeling and that we don't plan > to support DD1, modify the LPCR mask of all the POWER10 family. > Maybe consider dropping DD1 a

Re: [PATCH 02/26] ppc/pnv: Change the POWER10 machine to support DD2 only

On Mon, 9 Aug 2021 15:45:23 +0200 Cédric Le Goater wrote: > There is no need to keep the DD1 chip model as it will never be > publicly available. > > Signed-off-by: Cédric Le Goater > --- Reviewed-by: Greg Kurz > include/hw/ppc/pnv.h | 2 +- > hw/ppc/pnv.c | 2 +- > hw/ppc/pnv_core.

Re: [PATCH 04/26] ppc/pnv: Use a simple incrementing index for the chip-id

On Mon, 9 Aug 2021 15:45:25 +0200 Cédric Le Goater wrote: > When the QEMU PowerNV machine was introduced, multi chip support > modeled a two socket system with dual chip modules as found on some P8 > Tuleta systems (8286-42A). But this is hardly used and not relevant > for QEMU. Use a simple inde

Re: [PATCH v3 14/14] tcg/arm: Support raising sigbus for user-only

On Wed, 18 Aug 2021 at 22:43, Richard Henderson wrote: > > For v6+, use ldm/stm, ldrd/strd for the normal case of alignment > matching the access size. Otherwise, emit a test + branch sequence > invoking helper_unaligned_{ld,st}. > > For v4+v5, use piecewise load and stores to implement misalignm

xilinx-zynq-a9: cannot set up guest memory 'zynq.ext_ram'

Hi, The following command used to work on QEMU 4.2.0, but is now broken with QEMU head. $ qemu-system-arm -M xilinx-zynq-a9 -display none -m 4000 -nographic -serial /dev/null -serial mon:stdio -monitor null -device loader,file=u-boot-dtb.bin,addr=0x400,cpu-num=0 qemu-system-arm: cannot se

Re: [PATCH 05/26] ppc/pnv: Distribute RAM among the chips

On Mon, 9 Aug 2021 15:45:26 +0200 Cédric Le Goater wrote: > But always give the first 1GB to chip 0 as skiboot requires it. > > Signed-off-by: Cédric Le Goater > --- > hw/ppc/pnv.c | 33 + > 1 file changed, 25 insertions(+), 8 deletions(-) > > diff --git a/hw/p

Re: xilinx-zynq-a9: cannot set up guest memory 'zynq.ext_ram'

Hi Bin, On 8/20/21 4:04 PM, Bin Meng wrote: > Hi, > > The following command used to work on QEMU 4.2.0, but is now broken > with QEMU head. > > $ qemu-system-arm -M xilinx-zynq-a9 -display none -m 4000 > -nographic -serial /dev/null -serial mon:stdio -monitor null -device > loader,file=u-boo

Re: [PATCH 06/26] ppc/pnv: add a chip topology index for POWER10

On Mon, 9 Aug 2021 15:45:27 +0200 Cédric Le Goater wrote: > Signed-off-by: Cédric Le Goater Maybe add a short description of its purpose in the changelog for the records ? What's the difference with "ibm,chip-id" ? > --- > hw/ppc/pnv_xscom.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff

[PATCH 3/4] target/i386: Added ignore TPR check in ctl_has_irq

The APM2 states that if V_IGN_TPR is nonzero, the current virtual interrupt ignores the (virtual) TPR. Signed-off-by: Lara Lazier --- target/i386/tcg/sysemu/svm_helper.c | 5 + 1 file changed, 5 insertions(+) diff --git a/target/i386/tcg/sysemu/svm_helper.c b/target/i386/tcg/sysemu/svm_hel

[PATCH 2/4] target/i386: Added VGIF V_IRQ masking capability

VGIF provides masking capability for when virtual interrupts are taken. (APM2) Signed-off-by: Lara Lazier --- target/i386/cpu.c | 7 +-- target/i386/cpu.h | 2 ++ target/i386/tcg/sysemu/svm_helper.c | 12 3 files changed, 19 insertions(+), 2

[PATCH 0/4] target/i386: V_IRQ masking and V_TPR fixes

Patch 2 adds VGIF capability to mask virtual interrupts. Patches 3 and 4 fix bugs related to vTPR, while patch 1 refactors int_ctl into the state structure to simplify the fixes in the following patches. Lara Lazier (4): target/i386: Moved int_ctl into CPUX86State structure target/i386: Added

[PATCH 1/4] target/i386: Moved int_ctl into CPUX86State structure

Moved int_ctl into the CPUX86State structure to remove some unnecessary stores and loads. Signed-off-by: Lara Lazier --- slirp| 2 +- target/i386/cpu.c| 2 +- target/i386/cpu.h| 1 + target/i386/machine.c|

[RFC PATCH v2 7/8] pci: automatically unplug a PCI card before migration

We have moved all the functions needed by failover to unplug a card to the PCI subsystem. A side effect of this change is we can implement automatic hotplug/unplug of any PCI card during migration without using a failover virtio-net card. For that, we need to introduce a new PCI device property, "

[RFC PATCH v2 1/8] qdev: add an Error parameter to the DeviceListener hide_device() function

This allows an error to be reported to the caller of qdev_device_add() Signed-off-by: Laurent Vivier --- include/hw/qdev-core.h | 6 -- hw/core/qdev.c | 4 ++-- hw/net/virtio-net.c| 2 +- softmmu/qdev-monitor.c | 4 ++-- 4 files changed, 9 insertions(+), 7 deletions(-) diff --gi

[RFC PATCH v2 4/8] failover: pci: move failover hotplug/unplug code into pci subsystem

failover allows a VFIO device to be unplugged on migration to switch to the standby device, a virtio-net device. Failover relies on PCI ability to hotplug/unplug a card (the VFIO one) but all the code is implemented in virtio-net device that is not a PCI device (even not in virtio-net-pci that is

[PATCH 4/4] target/i386: Added changed priority check for VIRQ

Writes to cr8 affect v_tpr. This could set or unset an interrupt request as the priority might have changed. Signed-off-by: Lara Lazier --- target/i386/cpu.h| 15 +++ target/i386/tcg/sysemu/misc_helper.c | 7 +++ target/i386/tcg/sysemu/svm_helper.c | 15

[RFC PATCH v2 5/8] failover: hide the PCI device if the virtio-net device is not present

We can plug either the virtio-net device first or the PCI device first. If we plug the PCI device first, QEMU checks the failover_pair_id but doesn't hide the device if the virtio-net device is not present. This is a problem because if the virtio-net device is not plugged and the machine is migra

[RFC PATCH v2 8/8] failover: qemu-opts: manage hidden device list

failover relies on the command line parameters to store and detect failover devices because while the device is hidden it doesn't appears in qdev objects and so we don't have the list anywhere else. But this doesn't work if the the device is hotplugged because it is not added to the qemu opts list

[RFC PATCH v2 0/8] virtio-net failover cleanup and new features

v2: add helpers to manage the list of hidden devices rather than relying on the command line parameters Hide VFIO device if it is plugged before the virtio-net one This series moves the code used by virtio-net failover from the virtio-net device to the PCI subsystem. Doing that, we can us

Re: xilinx-zynq-a9: cannot set up guest memory 'zynq.ext_ram'

Hi Philippe, On Fri, Aug 20, 2021 at 10:10 PM Philippe Mathieu-Daudé wrote: > > Hi Bin, > > On 8/20/21 4:04 PM, Bin Meng wrote: > > Hi, > > > > The following command used to work on QEMU 4.2.0, but is now broken > > with QEMU head. > > > > $ qemu-system-arm -M xilinx-zynq-a9 -display none -m 4000

[RFC PATCH v2 2/8] qdev/qbus: remove failover specific code

Commit f3a850565693 ("qdev/qbus: add hidden device support") has introduced a generic way to hide a device but it has modified qdev_device_add() to check a specific option of the failover device, "failover_pair_id", before calling the generic mechanism. It's not needed (and not generic) to do that

Re: [qemu-web PATCH] Add a blog post about FUSE block exports

On Fri, Aug 20, 2021 at 09:56:54AM +0200, Hanna Reitz wrote: > On 19.08.21 18:23, Stefan Hajnoczi wrote: > > On Thu, Aug 19, 2021 at 12:25:01PM +0200, Hanna Reitz wrote: > > > This post explains when FUSE block exports are useful, how they work, > > > and that it is fun to export an image file on i

[RFC PATCH v2 3/8] failover: virtio-net: remove failover_primary_hidden flag

We dont't need a flag to know if the primary device must be hidden, we can rely on the machine state: Device is hidden if the machine is in prelaunch state (src) or in inmigrate state with migration status set to none (dst). We don't need to check the flag in virtio_net_handle_migration_primary() b

Re: [PATCH 0/2] 9pfs: v9fs_walk() cleanup

On Dienstag, 17. August 2021 15:52:39 CEST Christian Schoenebeck wrote: > Few cleanup patches for function v9fs_walk() as discussed last month. > > In patch 2 array variables 'wnames' and 'pathes' are omitted because they > contain dynamically allocated memory per array element which need to be >

[RFC PATCH v2 6/8] failover: pci: unregister ROM on unplug

The intend of failover is to allow a VM with a VFIO networking card to be migrated without disrupting the network operation by switching to a virtio-net device during the migration. This simple change allows a simulated device like e1000e to be tested rather than a vfio device, even if it's useles

Re: xilinx-zynq-a9: cannot set up guest memory 'zynq.ext_ram'

On 20.08.21 16:22, Bin Meng wrote: Hi Philippe, On Fri, Aug 20, 2021 at 10:10 PM Philippe Mathieu-Daudé wrote: Hi Bin, On 8/20/21 4:04 PM, Bin Meng wrote: Hi, The following command used to work on QEMU 4.2.0, but is now broken with QEMU head. $ qemu-system-arm -M xilinx-zynq-a9 -display n

Re: xilinx-zynq-a9: cannot set up guest memory 'zynq.ext_ram'

On Fri, 20 Aug 2021 at 15:34, David Hildenbrand wrote: > > On 20.08.21 16:22, Bin Meng wrote: > > Hi Philippe, > > > > On Fri, Aug 20, 2021 at 10:10 PM Philippe Mathieu-Daudé > > wrote: > >> > >> Hi Bin, > >> > >> On 8/20/21 4:04 PM, Bin Meng wrote: > >>> Hi, > >>> > >>> The following command use

Re: xilinx-zynq-a9: cannot set up guest memory 'zynq.ext_ram'

On 8/20/21 4:39 PM, Peter Maydell wrote: > On Fri, 20 Aug 2021 at 15:34, David Hildenbrand wrote: >> >> On 20.08.21 16:22, Bin Meng wrote: >>> Hi Philippe, >>> >>> On Fri, Aug 20, 2021 at 10:10 PM Philippe Mathieu-Daudé >>> wrote: Hi Bin, On 8/20/21 4:04 PM, Bin Meng wrote: >>

Re: xilinx-zynq-a9: cannot set up guest memory 'zynq.ext_ram'

On Fri, 20 Aug 2021 15:39:27 +0100 Peter Maydell wrote: > On Fri, 20 Aug 2021 at 15:34, David Hildenbrand wrote: > > > > On 20.08.21 16:22, Bin Meng wrote: > > > Hi Philippe, > > > > > > On Fri, Aug 20, 2021 at 10:10 PM Philippe Mathieu-Daudé > > > wrote: > > >> > > >> Hi Bin, > > >> > > >>

Re: [PATCH] hw/acpi: refactor acpi hp modules so that targets can just use what they need

On Thu, 19 Aug 2021, Philippe Mathieu-Daudé wrote: > On 8/12/21 9:14 AM, Ani Sinha wrote: > > +return; > > I suppose if you replace all 'return' by 'g_assert_not_reached()' > both issues reproducers crash? > > Your patch is not incorrect, and indeed fixes the issues, but > I feel we are goi

Re: xilinx-zynq-a9: cannot set up guest memory 'zynq.ext_ram'

On 20.08.21 17:44, Igor Mammedov wrote: On Fri, 20 Aug 2021 15:39:27 +0100 Peter Maydell wrote: On Fri, 20 Aug 2021 at 15:34, David Hildenbrand wrote: On 20.08.21 16:22, Bin Meng wrote: Hi Philippe, On Fri, Aug 20, 2021 at 10:10 PM Philippe Mathieu-Daudé wrote: Hi Bin, On 8/20/21 4:04

[PATCH] softmmu/physmem: Improve guest memory allocation failure error message

When Linux refuses to overcommit a seriously wild allocation we get: $ qemu-system-i386 -m 4000 qemu-system-i386: cannot set up guest memory 'pc.ram': Cannot allocate memory Slighly improve the error message, displaying the memory size requested (in case the user didn't expect unspecified

Re: [PATCH] softmmu/physmem: Improve guest memory allocation failure error message

On 20.08.21 17:52, Philippe Mathieu-Daudé wrote: When Linux refuses to overcommit a seriously wild allocation we get: $ qemu-system-i386 -m 4000 qemu-system-i386: cannot set up guest memory 'pc.ram': Cannot allocate memory Slighly improve the error message, displaying the memory size

Re: xilinx-zynq-a9: cannot set up guest memory 'zynq.ext_ram'

On 8/20/21 5:47 PM, David Hildenbrand wrote: > On 20.08.21 17:44, Igor Mammedov wrote: >> On Fri, 20 Aug 2021 15:39:27 +0100 >> Peter Maydell wrote: >> >>> On Fri, 20 Aug 2021 at 15:34, David Hildenbrand >>> wrote: On 20.08.21 16:22, Bin Meng wrote: > Hi Philippe, > > On Fri

Re: [PATCH] hw/acpi: refactor acpi hp modules so that targets can just use what they need

On 8/20/21 5:43 PM, Ani Sinha wrote: > On Thu, 19 Aug 2021, Philippe Mathieu-Daudé wrote: >> On 8/12/21 9:14 AM, Ani Sinha wrote: > >>> +return; >> >> I suppose if you replace all 'return' by 'g_assert_not_reached()' >> both issues reproducers crash? >> >> Your patch is not incorrect, and inde

Re: [PATCH] softmmu/physmem: Improve guest memory allocation failure error message

On 8/20/21 5:53 PM, David Hildenbrand wrote: > On 20.08.21 17:52, Philippe Mathieu-Daudé wrote: >> When Linux refuses to overcommit a seriously wild allocation we get: >> >>    $ qemu-system-i386 -m 4000 >>    qemu-system-i386: cannot set up guest memory 'pc.ram': Cannot >> allocate memory >> >

Re: xilinx-zynq-a9: cannot set up guest memory 'zynq.ext_ram'

On Fri, 20 Aug 2021 17:47:01 +0200 David Hildenbrand wrote: > On 20.08.21 17:44, Igor Mammedov wrote: > > On Fri, 20 Aug 2021 15:39:27 +0100 > > Peter Maydell wrote: > > > >> On Fri, 20 Aug 2021 at 15:34, David Hildenbrand wrote: > >>> > >>> On 20.08.21 16:22, Bin Meng wrote: > Hi P

Re: xilinx-zynq-a9: cannot set up guest memory 'zynq.ext_ram'

On 8/20/21 6:03 PM, Igor Mammedov wrote: > On Fri, 20 Aug 2021 17:47:01 +0200 > David Hildenbrand wrote: > >> On 20.08.21 17:44, Igor Mammedov wrote: >>> On Fri, 20 Aug 2021 15:39:27 +0100 >>> Peter Maydell wrote: >>> On Fri, 20 Aug 2021 at 15:34, David Hildenbrand wrote: > >

[PATCH] migration: RDMA registrations interval optimization

RDMA migration very hard to complete when VM run mysql benchmark on 1G host hugepage.I think the time between ram_control_before_iterate(f, RAM_CONTROL_ROUND) and after_iterate is too large when 1G host pagesize,so 1M buffer size match with mlx driver that will be good. after this patch,it will wor

Re: xilinx-zynq-a9: cannot set up guest memory 'zynq.ext_ram'

On Fri, 20 Aug 2021 17:53:41 +0200 Philippe Mathieu-Daudé wrote: > On 8/20/21 5:47 PM, David Hildenbrand wrote: > > On 20.08.21 17:44, Igor Mammedov wrote: > >> On Fri, 20 Aug 2021 15:39:27 +0100 > >> Peter Maydell wrote: > >> > >>> On Fri, 20 Aug 2021 at 15:34, David Hildenbrand > >>> wrot

Re: xilinx-zynq-a9: cannot set up guest memory 'zynq.ext_ram'

On 8/20/21 6:08 PM, Igor Mammedov wrote: > On Fri, 20 Aug 2021 17:53:41 +0200 > Philippe Mathieu-Daudé wrote: > >> On 8/20/21 5:47 PM, David Hildenbrand wrote: >>> On 20.08.21 17:44, Igor Mammedov wrote: On Fri, 20 Aug 2021 15:39:27 +0100 Peter Maydell wrote: > On Fri, 20

Re: xilinx-zynq-a9: cannot set up guest memory 'zynq.ext_ram'

On Fri, 20 Aug 2021 18:06:30 +0200 Philippe Mathieu-Daudé wrote: > On 8/20/21 6:03 PM, Igor Mammedov wrote: > > On Fri, 20 Aug 2021 17:47:01 +0200 > > David Hildenbrand wrote: > > > >> On 20.08.21 17:44, Igor Mammedov wrote: > >>> On Fri, 20 Aug 2021 15:39:27 +0100 > >>> Peter Maydell wrot

[PATCH] libqtest: check for g_setenv() failure

g_setenv() can fail; check for it when starting a QEMU process when we set the QEMU_AUDIO_DRV environment variable. Because this happens after fork() reporting an exact message via printf() is a bad idea; just exit(1), as we already do for the case of execlp() failure. Fixes: Coverity CID 1460117

Re: [PATCH] softmmu/physmem: Improve guest memory allocation failure error message

On Fri, 20 Aug 2021 18:00:26 +0200 Philippe Mathieu-Daudé wrote: > On 8/20/21 5:53 PM, David Hildenbrand wrote: > > On 20.08.21 17:52, Philippe Mathieu-Daudé wrote: > >> When Linux refuses to overcommit a seriously wild allocation we get: > >> > >>    $ qemu-system-i386 -m 4000 > >>    qemu

Re: [PATCH] libqtest: check for g_setenv() failure

On 8/20/21 6:37 PM, Peter Maydell wrote: > g_setenv() can fail; check for it when starting a QEMU process > when we set the QEMU_AUDIO_DRV environment variable. > > Because this happens after fork() reporting an exact message > via printf() is a bad idea; just exit(1), as we already do > for the c

Re: [PULL 03/33] i386: split cpu accelerators from cpu.c, using AccelCPUClass

On Tue, 11 May 2021 at 09:22, Paolo Bonzini wrote: > > From: Claudio Fontana > > i386 is the first user of AccelCPUClass, allowing to split > cpu.c into: > > cpu.ccpuid and common x86 cpu functionality > host-cpu.c host x86 cpu functions and "host" cpu type > kvm/kvm-cpu.cKV

[PATCH] target/i386: Fix memory leak in sev_read_file_base64()

In sev_read_file_base64() we call g_file_get_contents(), which allocates memory for the file contents. We then base64-decode the contents (which allocates another buffer for the decoded data), but forgot to free the memory for the original file data. Use g_autofree to ensure that the file data is

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