On 17/08/2021 21.26, Jose R. Ziviani wrote:
If users try to add an isa-vga device that was already registered,
still in command line, qemu will crash:
$ qemu-system-mips64el -M pica61 -device isa-vga
RAMBlock "vga.vram" already registered, abort!
Aborted (core dumped)
That particular board regi
VGIF provides masking capability for when virtual interrupts
are taken. (APM2)
Signed-off-by: Lara Lazier
---
target/i386/cpu.c | 7 +--
target/i386/cpu.h | 2 ++
target/i386/tcg/sysemu/svm_helper.c | 12
3 files changed, 19 insertions(+), 2
Patch 2 adds VGIF capability to mask virtual interrupts.
Patches 3 and 4 fix bugs related to vTPR, while patch 1 refactors
int_ctl into the state structure to simplify the fixes in the
following patches.
Lara Lazier (4):
target/i386: Moved int_ctl into CPUX86State structure
target/i386: Added
The feature allows the VMSAVE and VMLOAD instructions to execute in guest mode
without
causing a VMEXIT. (APM2 15.33.1)
This is currently untested; I sent it out as part of my GSoC project.
Signed-off-by: Lara Lazier
---
target/i386/cpu.h| 2 ++
target/i386/svm.h
Writes to cr8 affect v_tpr. This could set or unset an interrupt
request as the priority might have changed.
Signed-off-by: Lara Lazier
---
target/i386/cpu.h| 15 +++
target/i386/tcg/sysemu/misc_helper.c | 7 +++
target/i386/tcg/sysemu/svm_helper.c | 15
The APM2 states that if V_IGN_TPR is nonzero, the current
virtual interrupt ignores the (virtual) TPR.
Signed-off-by: Lara Lazier
---
target/i386/tcg/sysemu/svm_helper.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/target/i386/tcg/sysemu/svm_helper.c
b/target/i386/tcg/sysemu/svm_hel
Moved int_ctl into the CPUX86State structure to remove some
unnecessary stores and loads.
Signed-off-by: Lara Lazier
---
slirp| 2 +-
target/i386/cpu.c| 2 +-
target/i386/cpu.h| 1 +
target/i386/machine.c|
On 8/18/21 8:27 AM, Thomas Huth wrote:
> On 17/08/2021 11.30, Cédric Le Goater wrote:
>> Fetch the OpenPOWER images to boot the powernv8 and powernv9 machines
>> with a simple PCI layout.
>>
>> Cc: Cleber Rosa
>> Cc: Philippe Mathieu-Daudé
>> Cc: Wainer dos Santos Moschetta
>> Signed-off-by: Céd
On Wed, Aug 18, 2021 at 5:18 AM Richard Henderson
wrote:
>
> Replace uses of tcg_const_* with the allocate and free close together.
>
> Reviewed-by: Philippe Mathieu-Daudé
> Reviewed-by: Alistair Francis
> Signed-off-by: Richard Henderson
> ---
> target/riscv/translate.c| 36 ++
On 31/07/2021 16:41, Jason Thorpe wrote:
(added Michael on CC)
Hey folks —
I’d like to be able to use VirtIO with qemu-system-alpha but, at least on a NetBSD
x86_64 host, it does not currently work. This is because virtio_bus_device_plugged()
in hw/virtio/virtio-bus.c ends up picking addres
On 8/17/21 9:26 PM, Jose R. Ziviani wrote:
> If users try to add an isa-vga device that was already registered,
> still in command line, qemu will crash:
>
> $ qemu-system-mips64el -M pica61 -device isa-vga
> RAMBlock "vga.vram" already registered, abort!
> Aborted (core dumped)
>
> That particul
On 8/18/21 4:47 AM, Wen, Jianxian wrote:
> Add configurable property memory region which can connect with IOMMU region
> to support SMMU translate.
>
> Signed-off-by: Jianxian Wen
> ---
> v3 -> v4 (after review of Philippe Mathieu-Daudé):
> - Avoid adding unnecessary AS, add AS if we connect wi
We appreciate everyone's comments.
Before making the V5 patch, please let me check the patch contents.
> This looks reasonable to me, but you also need the 'sve' property that states
> sve in
> supported at all.
> > > So maybe we should just go ahead and add all sve* properties,
In response t
On 03/08/2021 05:14, Richard Henderson wrote:
The printf should have been qemu_log_mask, the parameters
themselves no longer compile, and because this is placed
before unwinding the PC is actively wrong.
We get better (and correct) logging on the other side of
raising the exception, in sparc_cp
On 03/08/2021 05:14, Richard Henderson wrote:
Signed-off-by: Richard Henderson
---
target/sparc/mmu_helper.c | 72 +--
1 file changed, 46 insertions(+), 26 deletions(-)
diff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c
index a44473a1c7..5
On Tue, Aug 17, 2021 at 01:59:22PM +0400, Marc-André Lureau wrote:
> Hi
>
> On Tue, Aug 17, 2021 at 12:56 PM Michal Privoznik
> wrote:
>
> > When opening a path that starts with "/dev/fdset/" the control
> > jumps into qemu_parse_fdset() and then into
> > monitor_fdset_dup_fd_add(). In here, cor
On 8/3/21 6:13 AM, Richard Henderson wrote:
> Reviewed-by: Peter Maydell
> Signed-off-by: Richard Henderson
> ---
> target/alpha/cpu.c| 2 +-
> target/alpha/mem_helper.c | 8 +++-
> 2 files changed, 4 insertions(+), 6 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
+Helge
On 8/3/21 6:13 AM, Richard Henderson wrote:
> Signed-off-by: Richard Henderson
> ---
> linux-user/hppa/cpu_loop.c | 2 +-
> target/hppa/cpu.c | 9 ++---
> 2 files changed, 7 insertions(+), 4 deletions(-)
>
> diff --git a/linux-user/hppa/cpu_loop.c b/linux-user/hppa/cpu_loop.
On 03/08/2021 05:14, Richard Henderson wrote:
We ought to have been recording the virtual address for reporting
to the guest trap handler. Move the function to mmu_helper.c, so
that we can re-use code shared with get_physical_address_data.
Cc: Mark Cave-Ayland
Signed-off-by: Richard Henderson
On 8/3/21 6:14 AM, Richard Henderson wrote:
> Reviewed-by: David Hildenbrand
> Signed-off-by: Richard Henderson
> ---
> target/s390x/cpu.c | 2 +-
> target/s390x/tcg/excp_helper.c | 28 +++-
> 2 files changed, 16 insertions(+), 14 deletions(-)
Reviewed-by: P
On 8/3/21 6:14 AM, Richard Henderson wrote:
> Cc: Max Filippov
> Signed-off-by: Richard Henderson
> ---
> target/xtensa/cpu.c| 2 +-
> target/xtensa/helper.c | 30 +++---
> 2 files changed, 16 insertions(+), 16 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
On 03/08/2021 05:14, Richard Henderson wrote:
Cc: Mark Cave-Ayland
Signed-off-by: Richard Henderson
---
linux-user/sparc/cpu_loop.c | 11 +++
target/sparc/cpu.c | 2 +-
target/sparc/mmu_helper.c | 4 +++-
3 files changed, 15 insertions(+), 2 deletions(-)
diff --git a
On 03/08/2021 05:14, Richard Henderson wrote:
The helper_*_mmu functions were the only thing available
when this code was written. This could have been adjusted
when we added cpu_*_mmuidx_ra, but now we can most easily
use the newest set of interfaces.
Cc: Mark Cave-Ayland
Signed-off-by: Rich
Hi Richard,
On 8/3/21 6:14 AM, Richard Henderson wrote:
> Use the newly exposed cpu_unaligned_access for atomic_mmu_lookup,
> which has access to complete alignment info from the TCGMemOpIdx arg.
>
> Signed-off-by: Richard Henderson
> ---
> accel/tcg/user-exec.c | 14 +-
> 1 file ch
On Wed, Aug 18, 2021 at 08:29:15AM +, ishii.shuuic...@fujitsu.com wrote:
>
> We appreciate everyone's comments.
> Before making the V5 patch, please let me check the patch contents.
>
> > This looks reasonable to me, but you also need the 'sve' property that
> > states sve in
> > supported a
On 8/3/21 6:14 AM, Richard Henderson wrote:
> There is no point in encoding load/store within a bit of
> the memory trace info operand. Represent atomic operations
> as a single read-modify-write tracepoint. Use MemOpIdx
> instead of inventing a form specifically for traces.
>
> Signed-off-by: R
On 8/3/21 6:14 AM, Richard Henderson wrote:
> Signed-off-by: Richard Henderson
> ---
> target/i386/tcg/mem_helper.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Philippe Mathieu-Daudé
On 8/3/21 6:14 AM, Richard Henderson wrote:
> These functions are much closer to the softmmu helper
> functions, in that they take the complete MemOpIdx,
> and from that they may enforce required alignment.
>
> The previous cpu_ldst.h functions did not have alignment info,
> and so did not enforce
On 10/08/2021 15:06, Daniel P. Berrangé wrote:
We need to cut down compile time by excluding more targets. Both these
targets still have their 64-bit variant enabled, so the loss of coverage
is mitigated to some degree.
Signed-off-by: Daniel P. Berrangé
---
.gitlab-ci.d/crossbuild-template.y
On Wed, Aug 18, 2021 at 5:18 AM Richard Henderson
wrote:
>
> Utilize the condition in the movcond more; this allows some of
> the setcond that were feeding into movcond to be removed.
> Do not write into source1 and source2. Re-name "condN" to "tempN"
> and use the temporaries for more than holdi
On 8/3/21 6:14 AM, Richard Henderson wrote:
> Rather than use 4-16 separate operations, use 2 operations
> plus some byte reordering as necessary.
>
> Cc: Philippe Mathieu-Daudé
> Signed-off-by: Richard Henderson
> ---
> target/mips/tcg/msa_helper.c | 201 +--
>
On 17/08/2021 20:26, Jose R. Ziviani wrote:
If users try to add an isa-vga device that was already registered,
still in command line, qemu will crash:
$ qemu-system-mips64el -M pica61 -device isa-vga
RAMBlock "vga.vram" already registered, abort!
Aborted (core dumped)
That particular board reg
On Wed, Aug 18, 2021 at 5:21 AM Richard Henderson
wrote:
>
Can we put some commit message here to explain the reason behind this change?
> Signed-off-by: Richard Henderson
> ---
> target/riscv/translate.c| 58 -
> target/riscv/insn_trans/trans_rva.c.inc
On Wed, Aug 18, 2021 at 10:15:47AM +0100, Mark Cave-Ayland wrote:
> On 10/08/2021 15:06, Daniel P. Berrangé wrote:
>
> > We need to cut down compile time by excluding more targets. Both these
> > targets still have their 64-bit variant enabled, so the loss of coverage
> > is mitigated to some degr
On 18/08/2021 10:29, Daniel P. Berrangé wrote:
On Wed, Aug 18, 2021 at 10:15:47AM +0100, Mark Cave-Ayland wrote:
On 10/08/2021 15:06, Daniel P. Berrangé wrote:
We need to cut down compile time by excluding more targets. Both these
targets still have their 64-bit variant enabled, so the loss o
Add property memory region which can connect with IOMMU region to support SMMU
translate.
Signed-off-by: Jianxian Wen
---
v5 (after review of Philippe Mathieu-Daudé):
- Refine code and use memory_region_name() to get MR name.
v4 (after review of Philippe Mathieu-Daudé):
- Avoid creating new AS
Am 17.08.21 um 22:21 schrieb Viktor Prutyanov:
Make 'qemu-img commit' work on Windows.
Command 'commit' requires reopening backing file in RW mode. So,
add reopen prepare/commit/abort handlers and change dwShareMode
for CreateFile call in order to allow further read/write reopening.
Resolves: h
On 8/18/21 11:45 AM, Mark Cave-Ayland wrote:
> On 18/08/2021 10:29, Daniel P. Berrangé wrote:
>> On Wed, Aug 18, 2021 at 10:15:47AM +0100, Mark Cave-Ayland wrote:
>>> On 10/08/2021 15:06, Daniel P. Berrangé wrote:
>>>
We need to cut down compile time by excluding more targets. Both these
On 8/18/21 12:17 PM, Wen, Jianxian wrote:
> Add property memory region which can connect with IOMMU region to support
> SMMU translate.
>
> Signed-off-by: Jianxian Wen
> ---
> v5 (after review of Philippe Mathieu-Daudé):
> - Refine code and use memory_region_name() to get MR name.
> v4 (after r
Hello Paolo,
On Mon, Aug 16, 2021 at 05:38:55PM +0200, Paolo Bonzini wrote:
> On 16/08/21 17:13, Ashish Kalra wrote:
> > > > I think that once the mirror VM starts booting and running the UEFI
> > > > code, it might be only during the PEI or DXE phase where it will
> > > > start actually running t
On Wed, Aug 18, 2021 at 5:22 AM Richard Henderson
wrote:
>
> Introduce get_gpr, dest_gpr, temp_new -- new helpers that do not force
> tcg globals into temps, returning a constant 0 for $zero as source and
> a new temp for $zero as destination.
>
> Introduce ctx->w for simplifying word operations,
From: Matheus Ferst
PPC gdbstub code has two possible swaps of the 64-bit elements of AVR
registers: in gdb_get_avr_reg/gdb_set_avr_reg (based on msr_le) and in
gdb_get_reg128/ldq_p (based on TARGET_WORDS_BIGENDIAN).
In softmmu, only the first is done, because TARGET_WORDS_BIGENDIAN is
always tr
From: Matheus Ferst
Changes the current bswap128 implementation to use __builtin_bswap128
when available, adds a bswap128 implementation for !CONFIG_INT128
builds, and introduces bswap128s based on bswap128.
Signed-off-by: Matheus Ferst
---
include/qemu/int128.h | 15 +++
1 file ch
From: Matheus Ferst
As vector registers are stored in host endianness, we shouldn't swap its
64-bit elements in user mode. Add a 16-byte case in
ppc_maybe_bswap_register to handle the reordering of elements in softmmu
and remove avr_need_swap which is now unused.
Signed-off-by: Matheus Ferst
--
On Wed, 2021-08-18 at 10:31 +, Ashish Kalra wrote:
> Hello Paolo,
>
> On Mon, Aug 16, 2021 at 05:38:55PM +0200, Paolo Bonzini wrote:
> > On 16/08/21 17:13, Ashish Kalra wrote:
> > > > > I think that once the mirror VM starts booting and running
> > > > > the UEFI code, it might be only during
Some of the removed CLI options have been added to the wrong section
in the "Removed features" chapter - they've been put into the
"Related binaries" section instead. Move them now into the correct
"System emulator command line arguments" section.
Signed-off-by: Thomas Huth
---
docs/about/remove
Ping ...
On Thu, 12 Aug 2021, Ani Sinha wrote:
> Currently various acpi hotplug modules like cpu hotplug, memory hotplug, pci
> hotplug, nvdimm hotplug are all pulled in when CONFIG_ACPI_X86 is turned on.
> This brings in support for whole lot of subsystems that some targets like
> mips does not
This adds hmp 'info tlb' command support for the arm platform.
The limitation is that this only implements a page walker for
ARMv8-A AArch64 Long Descriptor format, 32bit addressing is
not supported yet.
Signed-off-by: Changbin Du
Signed-off-by: Ivanov Arkady
---
hmp-commands-info.hx |3 +
This adds hmp 'info tlb' command support for the arm platform.
The limitation is that this only implements a page walker for
ARMv8-A AArch64 Long Descriptor format, 32bit addressing is
not supported yet.
To reuse existing code, this patch also extracts some APIs from
helper.c, including regime_tra
To reuse existing code for "tlb info", this patch also extracts
some of the APIs from helper.c including
mode_translation_disabled (), pt_start_level_stage1 (),
mode_ttbr (), arm_ldq_ptw ().
Signed-off-by: Ivanov Arkady
Signed-off-by: Changbin Du
---
target/arm/helper.c| 35 +++---
On Wed, Aug 18, 2021 at 7:48 PM NDNF wrote:
>
> This adds hmp 'info tlb' command support for the arm platform.
> The limitation is that this only implements a page walker for
> ARMv8-A AArch64 Long Descriptor format, 32bit addressing is
> not supported yet.
>
> Signed-off-by: Changbin Du
> Signed
On 8/12/21 11:33 AM, Peter Maydell wrote:
> The stellaris-gptm timer currently uses system_clock_scale for one of
> its timer modes where the timer runs at the CPU clock rate. Make it
> use a Clock input instead.
>
> We don't try to make the timer handle changes in the clock frequency
> while
Security fix. Sorry for the last-minute patch, I had completely
forgotten this one until the CVE number for it arrived today.
Given that the classic usb storage device is way more popular than
the uas (usb attached scsi) device the impact should be pretty low
and we might consider to not screw up
The device uses the guest-supplied stream number unchecked, which can
lead to guest-triggered out-of-band access to the UASDevice->data3 and
UASDevice->status3 fields. Add the missing checks.
Fixes: CVE-2021-3713
Signed-off-by: Gerd Hoffmann
---
hw/usb/dev-uas.c | 11 +++
1 file changed
On 8/18/21 1:06 PM, matheus.fe...@eldorado.org.br wrote:
> From: Matheus Ferst
>
> Changes the current bswap128 implementation to use __builtin_bswap128
> when available, adds a bswap128 implementation for !CONFIG_INT128
> builds, and introduces bswap128s based on bswap128.
>
> Signed-off-by: Ma
> On Aug 18, 2021, at 12:58 AM, Mark Cave-Ayland
> wrote:
>
> On 31/07/2021 16:41, Jason Thorpe wrote:
>
> (added Michael on CC)
>
> Hi Jason,
>
> Thanks for looking at this! I've had previous discussions with Martin trying
> to figure out why virtio-blk-pci doesn't work with Netbsd/sparc6
On Dienstag, 17. August 2021 19:57:21 CEST Philippe Mathieu-Daudé wrote:
> On 8/17/21 6:12 PM, Christian Schoenebeck wrote:
> > On Dienstag, 17. August 2021 14:41:27 CEST Gerd Hoffmann wrote:
> >> Hi,
> >>
> +Overall Audio frontends
> >>>
> >>> I would call that "Audio Hardware Emulation
On Wed, 18 Aug 2021 at 13:00, Bin Meng wrote:
>
> On Wed, Aug 18, 2021 at 7:48 PM NDNF wrote:
> >
> > This adds hmp 'info tlb' command support for the arm platform.
> > The limitation is that this only implements a page walker for
> > ARMv8-A AArch64 Long Descriptor format, 32bit addressing is
>
So could we close this QEMU ticket now, or is there still something to
be done from the QEMU side?
** Bug watch removed: Sourceware.org Bugzilla #27543
https://sourceware.org/bugzilla/show_bug.cgi?id=27543
--
You received this bug notification because you are a member of qemu-
devel-ml, which
Looking at the comments here, I assume this has been a bug in the
kernel, not in QEMU, so I'm closing this one now. If you still think
this is something that needs fixing in QEMU, please open a new ticket in
the new bug tracker at https://gitlab.com/qemu-project/qemu/-/issues
instead.
** Changed i
On Tue, Aug 17, 2021 at 08:14:46PM -0400, Vivek Goyal wrote:
> On Tue, Aug 17, 2021 at 03:45:19PM -0400, Vivek Goyal wrote:
> > On Tue, Aug 17, 2021 at 10:27:16AM +0200, Hanna Reitz wrote:
> > > On 16.08.21 21:44, Vivek Goyal wrote:
> > > > On Wed, Aug 11, 2021 at 08:41:18AM +0200, Hanna Reitz wrot
On Wed, Aug 18, 2021 at 8:54 PM Peter Maydell wrote:
>
> On Wed, 18 Aug 2021 at 13:00, Bin Meng wrote:
> >
> > On Wed, Aug 18, 2021 at 7:48 PM NDNF wrote:
> > >
> > > This adds hmp 'info tlb' command support for the arm platform.
> > > The limitation is that this only implements a page walker fo
Yes, it can be closed.
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1796520
Title:
autogen crashes on qemu-sh4-user after 61dedf2af7
Status in QEMU:
Incomplete
Bug description:
Running "auto
Hi all,
I recently noticed that we have quite a bunch of tickets against the vmxnet3
device in our bug trackers, which indicate that this device could be used to
crash QEMU in various ways:
https://gitlab.com/qemu-project/qemu/-/issues?state=opened&search=vmxnet3
https://bugs.launchpad.
On 18.08.21 15:32, Vivek Goyal wrote:
On Tue, Aug 17, 2021 at 08:14:46PM -0400, Vivek Goyal wrote:
On Tue, Aug 17, 2021 at 03:45:19PM -0400, Vivek Goyal wrote:
On Tue, Aug 17, 2021 at 10:27:16AM +0200, Hanna Reitz wrote:
On 16.08.21 21:44, Vivek Goyal wrote:
On Wed, Aug 11, 2021 at 08:41:18AM
Thanks, closing now.
** Changed in: qemu
Status: Incomplete => Invalid
--
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devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1796520
Title:
autogen crashes on qemu-sh4-user after 61dedf2af7
Status
On Wed, Aug 18, 2021 at 12:37:32AM +0200, Paolo Bonzini wrote:
> On Tue, Aug 17, 2021 at 11:54 PM Steve Rutherford
> wrote:
> > > 1) the easy one: the bottom 4G of guest memory are mapped in the mirror
> > > VM 1:1. The ram_addr_t-based addresses are shifted by either 4G or a
> > > huge value suc
Signed-off-By: Michael Tokarev
---
It is safe for 6.1
block/file-posix.c | 2 +-
tools/virtiofsd/fuse_lowlevel.h | 4 ++--
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/block/file-posix.c b/block/file-posix.c
index cb9bffe047..1854bfa397 100644
--- a/block/file-pos
Signed-off-by: Michael Tokarev
---
accel/kvm/kvm-all.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/accel/kvm/kvm-all.c b/accel/kvm/kvm-all.c
index 0125c17edb..cace5ffe64 100644
--- a/accel/kvm/kvm-all.c
+++ b/accel/kvm/kvm-all.c
@@ -2469,7 +2469,7 @@ static int kvm_init(Ma
Le 18/08/2021 à 16:06, Michael Tokarev a écrit :
> Signed-off-By: Michael Tokarev
> ---
> It is safe for 6.1
>
> block/file-posix.c | 2 +-
> tools/virtiofsd/fuse_lowlevel.h | 4 ++--
> 2 files changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/block/file-posix.c b/block/fil
Signed-off-by: Michael Tokarev
---
accel/kvm/kvm-all.c | 2 +-
target/i386/cpu-sysemu.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/accel/kvm/kvm-all.c b/accel/kvm/kvm-all.c
index 0125c17edb..cace5ffe64 100644
--- a/accel/kvm/kvm-all.c
+++ b/accel/kvm/kvm-all.c
@@
On Tue, Aug 17, 2021 at 3:30 PM Eric Blake wrote:
> On Tue, Aug 03, 2021 at 02:29:25PM -0400, John Snow wrote:
> > It's a little messier than connect, because it wasn't designed to accept
> > *precisely one* connection. Such is life.
> >
> > Signed-off-by: John Snow
> > ---
> > python/qemu/aqmp
On 8/18/21 4:11 PM, Michael Tokarev wrote:
> Signed-off-by: Michael Tokarev
> ---
> accel/kvm/kvm-all.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
IIUC 6.1 is closed now.
Reviewed-by: Philippe Mathieu-Daudé
On 8/18/21 4:06 PM, Michael Tokarev wrote:
> Signed-off-By: Michael Tokarev
> ---
> It is safe for 6.1
But too late ;)
>
> block/file-posix.c | 2 +-
> tools/virtiofsd/fuse_lowlevel.h | 4 ++--
> 2 files changed, 3 insertions(+), 3 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
On Tue, Aug 17, 2021 at 3:48 PM Eric Blake wrote:
> On Tue, Aug 03, 2021 at 02:29:29PM -0400, John Snow wrote:
> > The Message class is here primarily to serve as a solid type to use for
> > mypy static typing for unambiguous annotation and documentation.
> >
> > We can also stuff JSON serializat
On 8/18/21 2:05 PM, Gerd Hoffmann wrote:
> The device uses the guest-supplied stream number unchecked, which can
> lead to guest-triggered out-of-band access to the UASDevice->data3 and
> UASDevice->status3 fields. Add the missing checks.
>
> Fixes: CVE-2021-3713
Reported-by: Chen Zhe
Reported-
* James Bottomley (j...@linux.ibm.com) wrote:
> On Wed, 2021-08-18 at 10:31 +, Ashish Kalra wrote:
> > Hello Paolo,
> >
> > On Mon, Aug 16, 2021 at 05:38:55PM +0200, Paolo Bonzini wrote:
> > > On 16/08/21 17:13, Ashish Kalra wrote:
> > > > > > I think that once the mirror VM starts booting and
On 8/17/21 6:04 PM, Steve Rutherford wrote:
On Tue, Aug 17, 2021 at 1:50 PM Tobin Feldman-Fitzthum
wrote:
This is essentially what we do in our prototype, although we have an
even simpler approach. We have a 1:1 mapping that maps an address to
itself with the cbit set. During Migration QEMU ask
On Wed, 2021-08-18 at 16:31 +0100, Dr. David Alan Gilbert wrote:
> * James Bottomley (j...@linux.ibm.com) wrote:
> > On Wed, 2021-08-18 at 10:31 +, Ashish Kalra wrote:
> > > Hello Paolo,
> > >
> > > On Mon, Aug 16, 2021 at 05:38:55PM +0200, Paolo Bonzini wrote:
> > > > On 16/08/21 17:13, Ashis
* James Bottomley (j...@linux.ibm.com) wrote:
> On Wed, 2021-08-18 at 16:31 +0100, Dr. David Alan Gilbert wrote:
> > * James Bottomley (j...@linux.ibm.com) wrote:
> > > On Wed, 2021-08-18 at 10:31 +, Ashish Kalra wrote:
> > > > Hello Paolo,
> > > >
> > > > On Mon, Aug 16, 2021 at 05:38:55PM +0
For the record, this was fixed for 6.1 in
commit f3f713cc151086ca39d4f97270594fd8c43e17e5
Author: Richard Henderson
Date: Sun Jun 20 16:37:12 2021 -0700
target/rx: Use translator_use_goto_tb
Just use translator_use_goto_tb directly at the one call site,
rather than maintaining
On Wed, 2021-08-18 at 16:43 +0100, Dr. David Alan Gilbert wrote:
> * James Bottomley (j...@linux.ibm.com) wrote:
[...]
> > Given the lack of SMI, we can't guarantee that with plain SEV and
> > -ES. Once we move to -SNP, we can use VMPLs to achieve this.
>
> Doesn't the MH have access to different
MIPS CPU store its endianess in the CP0 Config0 register.
Use that runtime information instead of #ifdef'ry checking
TARGET_WORDS_BIGENDIAN by introducing the cpu_is_bigendian()
helper.
Philippe Mathieu-Daudé (5):
target/mips: Replace GET_OFFSET() macro by get_offset() function
target/mips: Re
The target endianess information is stored in the BigEndian
bit of the Config0 register in CP0.
As a first step, replace the GET_OFFSET() macro by an inlined
get_offset() function, passing CPUMIPSState as argument.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/tcg/ldst_helper.c | 57 +++
Most TCG helpers only have access to a DisasContext pointer,
not CPUMIPSState. Store a copy of CPUMIPSState::CP0_Config0
in DisasContext so we can access it from TCG helpers.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/tcg/translate.h | 1 +
target/mips/tcg/translate.c | 1 +
2 files c
Add the inlined cpu_is_bigendian() function in "translate.h".
Replace the TARGET_WORDS_BIGENDIAN #ifdef'ry by calls to
cpu_is_bigendian().
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/tcg/translate.h | 5 ++
target/mips/tcg/translate.c | 70 --
The target endianess information is stored in the BigEndian
bit of the Config0 register in CP0.
Replace the GET_LMASK() macro by an inlined get_lmask() function,
passing CPUMIPSState and the word size as argument.
We can remove one use of the TARGET_WORDS_BIGENDIAN definition.
Signed-off-by: Phi
The target endianess information is stored in the BigEndian
bit of the Config0 register in CP0.
Replace the GET_LMASK() macro by an inlined get_lmask() function,
passing CPUMIPSState and the word size as argument.
We can remove another use of the TARGET_WORDS_BIGENDIAN definition.
Signed-off-by:
On 8/17/21 3:00 PM, Richard Henderson wrote:
With v8, this is CONSTRAINED UNDEFINED and may either raise an
Bah, UNPREDICTABLE, of course, not UNDEFINED.
r~
On 8/18/21 6:43 AM, Philippe Mathieu-Daudé wrote:
The target endianess information is stored in the BigEndian
bit of the Config0 register in CP0.
As a first step, replace the GET_OFFSET() macro by an inlined
get_offset() function, passing CPUMIPSState as argument.
Signed-off-by: Philippe Mathie
On 8/18/21 6:43 AM, Philippe Mathieu-Daudé wrote:
-if (GET_LMASK(arg2) <= 2) {
+if (get_lmask(env, arg2, 32) <= 2) {
Whatever you decide to do with respect to the previous patch, the result of get_lmask is
constant across the function and should be computed only once.
r~
On Wed, Aug 18, 2021 at 02:06:25PM +, Ashish Kalra wrote:
> On Wed, Aug 18, 2021 at 12:37:32AM +0200, Paolo Bonzini wrote:
> > On Tue, Aug 17, 2021 at 11:54 PM Steve Rutherford
> > wrote:
> > > > 1) the easy one: the bottom 4G of guest memory are mapped in the mirror
> > > > VM 1:1. The ram_a
On 8/18/21 6:43 AM, Philippe Mathieu-Daudé wrote:
Most TCG helpers only have access to a DisasContext pointer,
not CPUMIPSState. Store a copy of CPUMIPSState::CP0_Config0
in DisasContext so we can access it from TCG helpers.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/tcg/translate.h
On 8/18/21 6:43 AM, Philippe Mathieu-Daudé wrote:
Add the inlined cpu_is_bigendian() function in "translate.h".
Replace the TARGET_WORDS_BIGENDIAN #ifdef'ry by calls to
cpu_is_bigendian().
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/tcg/translate.h | 5 ++
target/mips
* James Bottomley (j...@linux.ibm.com) wrote:
> On Wed, 2021-08-18 at 16:43 +0100, Dr. David Alan Gilbert wrote:
> > * James Bottomley (j...@linux.ibm.com) wrote:
> [...]
> > > Given the lack of SMI, we can't guarantee that with plain SEV and
> > > -ES. Once we move to -SNP, we can use VMPLs to ach
On 8/17/21 10:51 PM, Philippe Mathieu-Daudé wrote:
-void *ret = g2h(env_cpu(env), addr);
+
+ret = g2h(env_cpu(env), addr);
set_helper_retaddr(retaddr);
return ret;
Can't we simply do:
return g2h(env_cpu(env), addr);
?
I think the idea was to narrow the range of i
On 8/17/21 11:01 PM, Philippe Mathieu-Daudé wrote:
On 8/3/21 6:14 AM, Richard Henderson wrote:
These functions are much closer to the softmmu helper
functions, in that they take the complete MemOpIdx,
and from that they may enforce required alignment.
The previous cpu_ldst.h functions did not h
On 8/17/21 11:21 PM, Philippe Mathieu-Daudé wrote:
+#ifdef TARGET_WORDS_BIGENDIAN
+static inline uint64_t bswap16x4(uint64_t x)
+{
+uint64_t m = 0x00ff00ff00ff00ffull;
+return ((x & m) << 8) | ((x >> 8) & m);
+}
+
+static inline uint64_t bswap32x2(uint64_t x)
+{
+return ror64(bswap64(
Buglink: https://bugzilla.redhat.com/show_bug.cgi?id=1707441
The issue is in LSC clearing. So, after "link up"(during initialization),
the next LSC event is masked and can't be processed.
Technically, the event should be 'cleared' during ICR read.
On Windows guest, everything works well, mostly be
On Fri, Aug 13, 2021 at 11:11 AM Niteesh G. S. wrote:
>
> On Fri, Aug 6, 2021 at 12:28 AM John Snow wrote:
>
>>
>> On Fri, Jul 30, 2021 at 4:19 PM G S Niteesh Babu
>> wrote:
>>
>>> Added a draft of AQMP TUI.
>>>
>>> Implements the follwing basic features:
>>> 1) Command transmission/reception.
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