Currently various acpi hotplug modules like cpu hotplug, memory hotplug, pci
hotplug, nvdimm hotplug are all pulled in when CONFIG_ACPI_X86 is turned on.
This brings in support for whole lot of subsystems that some targets like
mips does not need. They are added just to satisfy symbol dependencies.
On 2021/8/12 下午2:12, Richard Henderson wrote:
On 8/11/21 7:03 PM, LIU Zhiwei wrote:
On 2021/8/12 下午12:42, Richard Henderson wrote:
On 8/11/21 12:40 PM, LIU Zhiwei wrote:
If the software doesn't use the high part, who cares the really
value in high part? Do you know the benefit? Thanks agai
On Thu, Aug 12, 2021 at 8:45 AM Jason Wang wrote:
>
> On Thu, Aug 12, 2021 at 2:43 PM Eugenio Perez Martin
> wrote:
> >
> > On Thu, Aug 12, 2021 at 8:16 AM Jason Wang wrote:
> > >
> > > On Thu, Aug 12, 2021 at 12:32 AM Eugenio Pérez
> > > wrote:
> > > >
> > > > With the introduction of the bat
On 8/12/21 3:40 AM, David Gibson wrote:
> On Wed, Aug 11, 2021 at 11:07:31AM +0200, Thomas Huth wrote:
>> On 10/08/2021 11.09, Cédric Le Goater wrote:
>>> On 8/10/21 10:36 AM, Joel Stanley wrote:
On Tue, 10 Aug 2021 at 08:34, Cédric Le Goater wrote:
>
> Fetch the OpenPOWER images to b
On 8/11/21 4:12 PM, Luc Michel wrote:
> The TCG_KICK_PERIOD macro is already defined in tcg-accel-ops-rr.h.
> Remove it from tcg-accel-ops-rr.c.
>
> Signed-off-by: Luc Michel
> ---
> accel/tcg/tcg-accel-ops-rr.c | 2 --
> 1 file changed, 2 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
Hi Peter,
On 8/11/21 2:58 PM, Peter Maydell wrote:
> On Wed, 11 Aug 2021 at 07:44, Gerd Hoffmann wrote:
>>
>> The following changes since commit 703e8cd6189cf699c8d5c094bc68b5f3afa6ad71:
>>
>> Update version for v6.1.0-rc3 release (2021-08-10 19:08:09 +0100)
>>
>> are available in the Git repos
On 09.08.2021 13:48, Denis Plotnikov wrote:
On vhost-user-blk migration, qemu normally sends a number of commands
to enable logging if VHOST_USER_PROTOCOL_F_LOG_SHMFD is negotiated.
Qemu sends VHOST_USER_SET_FEATURES to enable buffers logging and
VHOST_USER_SET_VRING_ADDR per each started ring
.bdrv_co_block_status() implementations are free to return a *pnum that
exceeds @bytes, because bdrv_co_block_status() in block/io.c will clamp
*pnum as necessary.
On the other hand, if drivers' implementations return values for *pnum
that are as large as possible, our recently introduced block-st
Hi,
See the cover letter from v1 for the general idea:
https://lists.nongnu.org/archive/html/qemu-block/2021-06/msg00843.html
Cover letter from v2, introducing RCU locking:
https://lists.nongnu.org/archive/html/qemu-block/2021-06/msg01060.html
v3:
- Patch 2:
- Add rcu_head object to BdrvBlock
As we have attempted before
(https://lists.gnu.org/archive/html/qemu-devel/2019-01/msg06451.html,
"file-posix: Cache lseek result for data regions";
https://lists.nongnu.org/archive/html/qemu-block/2021-02/msg00934.html,
"file-posix: Cache next hole"), this patch seeks to reduce the number of
SEEK_
There is a comment above the BDS definition stating care must be taken
to consider handling newly added fields in bdrv_append().
Actually, this comment should have said "bdrv_swap()" as of 4ddc07cac
(nine years ago), and in any case, bdrv_swap() was dropped in
8e419aefa (six years ago). So no suc
bdrv_co_block_status() does it for us, we do not need to do it here.
The advantage of not capping *pnum is that bdrv_co_block_status() can
cache larger data regions than requested by its caller.
Signed-off-by: Hanna Reitz
Reviewed-by: Eric Blake
Reviewed-by: Vladimir Sementsov-Ogievskiy
Review
bdrv_co_block_status() does it for us, we do not need to do it here.
The advantage of not capping *pnum is that bdrv_co_block_status() can
cache larger data regions than requested by its caller.
Signed-off-by: Hanna Reitz
Reviewed-by: Eric Blake
Reviewed-by: Vladimir Sementsov-Ogievskiy
Review
bdrv_co_block_status() does it for us, we do not need to do it here.
The advantage of not capping *pnum is that bdrv_co_block_status() can
cache larger data regions than requested by its caller.
Signed-off-by: Hanna Reitz
Reviewed-by: Eric Blake
Reviewed-by: Vladimir Sementsov-Ogievskiy
Review
Hi,
> > On Tue, Aug 10, 2021 at 03:17:43PM +0300, cla...@hotmail.com wrote:
> >> Gerd Hoffmann writes:
> >>
> >> Hell Gerd.
> >>
> >> > New maintainer wanted. Downgrade status to "Odd Fixes" for now.
> >>
> >> I can try to retake it.
Given your track record is zero contributions to qemu in
On Thu, Aug 12, 2021 at 03:04:38PM +0900, Shuuichirou Ishii wrote:
> Add a definition for the Fujitsu A64FX processor.
>
> The A64FX processor does not implement the AArch32 Execution state,
> so there are no associated AArch32 Identification registers.
>
> For SVE, the A64FX processor supports o
On 07/23/2021 02:29 PM, Richard Henderson wrote:
>
>> +void helper_movgr2fcsr(CPULoongArchState *env, target_ulong arg1,
>> + uint32_t fcsr)
>> +{
>> + switch (fcsr) {
>> + case 0:
>> + env->active_fpu.fcsr0 = arg1;
>> + break;
>> + case 1:
>> +
On Thu, Aug 12, 2021 at 11:16:50AM +0200, Andrew Jones wrote:
> On Thu, Aug 12, 2021 at 03:04:38PM +0900, Shuuichirou Ishii wrote:
> > Add a definition for the Fujitsu A64FX processor.
> >
> > The A64FX processor does not implement the AArch32 Execution state,
> > so there are no associated AArch3
This is mostly a (big) refactoring to use Clocks instead of a global.
Review of the new multiplier/divider functionality I've added to the
Clock API would also be interesting. If you're a maintainer for an
M-profile board that isn't covered by 'make check-acceptance' then
I'd appreciate it if you
Currently we implement the RAS register block within the NVIC device.
It isn't really very tightly coupled with the NVIC proper, so instead
move it out into a sysbus device of its own and have the top level
ARMv7M container create it and map it into memory at the right
address.
Signed-off-by: Pete
Add the usual-style QEMU interface comment documenting what
properties, etc, this device exposes.
Signed-off-by: Peter Maydell
---
include/hw/timer/armv7m_systick.h | 7 +++
1 file changed, 7 insertions(+)
diff --git a/include/hw/timer/armv7m_systick.h
b/include/hw/timer/armv7m_systick.h
i
Instead of having the NVIC device provide a single sysbus memory
region covering the whole of the "System PPB" space, which implements
the default behaviour for unimplemented ranges and provides the NS
alias window to the sysregs as well as the main sysreg MR, move this
handling to the container ar
There's no particular reason why the NVIC should be owning the
SysTick device objects; move them into the ARMv7M container object
instead, as part of consolidating the "create the devices which are
built into an M-profile CPU and map them into their architected
locations in the address space" work
Wire up the sysclk and refclk for the stm32f100 SoC. This SoC always
runs the systick refclk at 1/8 the frequency of the main CPU clock,
so the board code only needs to provide a single sysclk clock.
Because there is only one board using this SoC, we convert the SoC
and the board together, rather
The v7M systick timer can be programmed to run from either of
two clocks:
* an "external reference clock" (when SYST_CSR.CLKSOURCE == 0)
* the main CPU clock (when SYST_CSR.CLKSOURCE == 1)
Our implementation currently hardwires the external reference clock
to be 1MHz, and allows boards to set th
In the realize methods of the stm32f100 and stm32f205 SoC objects, we
call g_new() to create new MemoryRegion objjects for the sram, flash,
and flash_alias. This is unnecessary (and leaves open the
possibility of leaking the allocations if we exit from realize with
an error). Make these MemoryReg
Wire up the sysclk and refclk for the stm32f205 SoC. This SoC always
runs the systick refclk at 1/8 the frequency of the main CPU clock,
so the board code only needs to provide a single sysclk clock.
Because there is only one board using this SoC, we convert the SoC
and the board together, rather
It is quite common for a clock tree to involve possibly programmable
clock multipliers or dividers, where the frequency of a clock is for
instance divided by 8 to produce a slower clock to feed to a
particular device.
Currently we provide no convenient mechanism for modelling this. You
can implem
Create input clocks on the armv7m container object which pass through
to the systick timers, so that users of the armv7m object can specify
the clocks being used.
Signed-off-by: Peter Maydell
---
include/hw/arm/armv7m.h | 6 ++
hw/arm/armv7m.c | 23 +++
2 files c
Currently the stellaris_sys_init() function creates the
TYPE_STELLARIS_SYS object, sets its properties, realizes it, maps its
MMIO region and connects its IRQ. In order to support wiring the
sysclk up to the armv7m object, we need to split this function apart,
because to connect the clock output o
Connect the sysclk to the armv7m object. This board's SoC does not
connect up the systick reference clock, so we don't need to connect a
refclk.
Signed-off-by: Peter Maydell
---
hw/arm/stellaris.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/hw/arm/stellaris.c b/hw/ar
Wire up the sysclk and refclk for the stm32f405 SoC. This SoC always
runs the systick refclk at 1/8 the frequency of the main CPU clock,
so the board code only needs to provide a single sysclk clock.
Because there is only one board using this SoC, we convert the SoC
and the board together, rather
Connect up the armv7m clocks on the mps2-an385/386/500/511.
Connect up the armv7m object's clocks on the MPS boards defined in
mps2.c. The documentation for these FPGA images doesn't specify what
systick reference clock is used (if any), so for the moment we
provide a 1MHz refclock, which will re
Wire up the refclk for the msf2 SoC. This SoC runs the refclk at a
frequency which is programmably either /4, /8, /16 or /32 of the main
CPU clock. We don't currently model the register which allows the
guest to set the divisor, so implement the refclk as a fixed /32 of
the CPU clock (which is th
Wire up the cpuclk for the systick devices to the SSE object's
existing mainclk clock.
We do not wire up the refclk because the SSE subsystems do not
provide a refclk. (This is documented in the IoTKit and SSE-200
TRMs; the SSE-300 TRM doesn't mention it but we assume it follows the
same approach
Wire up the sysclk input to the armv7m object.
Strictly this SoC should not have a systick device at all, but our
armv7m container object doesn't currently support disabling the
systick device. For the moment, add a TODO comment, but note that
this is why we aren't wiring up a refclk (no need for
Fix the code style issues in the Stellaris general purpose timer
module code, so that when we move it to a different file in a
following patch checkpatch doesn't complain.
Signed-off-by: Peter Maydell
---
hw/arm/stellaris.c | 13 -
1 file changed, 8 insertions(+), 5 deletions(-)
dif
On Fri, 30 Jul 2021 at 20:07, Richard Henderson
wrote:
> I'll note two things:
>
> (1) The val == extval check could be sunk to the end of the function and
> shared with the
> left shift,
>
> (2) sat will never be unset, as #48 is encoded as sat=1 in the insn.
True; I'm kind of aiming for parity
The implementation of the Stellaris general purpose timer module
device stellaris-gptm is currently in the same source file as the
board model. Split it out into its own source file in hw/timer.
Apart from the new file comment headers and the Kconfig and
meson.build changes, this is just code mov
Instead of passing the MSF2 SoC an integer property specifying the
CPU clock rate, pass it a Clock instead. This lets us wire that
clock up to the armv7m object.
Signed-off-by: Peter Maydell
---
include/hw/arm/msf2-soc.h | 3 ++-
hw/arm/msf2-soc.c | 28 +---
hw/
Delete the trailing blank line at the end of the source file.
Signed-off-by: Peter Maydell
---
hw/arm/stm32vldiscovery.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/hw/arm/stm32vldiscovery.c b/hw/arm/stm32vldiscovery.c
index 07e401a818d..9b79004703b 100644
--- a/hw/arm/stm32vldiscovery.c
In the realize method of the msf2-soc SoC object, we call g_new() to
create new MemoryRegion objects for the nvm, nvm_alias, and sram.
This is unnecessary; make these MemoryRegions member fields of the
device state struct instead.
Signed-off-by: Peter Maydell
---
include/hw/arm/msf2-soc.h | 4 +
The stellaris-gptm timer currently uses system_clock_scale for one of
its timer modes where the timer runs at the CPU clock rate. Make it
use a Clock input instead.
We don't try to make the timer handle changes in the clock frequency
while the downcounter is running. This is not a change in beha
On Thu, 12 Aug 2021 at 10:25, Andrew Jones wrote:
> On second thought, do we want the QMP CPU model expansion query to show
> that this CPU type has sve,sve128,sve256,sve512? If so, then our SVE work
> isn't complete, because we need those properties, set true by default, but
> forbidden from chan
Now that all users of the systick devices wire up the clock inputs,
use those instead of the system_clock_scale and the hardwired 1MHz
value for the reference clock.
This will fix various board models where we were incorrectly
providing a 1MHz reference clock instead of some other value or
instead
Paolo Bonzini writes:
> On Mac --enable-modules and --enable-plugins are currently incompatible,
> because the
> Apple -Wl,-exported_symbols_list command line options prevents the export of
> any
> symbols needed by the modules. On x86 -Wl,--dynamic-list does not have this
> effect,
> but o
All the devices that used to use system_clock_scale have now been
converted to use Clock inputs instead, so the global is no longer
needed; remove it and all the code that sets it.
Signed-off-by: Peter Maydell
---
include/hw/timer/armv7m_systick.h | 22 --
hw/arm/armsse.c
On 8/12/21 1:56 AM, Richard Henderson wrote:
On 8/11/21 6:45 PM, Richard Henderson wrote:
On 8/11/21 5:39 PM, David Gibson wrote:
I mean, nothing is stopping us from calculating cycles using time, but in the
end we would do the same thing we're already doing today.
Oh.. ok. I had assumed
Related: https://bugzilla.redhat.com//show_bug.cgi?id=1985924
Signed-off-by: Gerd Hoffmann
---
hw/isa/lpc_ich9.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/hw/isa/lpc_ich9.c b/hw/isa/lpc_ich9.c
index 5f9de0239cf9..5f143dca17aa 100644
--- a/hw/isa/lpc_ich9.c
+++ b/hw/isa/lp
The sphinx-build is fairly verbose spitting out pages of output to the
console, which causes errors from other build commands to be scrolled
off the top of the terminal. This can leave the mistaken impression that
the build passed, when in fact there was a failure.
Signed-off-by: Daniel P. Berrang
On 8/12/21 12:24 PM, Daniel P. Berrangé wrote:
> The sphinx-build is fairly verbose spitting out pages of output to the
> console, which causes errors from other build commands to be scrolled
> off the top of the terminal. This can leave the mistaken impression that
> the build passed, when in fact
On Thu, Aug 12, 2021 at 12:23:41PM +0200, Gerd Hoffmann wrote:
> Related: https://bugzilla.redhat.com//show_bug.cgi?id=1985924
> Signed-off-by: Gerd Hoffmann
> ---
> hw/isa/lpc_ich9.c | 13 +
> 1 file changed, 13 insertions(+)
>
> diff --git a/hw/isa/lpc_ich9.c b/hw/isa/lpc_ich9.c
>
Hi Richard,
On 7/21/21 11:53 AM, Song Gao wrote:
> This patch add support for disassembling via option '-d in_asm'.
>
> Signed-off-by: Song Gao
> ---
> MAINTAINERS |1 +
> disas/loongarch.c | 2511
> +++
> disas/meson.build
On Thu, Aug 12, 2021 at 04:37:26AM +0300, Yajun Wu via wrote:
If call virtio_queue_set_host_notifier_mr fails, should free
host-notifier memory-region.
We can add:
Fixes: 44866521bd ("vhost-user: support registering external host notifiers")
Signed-off-by: Yajun Wu
---
hw/virtio/vhost-user.c
On Thu, Aug 12, 2021 at 2:25 PM Daniel P. Berrangé
wrote:
> The sphinx-build is fairly verbose spitting out pages of output to the
> console, which causes errors from other build commands to be scrolled
> off the top of the terminal. This can leave the mistaken impression that
> the build passed,
Il gio 12 ago 2021, 11:40 Alex Bennée ha scritto:
> ERROR: glib-2.56 gmodule-noexport-2.0 is required to compile QEMU
>
> Should it be gmodule-no-export? Hopefully the different distros aren't
> packaging different .pc files.
>
My bad. :( It's correct with the dash.
Does this mean --enable-mo
On Wed, Aug 11, 2021 at 11:47:05AM +0200, Thomas Huth wrote:
> vhost-user-blk-test needs the qemu-storage-deamon, otherwise it
> currently hangs. So make sure that we build the daemon before running
> the tests.
>
> Signed-off-by: Thomas Huth
> ---
> storage-daemon/meson.build | 8
> te
Mahmoud Mandour writes:
> This post introduces the new TCG plugin `cache` that's used for cache
> modelling. This plugin is a part of my GSoC 2021 participation.
>
> Signed-off-by: Mahmoud Mandour
Reviewed-by: Alex Bennée
--
Alex Bennée
What's the right way to ensure that when a machine has multiple
buses of the same type (eg multiple i2c controllers, multiple
sd card controllers) they all get assigned unique names so that
the user can use '-device ...,bus=some-name' to put a device on a
specific bus?
For instance in hw/arm/xlnx-
Hi,
> > +if ((lpc->smi_host_features &
> > BIT_ULL(ICH9_LPC_SMI_F_CPU_HOT_UNPLUG_BIT)) &&
> > +!(lpc->smi_host_features &
> > BIT_ULL(ICH9_LPC_SMI_F_CPU_HOTPLUG_BIT))) {
> > +/*
> > + * smi_features_ok_callback() throws an error on this.
> > + *
> > +
On 8/12/21 11:33 AM, Peter Maydell wrote:
Currently we implement the RAS register block within the NVIC device.
It isn't really very tightly coupled with the NVIC proper, so instead
move it out into a sysbus device of its own and have the top level
ARMv7M container create it and map it into mem
From: "Dr. David Alan Gilbert"
ShellCheck points out that tr '[a-z]' actually replaces the []'s
and only the a-z is needed.
Remove the spurious [] - although in this use it will make no
difference.
Fixes: bb55b712e8dc4d4eb515144d5c26798fea178cba
Signed-off-by: Dr. David Alan Gilbert
---
confi
~0UL has 64 bits on Linux and 32 bits on Windows.
Fixes: https://gitlab.com/qemu-project/qemu/-/issues/512";.
Reported-by: Volker Rümelin
Signed-off-by: Lara Lazier
---
target/i386/tcg/sysemu/misc_helper.c | 2 +-
target/i386/tcg/sysemu/svm_helper.c | 2 +-
2 files changed, 2 insertions(+), 2
On Thu, 12 Aug 2021 at 12:08, Alexandre IOOSS wrote:
>
>
>
> On 8/12/21 11:33 AM, Peter Maydell wrote:
> > Currently we implement the RAS register block within the NVIC device.
> > It isn't really very tightly coupled with the NVIC proper, so instead
> > move it out into a sysbus device of its own
On Thu, 12 Aug 2021 at 11:53, Daniel P. Berrangé wrote:
>
> On Wed, Aug 11, 2021 at 11:47:05AM +0200, Thomas Huth wrote:
> > vhost-user-blk-test needs the qemu-storage-deamon, otherwise it
> > currently hangs. So make sure that we build the daemon before running
> > the tests.
> >
> > Signed-off-b
Add MSI-X aswell since either MSI or MSI-X are optional and
MSI can still be used without any issues.
Signed-off-by: Neil Armstrong
---
hw/misc/edu.c | 15 ++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/hw/misc/edu.c b/hw/misc/edu.c
index e935c418d4..5d0643e1bd 100
On 8/12/21 1:10 PM, Lara Lazier wrote:
> ~0UL has 64 bits on Linux and 32 bits on Windows.
> Fixes: https://gitlab.com/qemu-project/qemu/-/issues/512";.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/512
Fixes: 3407259b20c ("target/i386: Added consistency checks for CR3")
> Reported-by:
On 8/12/21 11:33 AM, Peter Maydell wrote:
Instead of having the NVIC device provide a single sysbus memory
region covering the whole of the "System PPB" space, which implements
the default behaviour for unimplemented ranges and provides the NS
alias window to the sysregs as well as the main sys
On Thu, 12 Aug 2021 at 12:11, Dr. David Alan Gilbert (git)
wrote:
>
> From: "Dr. David Alan Gilbert"
>
> ShellCheck points out that tr '[a-z]' actually replaces the []'s
> and only the a-z is needed.
>
> Remove the spurious [] - although in this use it will make no
> difference.
>
> Fixes: bb55b7
On 8/12/21 11:33 AM, Peter Maydell wrote:
It is quite common for a clock tree to involve possibly programmable
clock multipliers or dividers, where the frequency of a clock is for
instance divided by 8 to produce a slower clock to feed to a
particular device.
Currently we provide no convenient
On 8/12/21 11:33 AM, Peter Maydell wrote:
In the realize methods of the stm32f100 and stm32f205 SoC objects, we
call g_new() to create new MemoryRegion objjects for the sram, flash,
and flash_alias. This is unnecessary (and leaves open the
possibility of leaking the allocations if we exit from r
On Thu, 12 Aug 2021 at 13:08, Alexandre IOOSS wrote:
>
>
> On 8/12/21 11:33 AM, Peter Maydell wrote:
> > It is quite common for a clock tree to involve possibly programmable
> > clock multipliers or dividers, where the frequency of a clock is for
> > instance divided by 8 to produce a slower clock
On Donnerstag, 12. August 2021 10:42:10 CEST Gerd Hoffmann wrote:
> Hi,
>
> > > On Tue, Aug 10, 2021 at 03:17:43PM +0300, cla...@hotmail.com wrote:
> > >> Gerd Hoffmann writes:
> > >>
> > >> Hell Gerd.
> > >>
> > >> > New maintainer wanted. Downgrade status to "Odd Fixes" for now.
> > >>
> >
On 8/12/21 11:33 AM, Peter Maydell wrote:
Delete the trailing blank line at the end of the source file.
Signed-off-by: Peter Maydell
---
hw/arm/stm32vldiscovery.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/hw/arm/stm32vldiscovery.c b/hw/arm/stm32vldiscovery.c
index 07e401a818d..9b79
On Thu, 12 Aug 2021 at 13:13, Alexandre IOOSS wrote:
>
> On 8/12/21 11:33 AM, Peter Maydell wrote:
> > In the realize methods of the stm32f100 and stm32f205 SoC objects, we
> > call g_new() to create new MemoryRegion objjects for the sram, flash,
> > and flash_alias. This is unnecessary (and leav
On Thu, 12 Aug 2021 at 12:38, Philippe Mathieu-Daudé wrote:
>
> On 8/12/21 1:10 PM, Lara Lazier wrote:
> > ~0UL has 64 bits on Linux and 32 bits on Windows.
>
> > Fixes: https://gitlab.com/qemu-project/qemu/-/issues/512";.
>
> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/512
> Fixes: 34
On 8/12/21 2:54 PM, Peter Maydell wrote:
> On Thu, 12 Aug 2021 at 12:38, Philippe Mathieu-Daudé wrote:
>>
>> On 8/12/21 1:10 PM, Lara Lazier wrote:
>>> ~0UL has 64 bits on Linux and 32 bits on Windows.
>>
>>> Fixes: https://gitlab.com/qemu-project/qemu/-/issues/512";.
>>
>> Resolves: https://gitla
* Peter Maydell (peter.mayd...@linaro.org) wrote:
> On Thu, 12 Aug 2021 at 12:11, Dr. David Alan Gilbert (git)
> wrote:
> >
> > From: "Dr. David Alan Gilbert"
> >
> > ShellCheck points out that tr '[a-z]' actually replaces the []'s
> > and only the a-z is needed.
> >
> > Remove the spurious [] -
Don't allocate the string until error conditions have been checked
Fixes: a00cfed0e ("Hexagon (disas) disassembler")
Eliminate Coverity CID 1460121 (Resource leak)
Signed-off-by: Taylor Simpson
---
disas/hexagon.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/disas/hexag
On Thu, 12 Aug 2021 at 14:09, Taylor Simpson wrote:
>
> Don't allocate the string until error conditions have been checked
>
> Fixes: a00cfed0e ("Hexagon (disas) disassembler")
> Eliminate Coverity CID 1460121 (Resource leak)
>
> Signed-off-by: Taylor Simpson
> ---
> disas/hexagon.c | 3 ++-
> 1
Hi all,
On 8/12/21 2:24 PM, Christian Schoenebeck wrote:
> On Donnerstag, 12. August 2021 10:42:10 CEST Gerd Hoffmann wrote:
>> Hi,
>>
On Tue, Aug 10, 2021 at 03:17:43PM +0300, cla...@hotmail.com wrote:
> Gerd Hoffmann writes:
>
> Hell Gerd.
>
>> New maintainer wanted.
On 8/12/21 3:09 PM, Taylor Simpson wrote:
> Don't allocate the string until error conditions have been checked
>
> Fixes: a00cfed0e ("Hexagon (disas) disassembler")
> Eliminate Coverity CID 1460121 (Resource leak)
>
> Signed-off-by: Taylor Simpson
> ---
> disas/hexagon.c | 3 ++-
> 1 file chang
On Thu, 12 Aug 2021, Ani Sinha wrote:
> Currently various acpi hotplug modules like cpu hotplug, memory hotplug, pci
> hotplug, nvdimm hotplug are all pulled in when CONFIG_ACPI_X86 is turned on.
> This brings in support for whole lot of subsystems that some targets like
> mips does not need. T
On 8/12/21 3:22 PM, Ani Sinha wrote:
> On Thu, 12 Aug 2021, Ani Sinha wrote:
>
>> Currently various acpi hotplug modules like cpu hotplug, memory hotplug, pci
>> hotplug, nvdimm hotplug are all pulled in when CONFIG_ACPI_X86 is turned on.
>> This brings in support for whole lot of subsystems that
On Thu, Aug 12, 2021 at 02:05:36PM +0100, Dr. David Alan Gilbert wrote:
> Indeed it's not; there's LOTS of warnings; although most of them are
> probably irrelevant; there are also two others at the error level:
>
> In configure line 4406:
> if "$ld" -verbose 2>&1 | grep -q "^[[:space:]]*$
With the introduction of the batch hinting, meaningless batches can be
created with no IOTLB updates if the memory region was skipped by
vhost_vdpa_listener_skipped_section. This is the case of host notifiers
memory regions, device un/realize, and others. This causes the vdpa
device to receive dma
The gunzip() function reads various fields from a passed in source
buffer in order to skip a header before passing the actual compressed
data to the zlib inflate() function. It does check whether the
passed in buffer is too small, but unfortunately it checks that only
after reading bytes from the
On Thu, 12 Aug 2021 12:23:41 +0200
Gerd Hoffmann wrote:
> Related: https://bugzilla.redhat.com//show_bug.cgi?id=1985924
> Signed-off-by: Gerd Hoffmann
Reviewed-by: Igor Mammedov
> ---
> hw/isa/lpc_ich9.c | 13 +
> 1 file changed, 13 insertions(+)
>
> diff --git a/hw/isa/lpc_ich9
In the riscv virt machine init function, We assemble a string
plic_hart_config which is a comma-separated list of N copies of the
VIRT_PLIC_HART_CONFIG string. The code that does this has a
misunderstanding of the strncat() length argument. If the source
string is too large strncat() will write a
On Mon, 9 Aug 2021 at 10:46, Peter Maydell wrote:
>
> On Tue, 25 Aug 2020 at 20:03, Alistair Francis
> wrote:
> >
> > From: Anup Patel
> >
> > We extend RISC-V virt machine to allow creating a multi-socket
> > machine. Each RISC-V virt machine socket is a NUMA node having
> > a set of HARTs, a
In the alignment check added to qemu_ram_alloc_from_fd() in commit
ce317be98db0dfdfa, the condition includes a check that 'mr' is not
NULL. This check is unnecessary because we can assume that the
caller always passes us a valid MemoryRegion, and indeed later in the
function we assume mr is not NU
The realpath() function can return NULL on error, so we need to check
for it to avoid crashing when we try to strstr() into it.
This can happen if we run out of memory, or if /sys/ is not mounted,
among other situations.
Fixes: Coverity 1459913, 1460474
Fixes: ce317be98db0 ("exec: fetch the alignm
On 8/11/21 3:25 AM, Joel Stanley wrote:
> On Tue, 10 Aug 2021 at 23:37, Corey Minyard wrote:
>>
>> On Mon, Aug 09, 2021 at 03:15:55PM +0200, Cédric Le Goater wrote:
>>> From: Joel Stanley
>>>
>>> This contains some hardcoded register values that were obtained from the
>>> hardware after reading t
Paolo Bonzini writes:
> Il gio 12 ago 2021, 11:40 Alex Bennée ha scritto:
>
>ERROR: glib-2.56 gmodule-noexport-2.0 is required to compile QEMU
>
> Should it be gmodule-no-export? Hopefully the different distros aren't
> packaging different .pc files.
>
> My bad. :( It's correct with the
On Thu, 12 Aug 2021, Philippe Mathieu-Daudé wrote:
> On 8/12/21 3:22 PM, Ani Sinha wrote:
> > On Thu, 12 Aug 2021, Ani Sinha wrote:
> >
> >> Currently various acpi hotplug modules like cpu hotplug, memory hotplug,
> >> pci
> >> hotplug, nvdimm hotplug are all pulled in when CONFIG_ACPI_X86 is t
Instead of counting how many elements from the top of the stack we need
to ignore until we find the thing we're interested in, we can just
directly pass the StackObject pointer because all callers already know
it.
We only need a different way now to tell if we want to know the name of
something co
This adds functions to the Visitor interface that can be used to define
aliases and alias scopes.
Signed-off-by: Kevin Wolf
---
include/qapi/visitor-impl.h | 12
include/qapi/visitor.h | 59 ++---
qapi/qapi-visit-core.c | 22 ++
3 fi
This makes qobject-input-visitor remember the currently valid aliases in
each StackObject. It doesn't actually allow using the aliases yet.
Signed-off-by: Kevin Wolf
---
qapi/qobject-input-visitor.c | 147 +++
1 file changed, 147 insertions(+)
diff --git a/qapi/q
When looking for an object in a struct in the external representation,
check not only the currently visited struct, but also whether an alias
in the current StackObject matches and try to fetch the value from the
alias then. Providing two values for the same object through different
aliases is an e
This series introduces alias definitions for QAPI object types (structs
and unions).
This allows using the same QAPI type and visitor even when the syntax
has some variations between different external interfaces such as QMP
and the command line.
It also provides a new tool for evolving the schem
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