This fixes the MMIO region so that the rtc works again on the ast2600.
The two patches after that are cleanups.
Joel Stanley (3):
hw: aspeed_gpio: Fix memory size
hw: aspeed_gpio: Simplify 1.8V defines
hw: aspeed_gpio: Clarify GPIO controller name
hw/gpio/aspeed_gpio.c | 100 ++
The macro used to calculate the maximum memory size of the MMIO region
had a mistake, causing all GPIO models to create a mapping of 0x9D8.
The intent was to have it be 0x9D8 - 0x800.
This extra size doesn't matter on ast2400 and ast2500, which have a 4KB
region set aside for the GPIO controller.
There are two GPIO controllers in the ast2600; one is 3.3V and the other
is 1.8V.
Signed-off-by: Joel Stanley
---
hw/gpio/aspeed_gpio.c | 26 +-
1 file changed, 13 insertions(+), 13 deletions(-)
diff --git a/hw/gpio/aspeed_gpio.c b/hw/gpio/aspeed_gpio.c
index dc721aec5da
There's no need to define the registers relative to the 0x800 offset
where the controller is mapped, as the device is instantiated as it's
own model at the correct memory address.
Simplify the defines and remove the offset to save future confusion.
Signed-off-by: Joel Stanley
---
hw/gpio/aspeed
在 2021/7/13 上午7:06, Bin Meng 写道:
On Mon, Jul 5, 2021 at 1:57 PM Bin Meng wrote:
On Mon, Jul 5, 2021 at 12:21 PM Jason Wang wrote:
在 2021/7/2 下午5:24, Bin Meng 写道:
From: Christina Wang
The initial value of VLAN Ether Type (VET) register is 0x8100, as per
the manual and real hardware.
Whi
On Mon, 12 Jul 2021, Finn Thain wrote:
> On Sun, 11 Jul 2021, Philippe Mathieu-Daudé wrote:
>
> >
> > > If I'm right that the big_endian flag should go away, commit
> > > b1600ff195 ("hw/mips/jazz: specify correct endian for dp8393x
> > > device") has already taken mainline in the wrong direct
LIU Zhiwei 於 2021年4月9日 週五 下午3:55寫道：
> When a vectored interrupt is selected and serviced, the hardware will
> automatically clear the corresponding pending bit in edge-triggered mode.
> This may lead to a lower priviledge interrupt pending forever.
>
> Therefore when interrupts return, pull a pen
On 08/07/2021 21.12, Cole Robinson wrote:
Hi all,
I'm a bit confused about the intended scope of ./configure
--without-default-features. When I try it here there's still lots of
stuff enabled:
$ ./configure --without-default-features
...
VNC support : YES
VNC SAS
Hi Drew,
On 2021/7/12 23:25, Andrew Jones wrote:
On Fri, Jul 02, 2021 at 06:07:37PM +0800, Yanan Wang wrote:
We are currently using maxcpus to calculate value of sockets but using
cpus to calculate value of cores/threads. This makes cmdlines like
"-smp 8,maxcpus=12,cores=4" work while "-smp 8,m
On Tue, 2021-07-13 at 16:28 +0930, Joel Stanley wrote:
> The macro used to calculate the maximum memory size of the MMIO
> region
> had a mistake, causing all GPIO models to create a mapping of 0x9D8.
> The intent was to have it be 0x9D8 - 0x800.
>
> This extra size doesn't matter on ast2400 and a
On Tue, 2021-07-13 at 16:28 +0930, Joel Stanley wrote:
> There's no need to define the registers relative to the 0x800 offset
> where the controller is mapped, as the device is instantiated as it's
> own model at the correct memory address.
>
> Simplify the defines and remove the offset to save fu
On Tue, 2021-07-13 at 16:28 +0930, Joel Stanley wrote:
> There are two GPIO controllers in the ast2600; one is 3.3V and the
> other
> is 1.8V.
>
> Signed-off-by: Joel Stanley
Thanks for picking this up.
Reviewed-by: Rashmica Gupta
> ---
> hw/gpio/aspeed_gpio.c | 26 +-
>
On 2021/7/2 18:07, Yanan Wang wrote:
We are currently using maxcpus to calculate value of sockets but using
cpus to calculate value of cores/threads. This makes cmdlines like
"-smp 8,maxcpus=12,cores=4" work while "-smp 8,maxcpus=12,sockets=3"
break the invalid cpu topology check.
This patch all
On Mon, 12 Jul 2021 at 11:30, Philippe Mathieu-Daudé wrote:
>
> The following changes since commit d1987c8114921eb30859854de664f879b5626da7:
>
> Merge remote-tracking branch 'remotes/bonzini-gitlab/tags/for-upstream'
> into staging (2021-07-11 22:20:51 +0100)
>
> are available in the Git reposi
On Tue, 13 Jul 2021 02:42:04 +0200
Julia Suvorova wrote:
> Q35 has three different types of PCI devices hot-plug: PCIe Native,
> SHPC Native and ACPI hot-plug. This patch changes the default choice
> for cold-plugged bridges from PCIe Native to ACPI Hot-plug with
> ability to use SHPC and PCIe Na
Brijesh,
On 10/07/2021 0:55, Brijesh Singh wrote:
> SEV-SNP builds upon existing SEV and SEV-ES functionality while adding
> new hardware-based memory protections. SEV-SNP adds strong memory integrity
> protection to help prevent malicious hypervisor-based attacks like data
> replay, memory re-map
On Friday, July 9, 2021 10:48 PM, Peter Xu wrote:
> On Fri, Jul 09, 2021 at 08:58:08AM +, Wang, Wei W wrote:
> > On Friday, July 9, 2021 2:31 AM, Peter Xu wrote:
> > > > > Yes I think this is the place I didn't make myself clear. It's
> > > > > not about sleeping, it's about the cmpxchg being
Viresh Kumar writes:
> On 26-05-21, 13:13, Alex Bennée wrote:
>>
>> Viresh Kumar writes:
>>
>> > Update .gitignore to ignore .swp and .patch files.
>> >
>> > Signed-off-by: Viresh Kumar
>>
>> Reviewed-by: Alex Bennée
>
> No one picked it up yet, do I need to do something here ?
As no one
* Dov Murik (dovmu...@linux.ibm.com) wrote:
> Brijesh,
>
> On 10/07/2021 0:55, Brijesh Singh wrote:
> > SEV-SNP builds upon existing SEV and SEV-ES functionality while adding
> > new hardware-based memory protections. SEV-SNP adds strong memory integrity
> > protection to help prevent malicious hy
On Tue, Jul 13, 2021 at 3:03 PM Jason Wang wrote:
>
>
> 在 2021/7/13 上午7:06, Bin Meng 写道:
> > On Mon, Jul 5, 2021 at 1:57 PM Bin Meng wrote:
> >> On Mon, Jul 5, 2021 at 12:21 PM Jason Wang wrote:
> >>>
> >>> 在 2021/7/2 下午5:24, Bin Meng 写道:
> From: Christina Wang
>
> The initial va
On Thursday, July 1, 2021 4:08 AM, Peter Xu wrote:
> Taking the mutex every time for each dirty bit to clear is too slow,
> especially we'll
> take/release even if the dirty bit is cleared. So far it's only used to sync
> with
> special cases with qemu_guest_free_page_hint() against migration th
On 13/07/2021 09.20, Thomas Huth wrote:
On 08/07/2021 21.12, Cole Robinson wrote:
Hi all,
I'm a bit confused about the intended scope of ./configure
--without-default-features. When I try it here there's still lots of
stuff enabled:
$ ./configure --without-default-features
...
VNC su
Reported on GitLab as https://gitlab.com/qemu-project/qemu/-/issues/427
** Bug watch added: gitlab.com/qemu-project/qemu/-/issues #427
https://gitlab.com/qemu-project/qemu/-/issues/427
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEM
在 2021/7/13 下午4:36, Bin Meng 写道:
On Tue, Jul 13, 2021 at 3:03 PM Jason Wang wrote:
在 2021/7/13 上午7:06, Bin Meng 写道:
On Mon, Jul 5, 2021 at 1:57 PM Bin Meng wrote:
On Mon, Jul 5, 2021 at 12:21 PM Jason Wang wrote:
在 2021/7/2 下午5:24, Bin Meng 写道:
From: Christina Wang
The initial value
On Tue, Jul 13, 2021 at 5:02 PM Jason Wang wrote:
>
>
> 在 2021/7/13 下午4:36, Bin Meng 写道:
> > On Tue, Jul 13, 2021 at 3:03 PM Jason Wang wrote:
> >>
> >> 在 2021/7/13 上午7:06, Bin Meng 写道:
> >>> On Mon, Jul 5, 2021 at 1:57 PM Bin Meng wrote:
> On Mon, Jul 5, 2021 at 12:21 PM Jason Wang wrote:
13.07.2021 00:55, Richard Henderson wrote:
From clang-13:
nbd/server.c:976:22: error: variable 'bitmaps' set but not used \
[-Werror,-Wunused-but-set-variable]
Cc: qemu-bl...@nongnu.org
Cc: Eric Blake
Cc: Vladimir Sementsov-Ogievskiy
Signed-off-by: Richard Henderson
---
nbd/server.c |
On Mon, 12 Jul 2021 at 14:23, Daniel P. Berrangé wrote:
>
> The following changes since commit bd38ae26cea0d1d6a97f930248df149204c210a2:
>
> Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20210710'
> into staging (2021-07-12 11:02:39 +0100)
>
> are available in the Git repositor
The "xen" variable should either contain "enabled", "disabled" or
nothing (for auto detection). But when the user currently runs the
configure script with --without-default-features, it gets set to
"no" instead. This does not work as expected, the feature will still
be enabled if the Xen headers ar
There's no reason why we should keep VNC enabled when the user
specified --without-default-features.
Reported-by: Cole Robinson
Signed-off-by: Thomas Huth
---
configure | 2 +-
meson.build | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/configure b/configure
index 229ea
13.07.2021 02:56, John Snow wrote:
On Tue, Jul 6, 2021 at 5:49 AM Vladimir Sementsov-Ogievskiy mailto:vsement...@virtuozzo.com>> wrote:
25.06.2021 21:20, John Snow wrote:
> This turns run_linters() into a bit of a hybrid test; returning non-zero
> on failed execution while also p
Many features do not get properly disabled when the user runs the
configure script with --without-default-features. Let's fix that now.
Thomas Huth (4):
configure: Fix --without-default-features propagation to meson
configure: Allow vnc to get disabled with --without-default-features
configu
A typo prevents that many features get disabled when the user
runs "configure" with the --without-default-features switch.
Reported-by: Cole Robinson
Signed-off-by: Thomas Huth
---
configure | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/configure b/configure
index 85db248a
The vhost_kernel and vhost_vdpa variables should be pre-initialized with
the $default_feature setting so that these features get disabled when
the user runs the configure scripts with --without-default-features.
Reported-by: Cole Robinson
Signed-off-by: Thomas Huth
---
configure | 2 ++
1 file
On Tue, Jul 13, 2021 at 07:43:59AM +0200, Klaus Jensen wrote:
From: Klaus Jensen
The new PMR test unearthed a long-standing issue with MMIO reads on
big-endian hosts.
Fix by using the ldn_he_p helper instead of memcpy.
Cc: Gollu Appalanaidu
Reported-by: Peter Maydell
Signed-off-by: Klaus Je
On Tue, Jul 13, 2021 at 06:30:28AM +0100, Christoph Hellwig wrote:
On Tue, Jul 13, 2021 at 06:30:28AM +0100, Christoph Hellwig wrote:
> On Mon, Jul 12, 2021 at 12:03:27PM +0100, Stefan Hajnoczi wrote:
> > Why did you decide to implement -device nvme-mi as a device on
> > TYPE_NVME_BUS? If the NVMe
Fix pba_offset initialization value for BAIDU KUNLUN Virtual
Function device. The KUNLUN hardware returns an incorrect
value for the VF PBA offset, and add a quirk to instead
return a hardcoded value of 0xb400.
v1->v2:
*add the incorrect value and BAR size to comment
*use vfio_pci_i
25.06.2021 21:20, John Snow wrote:
This turns run_linters() into a bit of a hybrid test; returning non-zero
on failed execution while also printing diffable information. This is
done for the benefit of the avocado simple test runner, which will soon
be attempting to execute this test from a diffe
25.06.2021 21:20, John Snow wrote:
Split the linter execution itself out from 297, leaving just environment
setup in 297. This is done so that non-iotest code can invoke the
linters without needing to worry about imports of unpackaged iotest
code.
Eventually, it should be possible to replace lin
25.06.2021 21:20, John Snow wrote:
Add a main() function to linters.py so that the Python CI infrastructure
has something it can run.
Now, linters.py represents an invocation of the linting scripts that
more resembles a "normal" execution of pylint/mypy, like you'd expect to
use if 'qemu' was a
On 7/13/21 12:05 AM, Cleber Rosa wrote:
> Wainer dos Santos Moschetta writes:
>
>> Hi,
>>
>> On 5/15/21 10:45 AM, Philippe Mathieu-Daudé wrote:
>>> Add a pair of tests for the Pegasos2 machine following the steps from:
>>> https://lists.nongnu.org/archive/html/qemu-devel/2021-01/msg01553.html
>>>
25.06.2021 21:20, John Snow wrote:
As a convenience, since iotests is an extremely prominent user of the
qemu.qmp and qemu.machine packages and already implements a linting
regime, run those tests as well so that it's very hard to miss
regressions caused by changes to the python library.
Signed-
Hi David,
On Tue, Jul 13, 2021 at 7:12 AM David Gibson
wrote:
> On Tue, Jul 13, 2021 at 02:42:01AM +0200, Julia Suvorova wrote:
> > Add acpi_pcihp to ich9_pm as part of
> > 'acpi-pci-hotplug-with-bridge-support' option. Set default to false.
> >
> > Signed-off-by: Julia Suvorova
> > Signed-off-
On Tue, 13 Jul 2021 at 06:44, Klaus Jensen wrote:
>
> From: Klaus Jensen
>
> The new PMR test unearthed a long-standing issue with MMIO reads on
> big-endian hosts.
>
> Fix by using the ldn_he_p helper instead of memcpy.
>
> Cc: Gollu Appalanaidu
> Reported-by: Peter Maydell
> Signed-off-by: Kl
On Jul 13 11:07, Peter Maydell wrote:
> On Tue, 13 Jul 2021 at 06:44, Klaus Jensen wrote:
> >
> > From: Klaus Jensen
> >
> > The new PMR test unearthed a long-standing issue with MMIO reads on
> > big-endian hosts.
> >
> > Fix by using the ldn_he_p helper instead of memcpy.
> >
> > Cc: Gollu Appa
On 7/13/21 5:14 AM, Qiang Liu wrote:
> xlnx_dp_read allows an out-of-bounds read at its default branch because
> of an improper index.
>
> According to
> https://www.xilinx.com/html_docs/registers/ug1087/ug1087-zynq-ultrascale-registers.html
> (DP Module), registers 0x3A4/0x3A4/0x3AC are allowed.
On 13.07.21 10:40, Wang, Wei W wrote:
On Thursday, July 1, 2021 4:08 AM, Peter Xu wrote:
Taking the mutex every time for each dirty bit to clear is too slow, especially
we'll
take/release even if the dirty bit is cleared. So far it's only used to sync
with
special cases with qemu_guest_free_p
Hi Igor,
On Tue, Jul 13, 2021 at 10:59 AM Igor Mammedov wrote:
> On Tue, 13 Jul 2021 02:42:04 +0200
> Julia Suvorova wrote:
>
> > Q35 has three different types of PCI devices hot-plug: PCIe Native,
> > SHPC Native and ACPI hot-plug. This patch changes the default choice
> > for cold-plugged bri
On 7/13/21 12:20 PM, Philippe Mathieu-Daudé wrote:
> On 7/13/21 5:14 AM, Qiang Liu wrote:
>> xlnx_dp_read allows an out-of-bounds read at its default branch because
>> of an improper index.
>>
>> According to
>> https://www.xilinx.com/html_docs/registers/ug1087/ug1087-zynq-ultrascale-registers.html
On Mon, 12 Jul 2021 at 16:02, Philippe Mathieu-Daudé wrote:
>
> The following changes since commit bd38ae26cea0d1d6a97f930248df149204c210a2:
>
> Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20210710'
> into staging (2021-07-12 11:02:39 +0100)
>
> are available in the Git repos
On Tue, 13 Jul 2021 at 11:19, Klaus Jensen wrote:
>
> On Jul 13 11:07, Peter Maydell wrote:
> > Looking at the surrounding code, I notice that we guard this "read size
> > bytes
> > from &n->bar + addr" with
> > if (addr < sizeof(n->bar)) {
> >
> > but that doesn't account for 'size', so if t
On Jul 13 11:31, Peter Maydell wrote:
> On Tue, 13 Jul 2021 at 11:19, Klaus Jensen wrote:
> >
> > On Jul 13 11:07, Peter Maydell wrote:
> > > Looking at the surrounding code, I notice that we guard this "read size
> > > bytes
> > > from &n->bar + addr" with
> > > if (addr < sizeof(n->bar)) {
On Friday, 2021-07-09 at 16:08:44 -04, Alexander Bulekov wrote:
> By default, -fsanitize=fuzzer instruments all code with coverage
> information. However, this means that libfuzzer will track coverage over
> hundreds of source files that are unrelated to virtual-devices. This
> means that libfuzzer
On Tue, 6 Jul 2021 at 11:39, Paolo Bonzini wrote:
>
> Make -smp syntactic sugar for a compound property "-machine
> smp.{cores,threads,cpu,...}". machine_smp_parse is replaced by the
> setter for the property.
>
> numa-test will now cover the new syntax, while other tests
> still use -smp.
>
> Si
On 7/13/21 12:25 PM, Peter Maydell wrote:
> On Mon, 12 Jul 2021 at 16:02, Philippe Mathieu-Daudé
> wrote:
>>
>> The following changes since commit bd38ae26cea0d1d6a97f930248df149204c210a2:
>>
>> Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20210710'
>> into staging (2021-07-1
On Tue, 14 Jul 2020 at 01:44, Alistair Francis wrote:
>
> From: Atish Patra
>
> Currently, the fdt is copied to the ROM after the reset vector. The firmware
> has to copy it to DRAM. Instead of this, directly copy the device tree to a
> pre-computed dram address. The device tree load address shou
On Tue, 6 Jul 2021 at 11:39, Paolo Bonzini wrote:
>
> Make -smp syntactic sugar for a compound property "-machine
> smp.{cores,threads,cpu,...}". machine_smp_parse is replaced by the
> setter for the property.
>
> numa-test will now cover the new syntax, while other tests
> still use -smp.
>
> Si
* Li Zhijian (lizhij...@cn.fujitsu.com) wrote:
> backtrace:
> '0x75f44ec2 in __ibv_dereg_mr_1_1 (mr=0x7fff1007d390) at
> /home/lizhijian/rdma-core/libibverbs/verbs.c:478
> 478 void *addr = mr->addr;
> (gdb) bt
> #0 0x75f44ec2 in __ibv_dereg_mr_1_1 (mr=0x7
* Laurent Vivier (lviv...@redhat.com) wrote:
> When the migration fails or is canceled we wait the end of the unplug
> operation to be able to plug it back. But if the unplug operation
> is never finished we stop to wait and QEMU emits a warning to inform
> the user.
>
> Based-on: 20210629155007.6
On Fri, 9 Jul 2021 at 06:17, David Gibson wrote:
>
> From: Alexey Kardashevskiy
>
> The PAPR platform describes an OS environment that's presented by
> a combination of a hypervisor and firmware. The features it specifies
> require collaboration between the firmware and the hypervisor.
Hi; Cover
* Peter Xu (pet...@redhat.com) wrote:
> A few more issues spotted by either Xiaohui or me. Please see and review
> individual patches for what they do. Thanks,
>
> Peter Xu (3):
> migration: Release return path early for paused postcopy
> migration: Don't do migrate cleanup if during postcop
Peter Maydell writes:
> On Tue, 6 Jul 2021 at 11:39, Paolo Bonzini wrote:
>>
>> Make -smp syntactic sugar for a compound property "-machine
>> smp.{cores,threads,cpu,...}". machine_smp_parse is replaced by the
>> setter for the property.
>>
>> numa-test will now cover the new syntax, while othe
On Fri, 9 Jul 2021 at 06:17, David Gibson wrote:
>
> From: Alexey Kardashevskiy
>
> The PAPR platform describes an OS environment that's presented by
> a combination of a hypervisor and firmware. The features it specifies
> require collaboration between the firmware and the hypervisor.
Another C
The GBM library detection does not need to be in the configure script,
since it does not have any user-facing options (there are no
--enable-gbm or --disable-gbm switches). Let's move it to meson.build
instead, so we don't have to clutter config-host.mak with the related
switches.
Additionally, on
On Tue, Jul 13, 2021 at 11:25:21AM +0100, Peter Maydell wrote:
> On Mon, 12 Jul 2021 at 16:02, Philippe Mathieu-Daudé
> wrote:
> >
> > The following changes since commit bd38ae26cea0d1d6a97f930248df149204c210a2:
> >
> > Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20210710'
>
On Tue, Jul 13, 2021 at 12:35:18PM +0200, Philippe Mathieu-Daudé wrote:
> On 7/13/21 12:25 PM, Peter Maydell wrote:
> > On Mon, 12 Jul 2021 at 16:02, Philippe Mathieu-Daudé
> > wrote:
> >>
> >> The following changes since commit
> >> bd38ae26cea0d1d6a97f930248df149204c210a2:
> >>
> >> Merge re
On Tue, Jul 13, 2021 at 6:24 PM Philippe Mathieu-Daudé wrote:
>
> On 7/13/21 12:20 PM, Philippe Mathieu-Daudé wrote:
> > On 7/13/21 5:14 AM, Qiang Liu wrote:
> >> xlnx_dp_read allows an out-of-bounds read at its default branch because
> >> of an improper index.
> >>
> >> According to
> >> https://
Le 12/07/2021 à 23:29, jonathan.albrecht a écrit :
> On 2021-07-12 4:02 pm, Laurent Vivier wrote:
>> Le 09/07/2021 à 18:04, Jonathan Albrecht a écrit :
>>> qemu-s390x signals with SIGILL on compare-and-trap instructions. This
>>> breaks OpenJDK which expects SIGFPE in its implementation of implicit
On Mon, Jul 12, 2021 at 01:24:07PM +, Thanos Makatos wrote:
> We're working on implementing a virtual NVMe controller based on SPDK and a
> multiprocess-qemu branch that uses the vfio-user. We're facing a problem
> where the existing API doesn't allow us to tell QEMU from which NVMe
> namesp
On 7/12/21 4:47 PM, Stefan Berger wrote:
Use QMP to check whether a given TPM device model is available
and if it is not the case then skip a test that requires it.
Signed-off-by: Stefan Berger
+rsp_tpm = qtest_qmp(qts, "{ 'execute': 'query-tpm'}");
+if (!qdict_haskey(rsp_tpm, "error
On 13/07/21 13:15, Thomas Huth wrote:
The GBM library detection does not need to be in the configure script,
since it does not have any user-facing options (there are no
--enable-gbm or --disable-gbm switches). Let's move it to meson.build
instead, so we don't have to clutter config-host.mak with
On Tue, Jul 13, 2021 at 12:27:48PM +0300, Vladimir Sementsov-Ogievskiy wrote:
> 13.07.2021 00:55, Richard Henderson wrote:
> > From clang-13:
> > nbd/server.c:976:22: error: variable 'bitmaps' set but not used \
> > [-Werror,-Wunused-but-set-variable]
> >
> > +++ b/nbd/server.c
> > @@ -973,
On Mon, Jul 12, 2021 at 10:41:46AM +0200, Emanuele Giuseppe Esposito wrote:
>
>
> On 08/07/2021 15:04, Stefan Hajnoczi wrote:
> > On Thu, Jul 08, 2021 at 01:32:12PM +0200, Paolo Bonzini wrote:
> > > On 08/07/21 12:36, Stefan Hajnoczi wrote:
> > > > > What is very clear from this patch is that it
On Tue, Jul 13, 2021 at 08:01:34AM -0500, Eric Blake wrote:
> > > @@ -973,7 +973,6 @@ static int nbd_negotiate_meta_queries(NBDClient
> > > *client,
> > > {
> > > int ret;
> > > g_autofree char *export_name = NULL;
> > > -g_autofree bool *bitmaps = NULL;
> > > NBDExportMeta
On Mon, Jul 12, 2021 at 10:42:47AM +0200, Emanuele Giuseppe Esposito wrote:
> On 08/07/2021 15:09, Stefan Hajnoczi wrote:
> > On Wed, Jul 07, 2021 at 06:58:07PM +0200, Emanuele Giuseppe Esposito wrote:
> > > This is a continuation on the work to reduce (and possibly get rid of)
> > > the usage of
On Mon, 12 Jul 2021 at 17:50, Stefan Hajnoczi wrote:
>
> The following changes since commit bd38ae26cea0d1d6a97f930248df149204c210a2:
>
> Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20210710'
> into staging (2021-07-12 11:02:39 +0100)
>
> are available in the Git repository a
On Mon, Jul 12, 2021 at 10:43:07AM +0200, Emanuele Giuseppe Esposito wrote:
>
>
> On 08/07/2021 12:50, Stefan Hajnoczi wrote:
> > On Wed, Jul 07, 2021 at 06:58:09PM +0200, Emanuele Giuseppe Esposito wrote:
> > > diff --git a/job.c b/job.c
> > > index 872bbebb01..96fb8e9730 100644
> > > --- a/job.
A cut-and-paste error meant we handled signed VADDV like
unsigned VADDV; fix the type used.
Signed-off-by: Peter Maydell
---
target/arm/mve_helper.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
index 16a701933b8..99b4
Although the architecture doesn't define it as an alias, VMOVL
(vector move long) is encoded as a VSHLL with a zero shift.
Add a comment in the decode file noting that we handle VMOVL
as part of VSHLL.
Signed-off-by: Peter Maydell
---
target/arm/mve.decode | 2 ++
1 file changed, 2 insertions(+)
This patchseries provides the third slice of the MVE implementation.
In this series:
* fixes for minor bugs in a couple of the insns already upstream
* all the remaining integer instructions
* the remaining loads and stores (scatter-gather and interleaving)
This is obviously for-6.2 material, s
Include the MVE VPR register value in the CPU dumps produced by
arm_cpu_dump_state() if we are printing FPU information. This
makes it easier to interpret debug logs when predication is
active.
Signed-off-by: Peter Maydell
---
target/arm/cpu.c | 3 +++
1 file changed, 3 insertions(+)
diff --git
In mve_element_mask(), we calculate a mask for tail predication which
should have a number of 1 bits based on the value of LR. However,
our MAKE_64BIT_MASK() macro has undefined behaviour when passed a
zero length. Special case this to give the all-zeroes mask we
require.
Signed-off-by: Peter Ma
In the MVE helpers for the narrowing operations (DO_VSHRN and
DO_VSHRN_SAT) we were using the wrong bits of the predicate mask for
the 'top' versions of the insn. This is because the loop works over
the double-sized input elements and shifts the predicate mask by that
many bits each time, but when
In the MVE shift-and-insert insns, we special case VSLI by 0
and VSRI by , both of which mean "no shift". However we
incorrectly implemented these as "don't update the destination",
which works only if Qd == Qm. When Qd != Qm this kind of
shift must update Qd, honouring the predicate mask.
Signed-
For vector loads, predicated elements are zeroed, instead of
retaining their previous values (as happens for most data
processing operations). This means we need to distinguish
"beat not executed due to ECI" (don't touch destination
element) from "beat executed but predicated out" (zero
destination
In some situations we need a mask telling us which parts of the
vector correspond to beats that are not being executed because of
ECI, separately from the combined "which bytes are predicated away"
mask. Factor this mask calculation out of mve_element_mask() into
its own function.
Signed-off-by:
Implement the MVE VMULL (polynomial) insn. Unlike Neon, this comes
in two flavours: 8x8->16 and a 16x16->32. Also unlike Neon, the
inputs are in either the low or the high half of each double-width
element.
The assembler for this insn indicates the size with "P8" or "P16",
encoded into bit 28 as
Factor out the "generate code to update VPR.MASK01/MASK23" part of
trans_VPST(); we are going to want to reuse it for the VPT insns.
Signed-off-by: Peter Maydell
---
target/arm/translate-mve.c | 31 +--
1 file changed, 17 insertions(+), 14 deletions(-)
diff --git a/t
We were not paying attention to the ECI state when advancing the VPT
state. Architecturally, VPT state advance happens for every beat
(see the pseudocode VPTAdvance()), so on every beat the 4 bits of
VPR.P0 corresponding to the current beat are inverted if required,
and at the end of beats 1 and 3
In do_sqrshl48_d() and do_uqrshl48_d() we got some of the edge
cases wrong and failed to saturate correctly:
(1) In do_sqrshl48_d() we used the same code that do_shrshl_bhs()
does to obtain the saturated most-negative and most-positive 48-bit
signed values for the large-shift-left case. This give
All the users of the vmlaldav formats have an 'x bit in bit 12 and an
'a' bit in bit 5; move these to the format rather than specifying them
in each insn pattern.
Signed-off-by: Peter Maydell
---
Not sure why I didn't write it this way in the first place;
when I came to implement VMLADAV I notice
Implement the MVE integer vector comparison instructions that compare
each element against a scalar from a general purpose register. These
are "VCMP (vector)" encodings T4, T5 and T6 and "VPT (vector)"
encodings T4, T5 and T6.
We have to move the decodetree pattern for VPST, because it
overlaps w
Implement the MVE instructions which perform shifts by a scalar.
These are VSHL T2, VRSHL T2, VQSHL T1 and VQRSHL T2. They take the
shift amount in a general purpose register and shift every element in
the vector by that amount.
Mostly we can reuse the helper functions for shift-by-immediate; we
Implement the MVE incrementing/decrementing dup insns VIDUP, VDDUP,
VIWDUP and VDWDUP. These fill the elements of a vector with
successively incrementing values, starting at the offset specified in
a general purpose register. The final value of the offset is written
back to this register. The wr
Implement the MVE VPSEL insn, which sets each byte of the destination
vector Qd to the byte from either Qn or Qm depending on the value of
the corresponding bit in VPR.P0.
Signed-off-by: Peter Maydell
---
target/arm/helper-mve.h| 2 ++
target/arm/mve.decode | 7 +--
target/arm/mve
The MVEGenDualAccOpFn is a bit misnamed, since it is used for
the "long dual accumulate" operations that use a 64-bit
accumulator. Rename it to MVEGenLongDualAccOpFn so we can
use the former name for the 32-bit accumulator insns.
Signed-off-by: Peter Maydell
---
target/arm/translate-mve.c | 16 +
Implement the MVE VMLADAV and VMLSLDAV insns. Like the VMLALDAV and
VMLSLDAV insns already implemented, these accumulate multiplied
vector elements; but they accumulate a 32-bit result rather than a
64-bit one.
Note that these encodings overlap with what would be RdaHi=0b111 for
VMLALDAV, VMLSLDA
Implement the MVE integer vector comparison instructions. These are
"VCMP (vector)" encodings T1, T2 and T3, and "VPT (vector)" encodings
T1, T2 and T3.
These insns compare corresponding elements in each vector, and update
the VPR.P0 predicate bits with the results of the comparison. VPT
also se
Implement the MVE VMLAS insn, which multiplies a vector by a vector
and adds a scalar.
Signed-off-by: Peter Maydell
---
target/arm/helper-mve.h| 8
target/arm/mve.decode | 3 +++
target/arm/mve_helper.c| 31 +++
target/arm/translate-mve.c | 2
Implement the MVE narrowing move insns VMOVN, VQMOVN and VQMOVUN.
These take a double-width input, narrow it (possibly saturating) and
store the result to either the top or bottom half of the output
element.
Signed-off-by: Peter Maydell
---
target/arm/helper-mve.h| 20 ++
target/arm/
Implement the MVE 1-operand saturating operations VQABS and VQNEG.
Signed-off-by: Peter Maydell
---
target/arm/helper-mve.h| 8
target/arm/mve.decode | 3 +++
target/arm/mve_helper.c| 37 +
target/arm/translate-mve.c | 2 ++
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