Commit ("i386: split cpu accelerators from cpu.c, using AccelCPUClass")
introduced two bugs that break cpu max and host in the refactoring,
by running initializations in the wrong order.
This small series of two patches is an attempt to correct the situation.
Please provide your test results and
we need to expand features first, before we attempt to check them
in the accel realizefn code called by cpu_exec_realizefn().
At the same time we need checks for code_urev and host_cpuid_required,
and modifications to cpu->mwait to happen after the initial setting
of them inside the accel realizef
This partially fixes host and max cpu initialization,
by running the accel cpu initialization only after all instance
init functions are called for all X86 cpu subclasses.
Partial Fix.
Fixes: 48afe6e4eabf ("i386: split cpu accelerators from cpu.c, using
AccelCPUClass")
Signed-off-by: Claudio Fon
On 1/7/19 12:22 PM, Alex Bennée wrote:
>
> Aleksandar Markovic writes:
>
>> From: Aleksandar Markovic
>>
>> Remove old directories after reorganization of MIPS TCG tests.
>>
>> Signed-off-by: Aleksandar Markovic
>> ---
>> tests/tcg/mips/mips32-dsp/Makefile| 136 -
>> tests
Hi Aleksandar Rikalo,
On 1/24/19 4:37 PM, Aleksandar Rikalo wrote:
>> From: Aleksandar Markovic
>> Sent: Thursday, January 24, 2019 4:19 PM
>> To: qemu-devel@nongnu.org
>> Cc: aurel...@aurel32.net; Aleksandar Markovic; Aleksandar Rikalo
>> Subject: [PATCH v4 0/3] tests: Reorganize MIPS TCG direct
Per the "MIPS® DSP Module for MIPS64 Architecture" manual (rev 3.02),
Figure 5.12 "SPECIAL3 Encoding of APPEND/DAPPEND Instruction Sub-class"
the byte position field ('bp') is 2 bits, not 3.
Cc: Jia Liu
Fixes: 26690560240 ("target-mips: Add ASE DSP compare-pick instructions")
Signed-off-by: Phili
On Mon, Aug 20, 2018 at 8:17 PM Aleksandar Markovic
wrote:
>
> From: Stefan Markovic
>
> Add emulation of nanoMIPS 16-bit branch instructions.
>
> Reviewed-by: Richard Henderson
> Signed-off-by: Yongbok Kim
> Signed-off-by: Aleksandar Markovic
> Signed-off-by: Stefan Markovic
> ---
> target/
On 5/29/21 3:52 PM, Philippe Mathieu-Daudé wrote:
> On Mon, Aug 20, 2018 at 8:17 PM Aleksandar Markovic
> wrote:
>>
>> From: Stefan Markovic
>>
>> Add emulation of nanoMIPS 16-bit branch instructions.
>>
>> Reviewed-by: Richard Henderson
>> Signed-off-by: Yongbok Kim
>> Signed-off-by: Aleksanda
If you have any patches you would like me to test out please send them to me.
Thank you.
> On May 27, 2021, at 11:13 AM, Programmingkid
> wrote:
>
> I have noticed that Windows 7 has stopped being able to boot recently. After
> doing some bisecting I found out it was this patch that is causin
Ping,
please implement this patch. The default icon on Mac OS 11 is not very good
looking.
https://lore.kernel.org/qemu-devel/20210202134410.9274-1-programmingk...@gmail.com/
Before switching the build system over to Meson, an icon was
added to the QEMU binary on Mac OS. This patch adds back
On 5/28/21 10:41 AM, Michael Morrell wrote:
I'm probably missing something, but why do we need both "float_flag_inorm_denormal" and
"float_flag_iflush_denormal"?
Couldn't the code that sets these flags set just a single flag for all denormal
inputs and the code that checks these flags check th
In this RFC patch series, I propose an initial cache modelling TCG
plugin. As of now, it models separate L1 data cache and L1 instruction
cache. It supports three eviction policies: LRU, random, and FIFO. Once
a policy is chosen, it's used for both instruction and data caches.
Mahmoud Mandour (3):
Now one of the three eviction policies can be chosen as an argument. On
not specifying an argument, LRU is used by default.
Signed-off-by: Mahmoud Mandour
---
contrib/plugins/cache.c | 159
1 file changed, 146 insertions(+), 13 deletions(-)
diff --git a/
Made both icache and dcache configurable through plugin arguments
and added memory trace printing in a separate file.
Signed-off-by: Mahmoud Mandour
---
contrib/plugins/cache.c | 68 +++--
1 file changed, 66 insertions(+), 2 deletions(-)
diff --git a/contrib/
Added a cache modelling plugin that uses a static configuration used in
many of the commercial microprocessors and uses random eviction policy.
Signed-off-by: Mahmoud Mandour
---
contrib/plugins/Makefile | 1 +
contrib/plugins/cache.c | 398 +++
2 files cha
Per the "MIPS® DSP Module for MIPS64 Architecture" manual, rev. 3.02,
Table 5.3 "SPECIAL3 Encoding of Function Field for DSP Module":
If the Module/ASE is not implemented, executing such an instruction
must cause a Reserved Instruction Exception.
The DINSV instruction lists the following exce
On Thu, 20 May 2021, Alexey Kardashevskiy wrote:
diff --git a/hw/ppc/spapr_vof.c b/hw/ppc/spapr_vof.c
new file mode 100644
index ..5e34d5402abf
--- /dev/null
+++ b/hw/ppc/spapr_vof.c
@@ -0,0 +1,156 @@
+/*
+ * SPAPR machine hooks to Virtual Open Firmware,
+ *
+ * SPDX-License-Identifie
From: Marc-André Lureau
The following changes since commit 62c0ac5041e9130b041adfa13a41583d3c3ddd24:
Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20210526' into
staging (2021-05-28 16:25:21 +0100)
are available in the Git repository at:
g...@github.com:elmarco/qemu.git t
From: Marc-André Lureau
Switch from stable-4.2 branch to upstream v4.5.0 release.
## [4.5.0] - 2021-05-18
### Added
- IPv6 forwarding. !62 !75 !77
- slirp_neighbor_info() to dump the ARP/NDP tables. !71
### Changed
- Lazy guest address resolution for IPv6. !81
- Improve signal handling w
From: Marc-André Lureau
Remove the manual build.
Moving projects to subprojects/ is required when using meson
subproject():
https://mesonbuild.com/Subprojects.html#why-must-all-subprojects-be-inside-a-single-directory
Tested-by: Joelle van Dyne
Signed-off-by: Marc-André Lureau
---
configure
On 5/29/21 9:54 AM, Philippe Mathieu-Daudé wrote:
Per the "MIPS® DSP Module for MIPS64 Architecture" manual, rev. 3.02,
Table 5.3 "SPECIAL3 Encoding of Function Field for DSP Module":
If the Module/ASE is not implemented, executing such an instruction
must cause a Reserved Instruction Exce
On 5/28/21 1:15 PM, Luis Fernando Fujita Pires wrote:
From: Richard Henderson
More completely, update the CPU state with any information that has been
assumed constant. For most guests, this is just the PC. But e.g. for hppa
this is both iaoq.f (cip) and iaoq.b (nip).
It is very much up to t
Hello i just saw the application you are developing from google summer of
code and i'm curious about it
what prerequisites that i need to learn so i can contribute in the
application
thanks in advance
Added a cache modelling plugin that uses a static configuration used in
many of the commercial microprocessors and uses random eviction policy.
Signed-off-by: Mahmoud Mandour
---
contrib/plugins/Makefile | 1 +
contrib/plugins/cache.c | 398 +++
2 files cha
Cc'ing Emilio too.
On 5/29/21 5:22 PM, Mahmoud Mandour wrote:
> In this RFC patch series, I propose an initial cache modelling TCG
> plugin. As of now, it models separate L1 data cache and L1 instruction
> cache. It supports three eviction policies: LRU, random, and FIFO. Once
> a policy is chosen
In this RFC patch series, I propose an initial cache modelling TCG
plugin. As of now, it models separate L1 data cache and L1 instruction
cache. It supports three eviction policies: LRU, random, and FIFO. Once
a policy is chosen, it's used for both instruction and data caches.
v1 -> v2: Unlocked d
Now one of the three eviction policies can be chosen as an argument. On
not specifying an argument, LRU is used by default.
Signed-off-by: Mahmoud Mandour
---
contrib/plugins/cache.c | 159
1 file changed, 146 insertions(+), 13 deletions(-)
diff --git a/
Made both icache and dcache configurable through plugin arguments
and added memory trace printing in a separate file.
Signed-off-by: Mahmoud Mandour
---
contrib/plugins/cache.c | 68 +++--
1 file changed, 66 insertions(+), 2 deletions(-)
diff --git a/contrib/
Thank you, I'll also CC Emilio in the v2 of this series.
On Sun, May 30, 2021 at 8:36 AM Philippe Mathieu-Daudé
wrote:
> Cc'ing Emilio too.
>
> On 5/29/21 5:22 PM, Mahmoud Mandour wrote:
> > In this RFC patch series, I propose an initial cache modelling TCG
> > plugin. As of now, it models separ
On Sun, May 30, 2021 at 8:37 AM Mahmoud Mandour
wrote:
> In this RFC patch series, I propose an initial cache modelling TCG
> plugin. As of now, it models separate L1 data cache and L1 instruction
> cache. It supports three eviction policies: LRU, random, and FIFO. Once
> a policy is chosen, it's
On 5/29/21 3:05 PM, Philippe Mathieu-Daudé wrote:
> Per the "MIPS® DSP Module for MIPS64 Architecture" manual (rev 3.02),
> Figure 5.12 "SPECIAL3 Encoding of APPEND/DAPPEND Instruction Sub-class"
> the byte position field ('bp') is 2 bits, not 3.
>
> Cc: Jia Liu
> Fixes: 26690560240 ("target-mips
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