On Fri, May 21, 2021 at 9:05 AM Markus Armbruster wrote:
>
> Eugenio Pérez writes:
>
> > Command to enable shadow virtqueue looks like:
> >
> > { "execute": "x-vhost-enable-shadow-vq",
> > "arguments": { "name": "dev0", "enable": true } }
> >
> > Signed-off-by: Eugenio Pérez
> > ---
> > qapi/
On Sun, May 23, 2021 at 07:09:26PM +0200, BALATON Zoltan wrote:
> On Sun, 23 May 2021, BALATON Zoltan wrote:
> > On Sun, 23 May 2021, Alexey Kardashevskiy wrote:
> > > One thing to note about PCI is that normally I think the client
> > > expects the firmware to do PCI probing and SLOF does it. But
On Thu, May 20, 2021 at 11:59:07PM +0200, BALATON Zoltan wrote:
> On Thu, 20 May 2021, Alexey Kardashevskiy wrote:
> > The PAPR platform describes an OS environment that's presented by
> > a combination of a hypervisor and firmware. The features it specifies
> > require collaboration between the fi
On Mon, May 24, 2021 at 02:26:42PM +1000, Alexey Kardashevskiy wrote:
>
>
> On 5/23/21 21:24, BALATON Zoltan wrote:
> > On Sun, 23 May 2021, Alexey Kardashevskiy wrote:
> > > On 23/05/2021 01:02, BALATON Zoltan wrote:
> > > > On Sat, 22 May 2021, BALATON Zoltan wrote:
> > > > > On Sat, 22 May 202
I also done a branch for current master from [RFC v3 00/13] s390x cleanup
https://gitlab.com/alcho.tw/qemu/-/tree/s390_cleanup_v4
and it's also built and test success passed through my CI:
https://gitlab.com/alcho.tw/qemu/-/pipelines/307149915
Cheers,
AL
Alex Bennée 於 2021年5月21日 週
On Sat, May 22, 2021 at 09:01:26AM +0530, Vaibhav Jain wrote:
> Thanks for looking into this patch David and Groug,
>
> David Gibson writes:
> > On Sat, May 15, 2021 at 01:07:59PM +0530, Vaibhav Jain wrote:
> >> Add support for H_SCM_PERFORMANCE_STATS described at [1] for
> >> spapr nvdimms. This
Ping?
On Tue, May 18, 2021 at 11:06 AM Ziqiao Kong wrote:
>
> On Tue, May 18, 2021 at 4:29 AM Eduardo Habkost wrote:
> >
> > Hi,
> >
> > Thanks for the patch, and apologies for not reviewing earlier
> > versions.
> >
>
> Nevermind, the earlier version is also hard to review without a proper spli
>From e55f890c11aea6e28e4b3cd5ef7f2496775f2a43 Mon Sep 17 00:00:00 2001
From: Xu Zou
Date: Mon, 24 May 2021 09:43:54 +0800
Subject: [PATCH] linux-user: Handle EXCP10_COPR properly for i386
Handle EXCP10_COPR properly for i386 in cpu loop.
NE flag is set to select the native mode for handling flo
Liang Li writes:
>> >> > Analyze events for all VMs, all VCPUs:
>> >> > VM-EXITSamples Samples% Time%Min TimeMax
>> >> > Time Avg time
>> >> > EXTERNAL_INTERRUPT 47183159.89%68.58% 0.64us
>> >> > 65.42us 2.34us ( +- 0.11% )
>> >> >
On Wed, May 19, 2021 at 06:28:34PM +0200, Eugenio Pérez wrote:
> Commit 17 introduces the buffer forwarding. Previous one are for
> preparations again, and laters are for enabling some obvious
> optimizations. However, it needs the vdpa device to be able to map
> every IOVA space, and some vDPA dev
On 21/05/21 15:44, Peter Maydell wrote:
What OS is it, and is there any chance of updating it? ninja 1.7 was
released in 2017, and I checked that all the supported OSes for QEMU
have 1.8 before sending the pull request.
It's the gcc compile farm's ppc64 box, whose /etc/redhat-release
says it's
On Mon, 24 May 2021 at 09:42, Jamie Iles wrote:
>
> The DAIF and PAC checks used raise_exception_ra to raise an exception
> and unwind CPU state but raise_exception_ra is currently designed for
> handling data aborts as the syndrome is partially precomputed and
> encoded in the TB and then merged
On Mon, 24 May 2021, David Gibson wrote:
On Thu, May 20, 2021 at 11:59:07PM +0200, BALATON Zoltan wrote:
On Thu, 20 May 2021, Alexey Kardashevskiy wrote:
The PAPR platform describes an OS environment that's presented by
a combination of a hypervisor and firmware. The features it specifies
requi
Commit 3ca1f3225727419ba573673b744edac10904276f
"block: BdrvChildClass: add .get_parent_aio_context handler" introduced
new handler and commit 228ca37e12f97788e05bd0c92f89b3e5e4019607
"block: drop ctx argument from bdrv_root_attach_child" made a generic
use of it. But 3ca1f3225727419ba573673b744eda
Hi!
As reported by Programmingkid, command
qemu-system-ppc -usb -device usb-storage,drive=fat16 -drive
file=fat:rw:fat-type=16:"",id=fat16,format=raw,if=none
crashes.
I tested it with qemu-system-x86_64 and it reproduces for me. I even
kept "" as is :).
So, here are two fixes.
Vladimir Seme
It's wrong to rely on s->qcow in vvfat_child_perm, as on permission
update during bdrv_open_child() call this field is not set yet.
Still prior to aa5a04c7db27eea6b36de32f241b155f0d9ce34d, it didn't
crash, as bdrv_open_child passed NULL as child to bdrv_child_perm(),
and NULL was equal to NULL in
On Fri, May 21, 2021 at 11:17:19AM +0200, Siddharth Chandrasekaran wrote:
> After a rebase to QEMU master, I am having trouble booting windows VMs.
> Git bisect indicates commit f5cc5a5c1686 ("i386: split cpu accelerators
> from cpu.c, using AccelCPUClass") to have introduced the issue. I spent
> s
On Mon, May 24, 2021 at 11:38 AM Michael S. Tsirkin wrote:
>
> On Wed, May 19, 2021 at 06:28:34PM +0200, Eugenio Pérez wrote:
> > Commit 17 introduces the buffer forwarding. Previous one are for
> > preparations again, and laters are for enabling some obvious
> > optimizations. However, it needs t
* Steven Sistare (steven.sist...@oracle.com) wrote:
> On 5/20/2021 9:13 AM, Dr. David Alan Gilbert wrote:
> > On the 'restart' branch of questions; can you explain,
> > other than the passing of the fd's, why the outgoing side of
> > qemu's 'migrate exec:' doesn't work for you?
>
> I'm not sure wh
This series adds support for using the Arm Memory Tagging Extensions
(MTE) in a KVM guest.
Changes since v12[1]:
* Use DEFINE_SPINLOCK() to define tag_sync_lock.
* Refactor mte_sync_tags() to take the old PTE value rather than a
pointer to the PTE. The checks in set_pte_at() are also streng
mte_sync_tags() used test_and_set_bit() to set the PG_mte_tagged flag
before restoring/zeroing the MTE tags. However if another thread were to
race and attempt to sync the tags on the same page before the first
thread had completed restoring/zeroing then it would see the flag is
already set and con
A new capability (KVM_CAP_ARM_MTE) identifies that the kernel supports
granting a guest access to the tags, and provides a mechanism for the
VMM to enable it.
A new ioctl (KVM_ARM_MTE_COPY_TAGS) provides a simple way for a VMM to
access the tags of a guest without having to maintain a PROT_MTE map
From: Catalin Marinas
Currently, on an anonymous page fault, the kernel allocates a zeroed
page and maps it in user space. If the mapping is tagged (PROT_MTE),
set_pte_at() additionally clears the tags under a spinlock to avoid a
race on the page->flags. In order to optimise the lock, clear the p
A KVM guest could store tags in a page even if the VMM hasn't mapped
the page with PROT_MTE. So when restoring pages from swap we will
need to check to see if there are any saved tags even if !pte_tagged().
However don't check pages for which pte_access_permitted() returns false
as these will not
Add a new VM feature 'KVM_ARM_CAP_MTE' which enables memory tagging
for a VM. This will expose the feature to the guest and automatically
tag memory pages touched by the VM as PG_mte_tagged (and clear the tag
storage) to ensure that the guest cannot see stale tags, and so that
the tags are correctl
It's now safe for the VMM to enable MTE in a guest, so expose the
capability to user space.
Signed-off-by: Steven Price
---
arch/arm64/kvm/arm.c | 9 +
arch/arm64/kvm/reset.c| 3 ++-
arch/arm64/kvm/sys_regs.c | 3 +++
3 files changed, 14 insertions(+), 1 deletion(-)
diff --git
Define the new system registers that MTE introduces and context switch
them. The MTE feature is still hidden from the ID register as it isn't
supported in a VM yet.
Signed-off-by: Steven Price
---
arch/arm64/include/asm/kvm_host.h | 6 ++
arch/arm64/include/asm/kvm_mte.h | 68
The VMM may not wish to have it's own mapping of guest memory mapped
with PROT_MTE because this causes problems if the VMM has tag checking
enabled (the guest controls the tags in physical RAM and it's unlikely
the tags are correct for the VMM).
Instead add a new ioctl which allows the VMM to easi
YAMAMOTO Takashi writes:
> It seems somehow common to execve /proc/self/exe in docker
> or golang community these days.
> At least, moby "reexec" and runc "libcontainer" do that.
>
> Signed-off-by: YAMAMOTO Takashi
> ---
> linux-user/syscall.c | 7 ++-
> 1 file changed, 6 insertions(+), 1
On Mon, 24 May 2021, David Gibson wrote:
On Sun, May 23, 2021 at 07:09:26PM +0200, BALATON Zoltan wrote:
On Sun, 23 May 2021, BALATON Zoltan wrote:
On Sun, 23 May 2021, Alexey Kardashevskiy wrote:
One thing to note about PCI is that normally I think the client
expects the firmware to do PCI pr
LXD developers have reported that [object] stanzas have stopped
working in configuration files.
The problem is that QEMU 6.0 switched the creation of objects from
qemu_opts_foreach to a bespoke QTAILQ, in preparation for supporting
JSON syntax in -object. Entries from the configuration file howev
Change the parser to put the values into a QDict and pass them
to a callback. qemu_config_parse's QemuOpts creation is
itself turned into a callback function.
This is useful for -readconfig to support keyval-based options;
getting a QDict from the parser removes a roundtrip from
QDict to QemuOpts
Let -readconfig support parsing command line options into QDict or
QemuOpts. This will be used to add back support for objects in
-readconfig.
Cc: Markus Armbruster
Cc: qemu-sta...@nongnu.org
Reviewed-by: Kevin Wolf
Signed-off-by: Paolo Bonzini
---
v1->v2: fix overlong line
include/block/qdi
YAMAMOTO Takashi writes:
> Otherwise, it can be easily fooled by the user app using chdir().
>
> Signed-off-by: YAMAMOTO Takashi
> ---
> linux-user/main.c | 6 +-
> 1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/linux-user/main.c b/linux-user/main.c
> index 4dfc47ad3b..1f
Commit bc2f4fcb1d ("qom: move user_creatable_add_opts logic to vl.c
and QAPIfy it", 2021-03-19) switched the creation of objects from
qemu_opts_foreach to a bespoke QTAILQ in preparation for supporting JSON
syntax in -object.
Unfortunately in doing so it lost support for [object] stanzas in
config
I'm not sure if this is neater than the original code but it does
remove a bunch of the !strcmp's in favour of glib's more natural bool
results. While we are at it make the function a bool return and fixup
the fake_open function prototypes.
Signed-off-by: Alex Bennée
---
linux-user/syscall.c | 3
Patchew URL:
https://patchew.org/QEMU/20210524112323.2310-1-alex.ben...@linaro.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20210524112323.2310-1-alex.ben...@linaro.org
Subject: [RFC PATCH] linux-user: glib-ify
On Mon, May 24, 2021 at 12:37:48PM +0200, Eugenio Perez Martin wrote:
> On Mon, May 24, 2021 at 11:38 AM Michael S. Tsirkin wrote:
> >
> > On Wed, May 19, 2021 at 06:28:34PM +0200, Eugenio Pérez wrote:
> > > Commit 17 introduces the buffer forwarding. Previous one are for
> > > preparations again,
On Mon, May 24, 2021 at 12:23:23PM +0100, Alex Bennée wrote:
> I'm not sure if this is neater than the original code but it does
> remove a bunch of the !strcmp's in favour of glib's more natural bool
> results. While we are at it make the function a bool return and fixup
> the fake_open function p
Distros have started using the 'scv' instructions (glibc 2.33) which
relies on the LPCR AIL bits. Unfortunately, the LPCR of hot-plugged
CPUs is not synchronized with the rest of machine and it breaks the
guest OS.
Fix that by using the first CPU to set the LPCR value of all hot-plugged
CPUs.
Sig
On Mon, 24 May 2021, David Gibson wrote:
On Mon, May 17, 2021 at 02:17:36PM +0200, BALATON Zoltan wrote:
On Mon, 17 May 2021, Alexey Kardashevskiy wrote:
On 5/16/21 01:04, BALATON Zoltan wrote:
On Thu, 22 Apr 2021, Alexey Kardashevskiy wrote:
[snip]
+/* Defined as Big Endian */
+struct pro
On Mon, 24 May 2021, David Gibson wrote:
On Mon, May 24, 2021 at 02:26:42PM +1000, Alexey Kardashevskiy wrote:
On 5/23/21 21:24, BALATON Zoltan wrote:
On Sun, 23 May 2021, Alexey Kardashevskiy wrote:
On 23/05/2021 01:02, BALATON Zoltan wrote:
On Sat, 22 May 2021, BALATON Zoltan wrote:
On Sat
Eduardo Habkost writes:
> On Thu, Apr 22, 2021 at 06:11:21PM +0200, Vitaly Kuznetsov wrote:
>> hyperv_expand_features() will be called before we create vCPU so
>> evmcs enablement should go away. hyperv_init_vcpu() looks like the
>> right place.
>>
>> Signed-off-by: Vitaly Kuznetsov
>> ---
>>
Eduardo Habkost writes:
> On Thu, Apr 22, 2021 at 06:11:22PM +0200, Vitaly Kuznetsov wrote:
>> Use standard error_setg() mechanism in hyperv_expand_features().
>>
>> Signed-off-by: Vitaly Kuznetsov
>
> No objections, but only suggestions below:
>
>> ---
>> target/i386/kvm/kvm.c | 101 +
On 5/20/21 6:02 PM, Alex Bennée wrote:
>
> Claudio Fontana writes:
>
>> On 5/18/21 4:02 PM, Alex Bennée wrote:
>>>
>>> Claudio Fontana writes:
>>>
On 5/17/21 11:53 AM, Claudio Fontana wrote:
> Hello all,
>
> due to my inactivity for a few weeks coupled likely with the upstream
Eduardo Habkost writes:
> On Thu, Apr 22, 2021 at 06:11:24PM +0200, Vitaly Kuznetsov wrote:
>> KVM_GET_SUPPORTED_HV_CPUID was made a system wide ioctl which can be called
>> prior to creating vCPUs and we are going to use that to expand Hyper-V cpu
>> features early. Use it when it is supported b
Eduardo Habkost writes:
> On Thu, Apr 22, 2021 at 06:11:26PM +0200, Vitaly Kuznetsov wrote:
>> To make Hyper-V features appear in e.g. QMP query-cpu-model-expansion we
>> need to expand and set the corresponding CPUID leaves early. Modify
>> x86_cpu_get_supported_feature_word() to call newly into
Eduardo Habkost writes:
> On Thu, Apr 22, 2021 at 06:11:27PM +0200, Vitaly Kuznetsov wrote:
>> hv_cpuid_check_and_set() does too much:
>> - Checks if the feature is supported by KVM;
>> - Checks if all dependencies are enabled;
>> - Sets the feature bit in cpu->hyperv_features for 'passthrough' m
On 24/05/2021 00:26, David Gibson wrote:
On Wed, May 19, 2021 at 05:47:05PM -0500, Richard Henderson wrote:
On 5/19/21 3:37 PM, Richard Henderson wrote:
On 5/18/21 9:52 PM, David Gibson wrote:
I've applied 1..15, still looking at the rest.
Please dequeue. I want to create a new mmu-internal
Eduardo Habkost writes:
> On Thu, Apr 22, 2021 at 06:11:28PM +0200, Vitaly Kuznetsov wrote:
>> According to TLFS, Hyper-V guest is supposed to check
>> HV_HYPERCALL_AVAILABLE privilege bit before accessing
>> HV_X64_MSR_GUEST_OS_ID/HV_X64_MSR_HYPERCALL MSRs but at least some
>> Windows versions i
Here's a draft schedule for the 6.1 cycle:
2021-07-13 Soft feature freeze. Only bug fixes after this point.
2021-07-20 Hard feature freeze. Tag rc0
2021-07-27 Tag rc1
2021-08-03 Tag rc2
2021-08-10 Tag rc3
2021-08-17 Release; or tag rc4 if needed
2021-08-24 Release if we needed an rc4
I don't thin
On Mon, 24 May 2021, David Gibson wrote:
On Sun, May 23, 2021 at 07:09:26PM +0200, BALATON Zoltan wrote:
On Sun, 23 May 2021, BALATON Zoltan wrote:
On Sun, 23 May 2021, Alexey Kardashevskiy wrote:
One thing to note about PCI is that normally I think the client
expects the firmware to do PCI pr
On 24/05/2021 20:55, BALATON Zoltan wrote:
On Mon, 24 May 2021, David Gibson wrote:
On Sun, May 23, 2021 at 07:09:26PM +0200, BALATON Zoltan wrote:
On Sun, 23 May 2021, BALATON Zoltan wrote:
On Sun, 23 May 2021, Alexey Kardashevskiy wrote:
One thing to note about PCI is that normally I thi
On 24/05/2021 00:02, David Gibson wrote:
On Fri, May 21, 2021 at 05:17:58PM -0300, Bruno Larsen (billionai) wrote:
Created a file with stubs needed to compile disabling TCG. *_ppc_opcodes
were created to make cpu_init.c have a few less ifdefs, since they are
not needed. coftmmu_resize_hpt_* hav
11.05.2021 22:22, Eric Blake wrote:
On 3/24/21 3:51 PM, Vladimir Sementsov-Ogievskiy wrote:
We are going to convert .bdrv_co_preadv_part and .bdrv_co_pwritev_part
to int64_t type for offset and bytes parameters (as it's already done
for generic block/io.c layer).
In qcow2 .bdrv_co_preadv_part i
The following changes since commit 6c769690ac845fa62642a5f93b4e4bd906adab95:
Merge remote-tracking branch
'remotes/vsementsov/tags/pull-simplebench-2021-05-04' into staging (2021-05-21
12:02:34 +0100)
are available in the Git repository at:
https://gitlab.com/stefanha/qemu.git tags/block-p
From: Paolo Bonzini
Simplify the code by removing conditionals. qemu_co_sleep_ns
can simply point the argument to an on-stack temporary.
Reviewed-by: Vladimir Sementsov-Ogievskiy
Signed-off-by: Paolo Bonzini
Message-id: 20210517100548.28806-3-pbonz...@redhat.com
Signed-off-by: Stefan Hajnoczi
From: Zenghui Yu
Quote docs/devel/style.rst (section "Automatic memory deallocation"):
* Variables declared with g_auto* MUST always be initialized,
otherwise the cleanup function will use uninitialized stack memory
Initialize @name properly to get rid of the compilation error (using
gcc-7.3.
From: Zenghui Yu
Quote docs/devel/style.rst (section "Automatic memory deallocation"):
* Variables declared with g_auto* MUST always be initialized,
otherwise the cleanup function will use uninitialized stack memory
Initialize @name properly to get rid of the compilation error (using
gcc-7.3.
The following changes since commit 6c769690ac845fa62642a5f93b4e4bd906adab95:
Merge remote-tracking branch
'remotes/vsementsov/tags/pull-simplebench-2021-05-04' into staging (2021-05-21
12:02:34 +0100)
are available in the Git repository at:
https://gitlab.com/stefanha/qemu.git tags/block-p
From: Philippe Mathieu-Daudé
Document the following functions return the bitmap size
if no matching bit is found:
- find_first_bit
- find_next_bit
- find_last_bit
- find_first_zero_bit
- find_next_zero_bit
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Stefa
From: Paolo Bonzini
The lifetime of the timer is well-known (it cannot outlive
qemu_co_sleep_ns_wakeable, because it's deleted by the time the
coroutine resumes), so it is not necessary to place it on the heap.
Reviewed-by: Vladimir Sementsov-Ogievskiy
Signed-off-by: Paolo Bonzini
Message-id:
From: Paolo Bonzini
Allow using QemuCoSleep to sleep forever until woken by qemu_co_sleep_wake.
This makes the logic of qemu_co_sleep_ns_wakeable easy to understand.
In the future we will introduce an API that can work even if the
sleep and wake happen from different threads. For now, initializ
From: Paolo Bonzini
All callers of qemu_co_sleep_wake are checking whether they are passing
a NULL argument inside the pointer-to-pointer: do the check in
qemu_co_sleep_wake itself.
As a side effect, qemu_co_sleep_wake can be called more than once and
it will only wake the coroutine once; after
From: Paolo Bonzini
This simplification is enabled by the previous patch. Now aio_co_wake
will only be called once, therefore we do not care about a spurious
firing of the timer after a qemu_co_sleep_wake.
Reviewed-by: Vladimir Sementsov-Ogievskiy
Signed-off-by: Paolo Bonzini
Message-id: 2021
From: Paolo Bonzini
Right now, users of qemu_co_sleep_ns_wakeable are simply passing
a pointer to QemuCoSleepState by reference to the function. But
QemuCoSleepState really is just a Coroutine*; making the
content of the struct public is just as efficient and lets us
skip the user_state_pointer
Please ignore. I resent the pull request with the proper subject line
and CC list.
Stefan
signature.asc
Description: PGP signature
On Mon, 24 May 2021 at 13:36, Jamie Iles wrote:
> On Mon, May 24, 2021 at 10:41:58AM +0100, Peter Maydell wrote:
> > raise_exception() and raise_exception_ra() are supposed to have
> > the same semantics apart from one of them being passed a return
> > address. So perhaps we should look at trying
On Mon, May 24, 2021 at 11:57:27AM +0200, BALATON Zoltan wrote:
> On Mon, 24 May 2021, David Gibson wrote:
> > On Thu, May 20, 2021 at 11:59:07PM +0200, BALATON Zoltan wrote:
> > > On Thu, 20 May 2021, Alexey Kardashevskiy wrote:
> > > > The PAPR platform describes an OS environment that's presente
The pointer auth properties are added to the max CPU type but the
finalization happens for all CPUs. It makes sense to be able to disable
pointer authentication for the max CPU type, but for future CPUs that
implement pointer authentication and have bits set in ID_AA64ISAR1,
don't clobber them unl
The DAIF and PAC checks used raise_exception_ra to raise an exception
and unwind CPU state but raise_exception_ra is currently designed for
handling data aborts as the syndrome is partially precomputed and
encoded in the TB and then merged in merge_syn_data_abort when handling
the data abort. Usin
Hi Peter,
On Mon, May 24, 2021 at 10:41:58AM +0100, Peter Maydell wrote:
> On Mon, 24 May 2021 at 09:42, Jamie Iles wrote:
> >
> > The DAIF and PAC checks used raise_exception_ra to raise an exception
> > and unwind CPU state but raise_exception_ra is currently designed for
> > handling data abor
On Sat, May 22, 2021 at 12:32:00AM +0530, Niteesh G. S. wrote:
> By end of this summer, I would like to get a basic TUI with some desirable
> features working. Some of the features I would like to get working are
> 1) Syntax checking
> 2) Syntax highlighting
> 3) Code completion
> 4) Logging
>
> I
Daniel P. Berrangé writes:
> On Mon, May 24, 2021 at 12:23:23PM +0100, Alex Bennée wrote:
>> I'm not sure if this is neater than the original code but it does
>> remove a bunch of the !strcmp's in favour of glib's more natural bool
>> results. While we are at it make the function a bool return
On 5/20/21 6:09 AM, Peter Maydell wrote:
When an M-profile CPU is restoring registers from the stack on
exception return, the stack pointer to use is determined based on
bits in the magic exception return type value. We were not getting
this logic entirely correct.
Whether we use one of the Sec
On 5/10/21 12:08 PM, Peter Maydell wrote:
The SRAM at 0x2000_ is part of the SSE-200 itself, and we model
it that way in hw/arm/armsse.c (along with the associated MPCs). We
incorrectly also added an entry to the RAMInfo array for the AN524 in
hw/arm/mps2-tz.c, which was pointless because th
On 5/10/21 12:08 PM, Peter Maydell wrote:
The AN547 sets the SRAM_ADDR_WIDTH for the SSE-300 to 21;
since this is not the default value for the SSE-300, model this
in mps2-tz.c as a per-board value.
Reported-by: Devaraj Ranganna
Signed-off-by: Peter Maydell
---
hw/arm/mps2-tz.c | 6 ++
1
On Fri, May 21, 2021 at 01:52:13PM +0100, Daniel P. Berrangé wrote:
> On Fri, May 21, 2021 at 02:27:26PM +0200, Philippe Mathieu-Daudé wrote:
> > On 5/21/21 1:53 PM, Daniel P. Berrangé wrote:
> > > On Fri, May 21, 2021 at 01:02:51PM +0200, Thomas Huth wrote:
> > >> On 21/05/2021 12.50, Daniel P. Be
On 5/10/21 12:08 PM, Peter Maydell wrote:
The SSE-300 was not correctly modelling its internal SRAMs:
* the SRAM address width default is 18
* the SRAM is mapped at 0x2100_, not 0x2000_ like
the SSE-200 and IoTKit
The default address width is no longer guest-visible since
our onl
On 5/10/21 12:08 PM, Peter Maydell wrote:
Convert armsse_realize() to use ERRP_GUARD(), following
the rules in include/qapi/error.h.
Signed-off-by: Peter Maydell
---
We'll be adding a new error check in the next patch, so
do this first to avoid adding more uses of legacy
error_propagate().
---
This patch series finishes the the changes required to support disabling
TCG for ppc targets.
With the current version of the patch, the project compiles and runs ok,
but we need some more testing to ensure that no regressions happened,
especially with relation to gdb.
Based-on: <20210521201759.8
Moved the ppc_cpu_do_interrupt function to cpu.c file, where it makes
more sense, and turned powerpc_excp not static, as it now needs to be
accessed from outside of excp_helper.c
Signed-off-by: Bruno Larsen (billionai)
---
target/ppc/cpu.c | 20
target/ppc/cpu.h
excp_helper.c, mmu-hash64.c and mmu_helper.c have some function
declarations that are TCG-only, and couldn't be easily moved to a
TCG only file, so ifdefs were added around them.
We also needed ifdefs around some header files because helper-proto.h
includes trace/generated-helpers.h, which is neve
The write calback decision when registering the MAS SPR has been turned
into a ternary operation, rather than an if-then-else block.
Signed-off-by: Bruno Larsen (billionai)
Suggested-by: Richard Henderson
---
target/ppc/cpu_init.c | 9 +++--
1 file changed, 3 insertions(+), 6 deletions(-)
Created a file with stubs needed to compile disabling TCG. *_ppc_opcodes
were created to make cpu_init.c have a few less ifdefs, since they are
not needed. coftmmu_resize_hpt_* have to be created because the compiler
can't automatically know they aren't used, but they should never be
reached.
Sign
15.05.2021 01:38, John Snow wrote:
On 5/6/21 5:57 AM, Kashyap Chamarthy wrote:
TODO: We also need to deprecate drive-backup transaction action..
But union members in QAPI doesn't support 'deprecated' feature. I tried
to dig a bit, but failed :/ Markus, could you please help with it? At
least by
updated build file to not compile some sources that are unnecessary if
TCG is disabled on the system.
Signed-off-by: Bruno Larsen (billionai)
---
target/ppc/meson.build | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/target/ppc/meson.build b/target/ppc/meson.build
inde
Hi all!
Here are some good refactorings and new (qemu-img check) checks for
qcow2.
v3: add r-b mark by Alberto and t-b marks by Kirill
07, 09: add missed "\n"
Vladimir Sementsov-Ogievskiy (10):
qcow2-refcount: improve style of check_refcounts_l2()
qcow2: compressed read: simplify cluster de
- don't use same name for size in bytes and in entries
- use g_autofree for l2_table
- add whitespace
- fix block comment style
Signed-off-by: Vladimir Sementsov-Ogievskiy
Reviewed-by: Eric Blake
---
block/qcow2-refcount.c | 47 +-
1 file changed, 24
Let's pass the whole L2 entry and not bother with
L2E_COMPRESSED_OFFSET_SIZE_MASK.
It also helps further refactoring that adds generic
qcow2_parse_compressed_l2_entry() helper.
Signed-off-by: Vladimir Sementsov-Ogievskiy
Reviewed-by: Eric Blake
Reviewed-by: Alberto Garcia
---
block/qcow2.h
Split fix_l2_entry_by_zero() out of check_refcounts_l2() to be
reused in further patch.
Signed-off-by: Vladimir Sementsov-Ogievskiy
Reviewed-by: Eric Blake
---
block/qcow2-refcount.c | 87 +-
1 file changed, 60 insertions(+), 27 deletions(-)
diff --git a
Add helper to parse compressed l2_entry and use it everywhere instead
of open-coding.
Note, that in most places we move to precise coffset/csize instead of
sector-aligned. Still it should work good enough for updating
refcounts.
Signed-off-by: Vladimir Sementsov-Ogievskiy
Reviewed-by: Eric Blake
Signed-off-by: Vladimir Sementsov-Ogievskiy
Reviewed-by: Eric Blake
Tested-by: Kirill Tkhai
---
block/qcow2.h | 1 +
block/qcow2-refcount.c | 6 ++
2 files changed, 7 insertions(+)
diff --git a/block/qcow2.h b/block/qcow2.h
index b8b1093b61..58fd7f1678 100644
--- a/block/qcow2.h
+
Ping. Now based on master
04.05.2021 12:45, Vladimir Sementsov-Ogievskiy wrote:
v2: rebased on Kevin's "[PATCH 0/2] block: Fix Transaction leaks"
1: add assertions and drop extra declaration
2: add Alberto's r-b
3: improve commit message
Based-on: <20210503110555.24001-1-kw...@redhat.com>
Vlad
We'll reuse the function to fix wrong L2 entry bitmap. Support it now.
Signed-off-by: Vladimir Sementsov-Ogievskiy
Reviewed-by: Eric Blake
---
block/qcow2-refcount.c | 18 +++---
1 file changed, 15 insertions(+), 3 deletions(-)
diff --git a/block/qcow2-refcount.c b/block/qcow2-refc
Check subcluster bitmap of the l2 entry for different types of
clusters:
- for compressed it must be zero
- for allocated check consistency of two parts of the bitmap
- for unallocated all subclusters should be unallocated
(or zero-plain)
For unallocated clusters we can safely fix the entry
Signed-off-by: Vladimir Sementsov-Ogievskiy
Reviewed-by: Eric Blake
Tested-by: Kirill Tkhai
---
block/qcow2.h | 1 +
block/qcow2-refcount.c | 12 +++-
2 files changed, 12 insertions(+), 1 deletion(-)
diff --git a/block/qcow2.h b/block/qcow2.h
index c0e1e83796..b8b1093b61 1006
Split checking for reserved bits out of aligned offset check.
Signed-off-by: Vladimir Sementsov-Ogievskiy
Reviewed-by: Eric Blake
Tested-by: Kirill Tkhai
---
block/qcow2.h | 1 +
block/qcow2-refcount.c | 10 +-
2 files changed, 10 insertions(+), 1 deletion(-)
diff --git a/bl
- use g_autofree for l1_table
- better name for size in bytes variable
- reduce code blocks nesting
- whitespaces, braces, newlines
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
block/qcow2-refcount.c | 98 +-
1 file changed, 50 insertions(+), 48 del
On 5/10/21 12:08 PM, Peter Maydell wrote:
Currently we model the ITCM in the AN547's RAMInfo list. This is incorrect
because this RAM is really a part of the SSE-300. We can't just delete
it from the RAMInfo list, though, because this would make boot_ram_size()
assert because it wouldn't be able
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