Enrico, with security_model=mapped (a.k.a. security_model=mapped-xattr)
9p is not following symlinks on host. That's the expected behaviour.
There are 2 distinct models:
security_model=passthrough uses the ownership information, permissions
and symlink info etc. directly from the host's file syst
On 28/04/2021 13:50, Philippe Mathieu-Daudé wrote:
Hi,
The floppy disc controllers pulls in irrelevant devices (sysbus in
an ISA-only machine, ISA bus + isa devices on a sysbus-only machine).
This series clean that by extracting each device in its own file,
adding the corresponding Kconfig sym
On 28/04/2021 15:16, Philippe Mathieu-Daudé wrote:
Missing review: 2-4
Since v1:
- move cpu_check_irqs() to target/sparc/ (rth)
This series fixes link failure when building either the leon3
machine or the sun4m ones.
The problem is we have hardware specific code in the architectural
translati
On 22/04/2021 16.59, Philippe Mathieu-Daudé wrote:
When building on Fedora 34 (gcc version 11.0.0 20210210) we get:
In file included from pc-bios/s390-ccw/main.c:11:
In function ‘memset’,
inlined from ‘boot_setup’ at pc-bios/s390-ccw/main.c:185:5,
inlined from ‘main’ at pc-bi
On 02/05/2021 12.39, Thomas Huth wrote:
On 22/04/2021 16.59, Philippe Mathieu-Daudé wrote:
When building on Fedora 34 (gcc version 11.0.0 20210210) we get:
In file included from pc-bios/s390-ccw/main.c:11:
In function ‘memset’,
inlined from ‘boot_setup’ at pc-bios/s390-ccw/main.c:1
The cc-option macro is not doing what it should - compared with the
original from the rules.mak file that got removed with commit
660f793093 ("Makefile: inline the relevant parts of rules.mak"),
the arguments got changed and thus the macro is rather doubling
the QEMU_CFLAGS than adding the flag tha
On 07/04/2021 18:53, Philippe Mathieu-Daudé wrote:
Hi Mark,
This series QOM'ify a bit more the sun4m machines.
I need it for a further memory maxsize check.
It is mostly code movement (and the diff-stat is good).
Philippe Mathieu-Daudé (3):
hw/sparc/sun4m: Introduce TYPE_SUN4M_MACHINE and S
On Sat, 1 May 2021 at 19:51, Richard Henderson
wrote:
>
> The following changes since commit 8f860d2633baf9c2b6261f703f86e394c6bc22ca:
>
> Merge remote-tracking branch 'remotes/armbru/tags/pull-qapi-2021-04-30'
> into staging (2021-04-30 16:02:00 +0100)
>
> are available in the Git repository a
Starting from ceph Pacific, RBD has built-in support for image-level encryption.
Currently supported formats are LUKS version 1 and 2.
There are 2 new relevant librbd APIs for controlling encryption, both expect an
open image context:
rbd_encryption_format: formats an image (i.e. writes the LUKS
On 5/1/21 6:37 PM, Guenter Roeck wrote:
> On 5/1/21 5:24 PM, Bin Meng wrote:
>> On Sun, May 2, 2021 at 7:21 AM Guenter Roeck wrote:
>>>
>>> On 5/1/21 2:40 PM, Philippe Mathieu-Daudé wrote:
On 5/1/21 10:12 PM, Guenter Roeck wrote:
> On 4/30/21 9:28 PM, Bin Meng wrote:
>> On Fri, Apr 30
Patchew URL: https://patchew.org/QEMU/20210502073617.2978836-1-...@il.ibm.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20210502073617.2978836-1-...@il.ibm.com
Subject: [PATCH] block/rbd: Add support for rbd image
After doing tests with Windows 95, 3,1, NT 4.0, and 2000 I can say this
bug appears to be fixed.
** Changed in: qemu
Status: Incomplete => Fix Released
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From: Taylor Simpson
Change cpu_ldl_code to translator_ldl.
Don't end the TB after every packet when HEX_DEBUG is on.
Make gen_check_store_width a simple call.
Reported-by: Richard Henderson <
Signed-off-by: Taylor Simpson
Message-Id: <1615783984-25918-1-git-send-email-tsimp...@quicinc.com>
Sig
The following changes since commit 8f860d2633baf9c2b6261f703f86e394c6bc22ca:
Merge remote-tracking branch 'remotes/armbru/tags/pull-qapi-2021-04-30' into
staging (2021-04-30 16:02:00 +0100)
are available in the Git repository at:
https://gitlab.com/rth7680/qemu.git tags/pull-he
From: Taylor Simpson
Multiple writes to the same preg are and'ed together. Rather than
generating a runtime check, we can determine at TCG generation time
if the predicate has previously been written in the packet.
Test added to tests/tcg/hexagon/misc.c
Suggested-by: Richard Henderson
Signed-
From: Taylor Simpson
When exiting a TB, generate all the code before returning from
hexagon_tr_translate_packet so that nothing needs to be done in
hexagon_tr_tb_stop.
Suggested-by: Richard Henderson
Signed-off-by: Taylor Simpson
Reviewed-by: Richard Henderson
Message-Id: <1617930474-31979-6-
From: Taylor Simpson
Reported-by: Richard Henderson <
Signed-off-by: Taylor Simpson
Message-Id: <1615784037-26129-1-git-send-email-tsimp...@quicinc.com>
Signed-off-by: Richard Henderson
---
target/hexagon/iclass.c | 4
1 file changed, 4 deletions(-)
diff --git a/target/hexagon/iclass.c b
From: Taylor Simpson
Suggested-by: Richard Henderson
Signed-off-by: Taylor Simpson
Reviewed-by: Richard Henderson
Message-Id: <1617930474-31979-11-git-send-email-tsimp...@quicinc.com>
Signed-off-by: Richard Henderson
---
target/hexagon/cpu.c | 5
target/hexagon/op_helper.c
From: Taylor Simpson
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Taylor Simpson
Message-Id: <1615784115-26559-1-git-send-email-tsimp...@quicinc.com>
Signed-off-by: Richard Henderson
---
target/hexagon/op_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/targe
From: Taylor Simpson
Suggested-by: Richard Henderson
Signed-off-by: Taylor Simpson
Reviewed-by: Richard Henderson
Message-Id: <1617930474-31979-9-git-send-email-tsimp...@quicinc.com>
Signed-off-by: Richard Henderson
---
target/hexagon/arch.h | 1 -
target/hexagon/macros.h | 2 --
target/
From: Taylor Simpson
Suggested-by: Richard Henderson
Signed-off-by: Taylor Simpson
Reviewed-by: Richard Henderson
Message-Id: <1617930474-31979-4-git-send-email-tsimp...@quicinc.com>
Signed-off-by: Richard Henderson
---
target/hexagon/cpu.c | 9 -
target/hexagon/decode.c|
From: Taylor Simpson
Include size in declaration
Remove {0, 0} entry
Suggested-by: Richard Henderson
Signed-off-by: Taylor Simpson
Reviewed-by: Richard Henderson
Message-Id: <1617930474-31979-15-git-send-email-tsimp...@quicinc.com>
Signed-off-by: Richard Henderson
---
target/hexagon/reg_fie
From: Taylor Simpson
Reviewed-by: Philippe Mathieu-Daudé
Reported-by: Richard Henderson <
Signed-off-by: Taylor Simpson
Message-Id: <1615784100-26459-1-git-send-email-tsimp...@quicinc.com>
Signed-off-by: Richard Henderson
---
target/hexagon/gen_tcg.h | 4 ++--
1 file changed, 2 insertions(+),
From: Taylor Simpson
Suggested-by: Richard Henderson
Signed-off-by: Taylor Simpson
Reviewed-by: Richard Henderson
Message-Id: <1617930474-31979-12-git-send-email-tsimp...@quicinc.com>
Signed-off-by: Richard Henderson
---
target/hexagon/arch.c | 28 +++-
1 file changed
From: Taylor Simpson
Reported-by: Richard Henderson <
Signed-off-by: Taylor Simpson
Message-Id: <1615784049-26215-1-git-send-email-tsimp...@quicinc.com>
Signed-off-by: Richard Henderson
---
target/hexagon/decode.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/h
From: Taylor Simpson
Rd32,Pe4 = sfinvsqrta(Rs32)
Square root approx
The helper packs the 2 32-bit results into a 64-bit value,
and the fGEN_TCG override unpacks them into the proper results.
Test cases in tests/tcg/hexagon/multi_result.c
FP exception tests added to tests/tcg/hexagon/fpstuff
From: Taylor Simpson
Similar to previous cleanup of gen_log_predicated_reg_write
Signed-off-by: Taylor Simpson
Reviewed-by: Richard Henderson
Message-Id: <1617930474-31979-3-git-send-email-tsimp...@quicinc.com>
Signed-off-by: Richard Henderson
---
target/hexagon/genptr.c | 27 +--
From: Taylor Simpson
Use the proper return for helpers that convert to unsigned
Remove target/hexagon/conv_emu.[ch]
Suggested-by: Richard Henderson
Signed-off-by: Taylor Simpson
Reviewed-by: Richard Henderson
Message-Id: <1617930474-31979-13-git-send-email-tsimp...@quicinc.com>
Signed-off-by:
From: Taylor Simpson
Simplify TCG generation of hex_reg_written
Suggested-by: Richard Henderson
Signed-off-by: Taylor Simpson
Reviewed-by: Richard Henderson
Message-Id: <1617930474-31979-2-git-send-email-tsimp...@quicinc.com>
Signed-off-by: Richard Henderson
---
target/hexagon/genptr.c | 14
From: Taylor Simpson
Rxx32,Pe4 = vacsh(Rss32, Rtt32)
Add compare and select elements of two vectors
Test cases in tests/tcg/hexagon/multi_result.c
Signed-off-by: Taylor Simpson
Reviewed-by: Richard Henderson
Message-Id: <1617930474-31979-20-git-send-email-tsimp...@quicinc.com>
Signed-off-
From: Taylor Simpson
Remove hexagon_env_get_cpu and replace with env_archcpu
Replace CPU(hexagon_env_get_cpu(env)) with env_cpu(env)
Suggested-by: Richard Henderson
Signed-off-by: Taylor Simpson
Reviewed-by: Richard Henderson
Message-Id: <1617930474-31979-5-git-send-email-tsimp...@quicinc.com
From: Taylor Simpson
Change #if HEX_DEBUG to if (HEX_DEBUG) so the debug code doesn't bit rot
Suggested-by: Philippe Mathieu-Daudé
Signed-off-by: Taylor Simpson
Reviewed-by: Richard Henderson
Message-Id: <1617930474-31979-17-git-send-email-tsimp...@quicinc.com>
Signed-off-by: Richard Henderso
From: Taylor Simpson
Change (cond ? (res = x) : (res = y)) to res = (cond ? x : y)
This makes the semnatics easier to for idef-parser to deal with
The following instructions are impacted
C2_any8
C2_all8
C2_mux
C2_muxii
C2_muxir
C2_muxri
Signed-off-by: Taylor Simpson
R
From: Taylor Simpson
The following instructions are added
L2_loadrub_pbr Rd32 = memub(Rx32++Mu2:brev)
L2_loadrb_pbr Rd32 = memb(Rx32++Mu2:brev)
L2_loadruh_pbr Rd32 = memuh(Rx32++Mu2:brev)
L2_loadrh_pbr Rd32 = memh(Rx32++Mu2:brev)
L2_loadri
From: Taylor Simpson
Suggested-by: Richard Henderson
Signed-off-by: Taylor Simpson
Reviewed-by: Richard Henderson
Message-Id: <1617930474-31979-10-git-send-email-tsimp...@quicinc.com>
Signed-off-by: Richard Henderson
---
target/hexagon/arch.c | 2 +-
1 file changed, 1 insertion(+), 1 deletio
From: Taylor Simpson
Rdd32 = add(Rss32, Rtt32, Px4):carry
Add with carry
Rdd32 = sub(Rss32, Rtt32, Px4):carry
Sub with carry
Test cases in tests/tcg/hexagon/multi_result.c
Signed-off-by: Taylor Simpson
Reviewed-by: Richard Henderson
Message-Id: <1617930474-31979-22-git-send-email-tsim
From: Taylor Simpson
Suggested-by: Richard Henderson
Signed-off-by: Taylor Simpson
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <1617930474-31979-8-git-send-email-tsimp...@quicinc.com>
Signed-off-by: Richard Henderson
---
target/hexagon/cpu_bits.h | 2 +-
From: Taylor Simpson
The following instructions are added
L2_loadbzw2_io Rd32 = memubh(Rs32+#s11:1)
L2_loadbzw4_io Rdd32 = memubh(Rs32+#s11:1)
L2_loadbsw2_io Rd32 = membh(Rs32+#s11:1)
L2_loadbsw4_io Rdd32 = membh(Rs32+#s11:1)
L4_loadbzw2_ur
From: Taylor Simpson
Suggested-by: Philippe Mathieu-Daudé
Signed-off-by: Taylor Simpson
Reviewed-by: Richard Henderson
Message-Id: <1617930474-31979-16-git-send-email-tsimp...@quicinc.com>
Signed-off-by: Richard Henderson
---
target/hexagon/genptr.c | 3 ++-
1 file changed, 2 insertions(+),
From: Taylor Simpson
Rdd32,Pe4 = vminub(Rtt32, Rss32)
Vector min of bytes
Test cases in tests/tcg/hexagon/multi_result.c
Signed-off-by: Taylor Simpson
Reviewed-by: Richard Henderson
Message-Id: <1617930474-31979-21-git-send-email-tsimp...@quicinc.com>
Signed-off-by: Richard Henderson
---
From: Taylor Simpson
Rd32,Pe4 = sfrecipa(Rs32, Rt32)
Recripocal approx
Test cases in tests/tcg/hexagon/multi_result.c
FP exception tests added to tests/tcg/hexagon/fpstuff.c
Signed-off-by: Taylor Simpson
Reviewed-by: Richard Henderson
Message-Id: <1617930474-31979-18-git-send-email-tsimp.
From: Taylor Simpson
The following instructions are added
L2_loadalignb_io Ryy32 = memb_fifo(Rs32+#s11:1)
L2_loadalignh_io Ryy32 = memh_fifo(Rs32+#s11:1)
L4_loadalignb_ur Ryy32 = memb_fifo(Rt32<<#u2+#U6)
L4_loadalignh_ur Ryy32 = memh_fifo(Rt32<<
From: Taylor Simpson
The following instruction is added
S2_cabacdecbinRdd32=decbin(Rss32,Rtt32)
Test cases added to tests/tcg/hexagon/misc.c
Signed-off-by: Taylor Simpson
Reviewed-by: Richard Henderson
Message-Id: <1617930474-31979-27-git-send-email-tsimp...@quicinc.com>
Signe
From: Taylor Simpson
The following instructions are added
L2_loadrub_pci Rd32 = memub(Rx32++#s4:0:circ(Mu2))
L2_loadrb_pci Rd32 = memb(Rx32++#s4:0:circ(Mu2))
L2_loadruh_pci Rd32 = memuh(Rx32++#s4:1:circ(Mu2))
L2_loadrh_pci Rd32 = memh(Rx32++#s
Hi Edgar,
+Damien/Luc/Markus
On 5/2/21 8:21 AM, Edgar E. Iglesias wrote:
> On Sun, May 02, 2021 at 12:13:49AM +0200, Philippe Mathieu-Daudé wrote:
>> From: Philippe Mathieu-Daudé
>>
>> TYPE_ETRAX_FS_TIMER is a sysbus device, so its DeviceClass::reset()
>> handler is called automatically when its
I am not currently actively building this. However since this has not
been fixed we moved to pre-compiling this in order to avoid using QEMU.
It means building needed dedcated hardware.
See resolution at:
https://github.com/zynthian/zynthian-sys/issues/59
** Bug watch added: github.com/zynthian/z
On 4/14/21 6:11 PM, Cleber Rosa wrote:
> This is being proposed as a separate single patch simply to show
> that no known regressions have been introduced as far as the
> acceptance tests/jobs are related. CI job:
>
>https://gitlab.com/cleber.gnu/qemu/-/pipelines/286347312
>
> This version (
Which QEMU version did you re-test with?
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https://bugs.launchpad.net/bugs/1776478
Title:
Getting qemu: uncaught target signal 6 when running lv2 plugin cross-
compilation
Status in
If a PHY does not exist, attempts to read from it should return 0x.
Otherwise the Linux kernel will believe that a PHY is there and select
the non-existing PHY. This in turn will result in network errors later
on since the real PHY is not selected or configured.
Since reading from or writing t
On Mon, May 3, 2021 at 12:03 AM Guenter Roeck wrote:
>
> If a PHY does not exist, attempts to read from it should return 0x.
> Otherwise the Linux kernel will believe that a PHY is there and select
> the non-existing PHY. This in turn will result in network errors later
> on since the real PHY
On 5/2/21 6:03 PM, Guenter Roeck wrote:
> If a PHY does not exist, attempts to read from it should return 0x.
> Otherwise the Linux kernel will believe that a PHY is there and select
> the non-existing PHY. This in turn will result in network errors later
> on since the real PHY is not selected
On 5/2/21 9:09 AM, Bin Meng wrote:
> On Mon, May 3, 2021 at 12:03 AM Guenter Roeck wrote:
>>
>> If a PHY does not exist, attempts to read from it should return 0x.
>> Otherwise the Linux kernel will believe that a PHY is there and select
>> the non-existing PHY. This in turn will result in net
The following changes since commit 53c5433e84e8935abed8e91d4a2eb813168a0ecf:
Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20210501' into
staging (2021-05-02 12:02:46 +0100)
are available in the Git repository at:
https://github.com/philmd/qemu.git tags/mips-202
restore_msa_fp_status() is declared inlined in fpu_helper.h,
and uses the ieee_rm[] array. Therefore any code calling
restore_msa_fp_status() must have access to this ieee_rm[] array.
kvm_mips_get_fpu_registers(), which is in target/mips/kvm.c,
calls restore_msa_fp_status.
Except this tiny array,
The CACHEE opcode "requires CP0 privilege".
The pseudocode checks in the ISA manual is:
if is_eva and not C0.Config5.EVA:
raise exception('RI')
if not IsCoprocessor0Enabled():
raise coprocessor_exception(0)
Add the missing checks.
Inspired-by: Richard Henderson
Signed-off-
Since commit 078778c5a55 ("piix4: Add an i8259 Interrupt Controller")
the TYPE_PIIX4_PCI_DEVICE exposes the ISA input IRQs as "isa" alias.
Use this alias to get IRQ for the power management PCI function.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <202103241
mips_cpu_reset() is used by all accelerators, and calls
msa_reset(), which is defined in msa_helper.c.
Beside msa_reset(), the rest of msa_helper.c is only useful
to the TCG accelerator. To be able to restrict this helper
file to TCG, we need to move msa_reset() out of it.
Reviewed-by: Richard He
As mips_cpu_dump_state() is only used once to initialize the
CPUClass::dump_state handler, we can move it to cpu.c to keep
it symbol local.
Beside, this handler is used by all accelerators, while the
translate.c file targets TCG.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daud
Add various missing fields to the CPU migration vmstate:
- CP0_VPControl & CP0_GlobalNumber (01bc435b44b 2016-02-03)
- CMGCRBase (c870e3f52ca 2016-03-15)
- CP0_ErrCtl(0d74a222c27 2016-03-25)
- MXU GPR[] & CR(eb555
The CPU/FPU regnames[] arrays is used in mips_tcg_init() and
mips_cpu_dump_state(), which while being in translate.c is
not specific to TCG.
To be able to move mips_cpu_dump_state() to cpu.c, which is
compiled for all accelerator, we need to make the regnames[]
arrays global to target/mips/ by dec
Turn printfpr() macro into a proper function: fpu_dump_fpr().
Suggested-by: Richard Henderson
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20210428170410.479308-8-f4...@amsat.org>
---
target/mips/cpu.c | 50 ++-
1
Declare get_physical_address() with local scope and move it along
with mips_cpu_get_phys_page_debug() to sysemu/physaddr.c new file.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20210428170410.479308-18-f4...@amsat.org>
---
target/mips/internal.h |
Per the nanoMIPS32 Instruction Set Technical Reference Manual,
Revision 01.01, Chapter 3. "Instruction Definitions":
The Read/Write Previous GPR opcodes "require CP0 privilege".
Add the missing CP0 checks.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <202104
Rename set_pc() as mips_env_set_pc(), declare it inlined
and use it in cpu.c and op_helper.c.
Reported-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20210428170410.479308-9-f4...@amsat.org>
---
target/mips/internal.h | 10 ++
t
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20210428170410.479308-11-f4...@amsat.org>
---
target/mips/ldst_helper.c | 288 ++
target/mips/op_helper.c | 259 --
target/mips/meson.build |
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20210428170410.479308-19-f4...@amsat.org>
---
target/mips/internal.h | 4
target/mips/tcg/tcg-internal.h | 9 +
2 files changed, 9 insertions(+), 4 deletions(-)
diff --git a/target/mips/intern
When running with '-d unimp' all MTHC0 opcode executed
are logged as unimplemented... Add the proper 'return'
statement missed from commit 5204ea79ea7.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20210422081055.2349216-1-f4...@amsat.org>
---
target/mips/tra
Move cp0_helper.c and mips-semi.c to the new tcg/sysemu/ folder,
adapting the Meson machinery.
Move the opcode definitions to tcg/sysemu_helper.h.inc.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20210428170410.479308-20-f4...@amsat.org>
---
target/mips/hel
Similarly to the 'target_softmmu_arch' source set which allows
to restrict target-specific sources to system emulation, add
the equivalent 'target_user_arch' set for user emulation.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20210428170410.479308-12-f4...@a
To avoid callers to emit dead code if check_cp0_enabled()
raise an exception, let it return a boolean value, whether
CP0 is enabled or not.
Suggested-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20210420193453.1913810-4-f4...@amsat.org>
Move helper_cache() to tcg/sysemu/special_helper.c.
The CACHE opcode is privileged and is not accessible in user
emulation. However we get a link failure when restricting the
symbol to sysemu. For now, add a stub helper to satisfy linking,
which abort if ever called.
Reviewed-by: Richard Henderso
Opcodes accessing Coprocessor 0 are privileged.
Move the CP0 helpers to sysemu/ and simplify the #ifdef'ry.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20210428170410.479308-28-f4...@amsat.org>
---
target/mips/internal.h | 9 +--
target/mips/cpu.c
We will gradually move TCG-specific declarations to a new local
header: "tcg-internal.h". To keep review simple, first add this
header with 2 TCG prototypes, which we are going to move in the
next 2 commits.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <202104
We already have the mips_tcg_ss source set for TCG-specific files,
use it for mxu_translate.c and tx79_translate.c to simplify a bit.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20210428170410.479308-2-f4...@amsat.org>
---
target/mips/meson.build | 5 ++---
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20210428170410.479308-27-f4...@amsat.org>
---
target/mips/internal.h | 13 ---
target/mips/tcg/tcg-internal.h | 14 +++
target/mips/cpu.c | 113 --
target/mips/exception.c
Only the malta and loongson3-virt machines support KVM.
Restrict the other machines to TCG:
- mipssim
- magnum
- pica61
- fuloong2e
- boston
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20210428170410.479308-30-f4...@amsat.org>
---
hw/mips/meson.build
The #ifdef'ry hides that the user-mode implementation of
mips_cpu_do_interrupt() simply sets exception_index = EXCP_NONE.
Add this simple implementation to tcg/user/tlb_helper.c, and
the corresponding Meson machinery to build this file when user
emulation is configured.
Reviewed-by: Richard Hende
Since all entries are no more than 4 bytes (including nul
terminator), can save space and pie runtime relocations by
declaring regnames[] as array of 4 const char.
Suggested-by: Richard Henderson
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20210428170410.47
To ease maintenance, move all TCG specific files under the tcg/
sub-directory. Adapt the Meson machinery.
The following prototypes:
- mips_tcg_init()
- mips_cpu_do_unaligned_access()
- mips_cpu_do_transaction_failed()
can now be restricted to the "tcg-internal.h" header.
Reviewed-by: Richard Hend
Currently cpu_mips_translate_address() calls raise_mmu_exception(),
and do_translate_address() calls cpu_loop_exit_restore().
This API split is dangerous, we could call cpu_mips_translate_address
without returning to the main loop.
As there is only one caller, it is trivial (and safer) to merge
d
The 3 map_address() handlers are local to tlb_helper.c,
no need to have their prototype declared publically.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20210428170410.479308-23-f4...@amsat.org>
---
target/mips/internal.h | 6 --
target/mi
Add a new job to cross-build the mips64el target without
the TCG accelerator (IOW: only KVM accelerator enabled).
Only build the mips64el target which is known to work
and has users.
Reviewed-by: Richard Henderson
Acked-by: Thomas Huth
Reviewed-by: Willian Rampazzo
Signed-off-by: Philippe Math
tlb_helper.c's #ifdef'ry hides a quite simple user-mode
implementation of mips_cpu_tlb_fill().
Copy the user-mode implementation (without #ifdef'ry) to
tcg/user/helper.c and simplify tlb_helper.c's #ifdef'ry.
This will allow us to restrict tlb_helper.c to sysemu.
Reviewed-by: Richard Henderson
On 4/21/21 11:41 PM, Philippe Mathieu-Daudé wrote:
Philippe Mathieu-Daudé (2):
MAINTAINERS: Add include/exec/gen-icount.h to 'Main Loop' section
exec/gen-icount.h: Add missing "exec/exec-all.h" include
Queued, thanks.
r~
We have 2 blocks guarded with #ifdef for sysemu, which
are simply separated by the cpu_signal_handler definition.
To simplify the following commits which involve various
changes in internal.h, first join the sysemu-guarded blocks.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Da
Move sysemu-specific files under the new sysemu/ subfolder
and adapt the Meson machinery.
Update the KVM MIPS entry in MAINTAINERS.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20210428170410.479308-17-f4...@amsat.org>
---
target/mips/{ => sysemu}/addr.c
mmu_init() is only required by TCG accelerator.
Restrict its declaration and call to TCG.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20210428170410.479308-21-f4...@amsat.org>
---
target/mips/internal.h | 3 ---
target/mips/tcg/tcg-internal.h | 2 ++
TYPE_MC146818_RTC is an ISA device, so its DeviceClass::reset()
handler is called automatically when its qbus parent is reset
(we don't need to register it manually).
We have 2 reset() methods: a generic one and the qdev one.
Merge them into a reset_enter handler (keeping the IRQ lowering
to a res
Move tlb_helper.c to the tcg/sysemu/ subdir, along with
the following 3 declarations to tcg-internal.h:
- cpu_mips_tlb_flush()
- cpu_mips_translate_address()
- r4k_invalidate_tlb()
Simplify tlb_helper.c #ifdef'ry because files in tcg/sysemu/
are only build when sysemu mode is configured.
Reviewed
Move the Special opcodes helpers to tcg/sysemu/special_helper.c.
Since mips_io_recompile_replay_branch() is set as
CPUClass::io_recompile_replay_branch handler in cpu.c,
we need to declare its prototype in "tcg-internal.h".
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
Me
Move TLB management helpers to tcg/sysemu/tlb_helper.c.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20210428170410.479308-26-f4...@amsat.org>
---
target/mips/helper.h| 10 -
target/mips/internal.h | 7 -
target/mips/tcg/sysem
ping?
On 4/22/21 8:41 AM, Philippe Mathieu-Daudé wrote:
> include/exec/gen-icount.h is listed as unmaintained.
> Add it to Main Loop (or should it be TCG? softmmu/icount.c
> is already there).
>
> Add the missing "exec/exec-all.h" header.
>
> Philippe Mathieu-Daudé (2):
> MAINTAINERS: Add incl
Patchew URL: https://patchew.org/QEMU/20210502161538.534038-1-f4...@amsat.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20210502161538.534038-1-f4...@amsat.org
Subject: [PULL 00/36] MIPS patches for 2021-05-02
==
Hi Laurent, could you take this patch via your Trivial tree please?
On 4/8/21 12:30 AM, Philippe Mathieu-Daudé wrote:
> We check the amount of RAM is enough, warn when it is
> not, but if so we neglect to bail out. Fix that by
> adding the missing exit() call.
>
> Fixes: bda19d7bb56 ("hw/rx: Add
Hi Peter,
Could you take this patch via the ARM tree?
It has been reviewed twice.
Thanks,
Phil.
On 4/8/21 12:56 AM, Philippe Mathieu-Daudé wrote:
> The i.MX25 PDK board has 2 banks for SDRAM, each can
> address up to 256 MiB. So the total RAM usable for this
> board is 512M. When we ask for mor
Remove qemu_register_reset() when a qdev type has a qbus parent,
implementing the 3-phase Resettable interface.
Since v2:
- Lower IRQ in 'hold' phase, not 'exit' one (Edgar)
Since v1:
- Use 3-phase reset interface instead of qdev one (Laurent)
Supersedes: <20210423233652.3042941-1-f4...@amsat.or
TYPE_ETRAX_FS_TIMER is a sysbus device, so its DeviceClass::reset()
handler is called automatically when its qbus parent is reset
(we don't need to register it manually).
Convert the generic reset to a enter/hold resettable ones, and
remove the qemu_register_reset() call.
Signed-off-by: Philippe
On 5/2/21 1:20 PM, Mark Cave-Ayland wrote:
> On 07/04/2021 18:53, Philippe Mathieu-Daudé wrote:
>
>> Hi Mark,
>>
>> This series QOM'ify a bit more the sun4m machines.
>> I need it for a further memory maxsize check.
>> It is mostly code movement (and the diff-stat is good).
>>
>> Philippe Mathieu-
Clang can provide some additional warnings compared to GCC which can
sometimes help to catch some more bugs. So it would be good to be
able to build the s390-ccw bios with Clang, too. Only caveat: Clang
does not support the z900 anymore which is the lowest guest CPU that
could be used in QEMU, so w
Clang unfortunately does not support generating code for the z900
architecture level and starts with the z10 instead. Thus to be able
to support compiling with Clang, we have to check for the supported
compiler flags. The disadvantage is of course that the bios image
will only run with z10 guest CP
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