The AST2600 SPI controllers have a set of bits to request/grant DMA
access. Add a new SMC feature for these controllers and use it to
check access to the DMA registers.
Cc: Chin-Ting Kuo
Signed-off-by: Cédric Le Goater
Reviewed-by: Joel Stanley
Message-Id: <20210407171637.43-16-...@kaod.org
The Rainier BMC board is a board for the middle range POWER10 IBM systems.
Signed-off-by: Cédric Le Goater
Reviewed-by: Joel Stanley
Message-Id: <20210407171637.43-19-...@kaod.org>
Signed-off-by: Cédric Le Goater
---
hw/arm/aspeed.c | 79 +
1
This is an automated cleanup. This bug report has been moved
to QEMU's new bug tracker on gitlab.com and thus gets marked
as 'expired' now. Please continue with the discussion here:
https://gitlab.com/qemu-project/qemu/-/issues/58
** Changed in: qemu
Status: Incomplete => Expired
** Cha
On 29/04/2021 18:23, Fabiano Rosas wrote:
"Bruno Larsen (billionai)" writes:
finished isolation of CPU initialization logic from
translation logic. CPU initialization now only has common code
which may or may not call accelerator-specific code, as the
build options require, and is compiled se
Le 22/02/2021 à 12:28, Greg Kurz a écrit :
> This is just an oversight.
>
> Fixes: f518be3aa35b ("target/ppc: Remove "compat" property of server class
> POWER CPUs")
> Cc: gr...@kaod.org
> Signed-off-by: Greg Kurz
> ---
> docs/system/removed-features.rst |6 ++
> 1 file changed, 6 inser
This is an automated cleanup. This bug report has been moved
to QEMU's new bug tracker on gitlab.com and thus gets marked
as 'expired' now. Please continue with the discussion here:
https://gitlab.com/qemu-project/qemu/-/issues/59
** Changed in: qemu
Status: New => Expired
** Changed in
The following changes since commit ffa090bc56e73e287a63261e70ac02c0970be61a:
target/s390x: fix s390_probe_access to check PAGE_WRITE_ORG for writeability
(2021-04-23 14:10:56 +0100)
are available in the Git repository at:
https://gitlab.com/bsdimp/qemu.git tags/pull-bsd-user-20210430
for
Le 23/03/2021 à 13:34, Silvano Cirujano Cuesta a écrit :
> This patch fixes the update-binfmts templates being used in the script
> scripts/qemu-binfmt-conf.sh when the option --debian is used.
>
> Fixed issues are:
> - Typo in flag 'credentials' (previously 'credential').
> - Missing flags 'prese
On Fri, 30 Apr 2021 at 18:18, Richard Henderson
wrote:
>
> On 4/30/21 9:22 AM, Peter Maydell wrote:
> > The WFI insn is not system-mode only, though it doesn't usually make
> > a huge amount of sense for userspace code to execute it. Currently
> > if you try it in qemu-arm then the helper functio
Reviewed-by: Richard Henderson
Signed-off-by: Warner Losh
---
bsd-user/qemu.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/bsd-user/qemu.h b/bsd-user/qemu.h
index d2bcaab741..b836b603af 100644
--- a/bsd-user/qemu.h
+++ b/bsd-user/qemu.h
@@ -233,7 +233,7 @@ static inlin
On 4/30/21 9:22 AM, Peter Maydell wrote:
The WFI insn is not system-mode only, though it doesn't usually make
a huge amount of sense for userspace code to execute it. Currently
if you try it in qemu-arm then the helper function will raise an
EXCP_HLT exception, which is not covered by the switch
keyword space paren, no space before ( in function calls, spaces around
operators.
Reviewed-by: Richard Henderson
Signed-off-by: Warner Losh
---
bsd-user/bsdload.c | 32
1 file changed, 16 insertions(+), 16 deletions(-)
diff --git a/bsd-user/bsdload.c b/bsd-use
Reviewed-by: Richard Henderson
Signed-off-by: Warner Losh
---
bsd-user/bsdload.c | 12 +++-
1 file changed, 7 insertions(+), 5 deletions(-)
diff --git a/bsd-user/bsdload.c b/bsd-user/bsdload.c
index fd14ffa4cd..e1ed3b7b60 100644
--- a/bsd-user/bsdload.c
+++ b/bsd-user/bsdload.c
@@ -13,8
On 4/30/21 9:03 AM, Thomas Huth wrote:
There are no known users of this CPU anymore, and there are no
binaries available online which could be used for regression tests,
so the code has likely completly bit-rotten already. It's been
marked as deprecated since two releases now and nobody spoke up
Philippe Mathieu-Daudé writes:
> Since commit 82bf7ae84ce ("target/arm: Remove KVM support for
> 32-bit Arm hosts") we can remove the comment / check added in
> commit ab6b6a4 and directly run the bios-tables-test.
>
> Reviewed-by: Eric Blake
> Signed-off-by: Philippe Mathieu-Daudé
> ---
On Tue, 23 Feb 2021 at 05:06, Niklas Hambüchen wrote:
>
> As the added commend and `man smb.conf` explain, starting
> with that samba version, `force user` must be configured
> in `[global]` in order to access the configured `smb_dir`.
>
> This broke `-net user,smb=/path/to/folder`:
>
> The `chdir
On 30/04/2021 00:40, Richard Henderson wrote:
On 4/29/21 9:21 AM, Bruno Larsen (billionai) wrote:
@@ -234,19 +235,19 @@ static void spr_read_tbu(DisasContext *ctx, int
gprn, int sprn)
}
ATTRIBUTE_UNUSED
-static void spr_read_atbl(DisasContext *ctx, int gprn, int sprn)
+void spr_read_atbl
Thanks David. I did a quick test with the above patch and it seems to
work for me. With this patch, apparently I can create a VM with
SR-IOV VF and DAX cache ( virtio_fs_cache_size = 1024).
Thanks
Dev
On Thu, Apr 29, 2021 at 6:55 PM Dr. David Alan Gilbert
wrote:
>
> * Alex Williamson (alex.will
Reviewed-by: Richard Henderson
Signed-off-by: Warner Losh
---
bsd-user/bsdload.c | 13 ++---
1 file changed, 6 insertions(+), 7 deletions(-)
diff --git a/bsd-user/bsdload.c b/bsd-user/bsdload.c
index 546946b91d..fd14ffa4cd 100644
--- a/bsd-user/bsdload.c
+++ b/bsd-user/bsdload.c
@@ -28,
On 30/04/2021 11:31, Richard Henderson wrote:
On 4/30/21 7:05 AM, Matheus K. Ferst wrote:
+ADDI 01 10 0--.-- .. \
+ 001110 . . @PLS_D
I'm not sure about this. It's a bit surprising to find ADDI here, and
the commen
Reviewed-by: Richard Henderson
Signed-off-by: Warner Losh
---
bsd-user/syscall.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/bsd-user/syscall.c b/bsd-user/syscall.c
index adc3d21b54..4abff796c7 100644
--- a/bsd-user/syscall.c
+++ b/bsd-user/syscall.c
@@ -199,6 +199,7 @@ static int sysctl
Should be fixed by:
https://patchew.org/QEMU/20210430162212.825-1-peter.mayd...@linaro.org/
** Changed in: qemu
Status: Confirmed => Won't Fix
** Changed in: qemu
Status: Won't Fix => In Progress
--
You received this bug notification because you are a member of qemu-
devel-ml, wh
On 4/30/21 7:29 PM, Peter Maydell wrote:
> If we add 'force user=whoever' to the [global] section, is it then
> unnecessary to also specify it in the [qemu] section ?
I believe it is, yes.
Source:
https://www.samba.org/~ab/output/htmldocs/manpages-3/smb.conf.5.html#id2506183
> All S parameters
On 4/30/21 10:12 AM, Bruno Piazera Larsen wrote:
+#include "helper_regs.h"
+#include "internal.h"
+#include "spr_tcg.h"
These two includes look like they belong in patch 3 and 4 respectively.
And we probably want an #ifdef CONFIG_TCG around them.
Just to make sure, you mean spr_tcg.h and inte
On 4/29/21 7:19 PM, Ziqiao Kong wrote:
@@ -1440,7 +1442,9 @@ typedef struct CPUX86State {
FPReg fpregs[8];
/* KVM-only so far */
uint16_t fpop;
+uint16_t fpcs;
uint64_t fpip;
+uint16_t fpds;
uint64_t fpdp;
Let's put all uint16_t together, just after fpop, t
On Fri, 30 Apr 2021 at 12:48, Markus Armbruster wrote:
>
> The following changes since commit ccdf06c1db192152ac70a1dd974c624f566cb7d4:
>
> Open 6.1 development tree (2021-04-30 11:15:40 +0100)
>
> are available in the Git repository at:
>
> git://repo.or.cz/qemu/armbru.git tags/pull-qapi-2021
FYI I experienced hangs with emm386.exe (with NOEMS but not HIGHSCAN)
using qemu 3.1.0 (from debian buster), but not with qemu 5.0.1
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/740895
Title:
qemu
After the feedback from v1 I reworked the patch with suggested ideas and
this version has less duplicated code and is overall simpler.
This patch series is still a WIP, there are still 2 main problems I am
trying to solve, I'll mention them in their respective patches.
The aim of these patches is
Moved h_enter, remove_hpte, h_remove, h_bulk_remove,h_protect and
h_read to spapr_hcall_tcg.c, added h_tcg_only to be used in a !TCG
environment in spapr_hcall.c and changed build options to only build
spapr_hcall_tcg.c when CONFIG_TCG is enabled.
Added the function h_tcg_only to be used for hyper
The functions ppc_store_lpcr, ppc_hash64_filter_pagesizes and
ppc_hash64_unmap_hptes have been moved to mmu-misc.h since they are
not needed in a !TCG context and mmu-hash64 should not be compiled
in such situation.
ppc_store_lpcr and ppc_hash64_filter_pagesizes are used by multiple
functions, whi
From: Richard Henderson
> On 4/30/21 4:23 AM, Luis Fernando Fujita Pires wrote:
> > I think we should reconsider using the same .decode file for both 32-
> > and 64-bit instructions, to avoid duplicating argument set
> > definitions, and to keep the prefixed instructions close to their
> > non-pr
On 4/30/21 11:02 AM, Matheus K. Ferst wrote:
But in this case ADDI probably doesn't use PLS_D. You could use
static bool trans_PADDI(DisasContext *ctx, arg_PLS_D *a)
{
arg_D d;
if (!resolve_PLS_D(ctx, &d, a)) {
return false;
}
return trans_ADDI(ctx, &d);
}
making s
Patchew URL:
https://patchew.org/QEMU/20210430184047.81653-1-lucas.ara...@eldorado.org.br/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20210430184047.81653-1-lucas.ara...@eldorado.org.br
Subject: [RFC PATCH v2 0/2]
On 4/30/21 11:03 AM, Thomas Huth wrote:
> There are no known users of this CPU anymore, and there are no
> binaries available online which could be used for regression tests,
> so the code has likely completly bit-rotten already. It's been
completely
> marked as deprecated since two releases now
On 4/15/21 11:32 AM, Philippe Mathieu-Daudé wrote:
> Introduce the 'query-accels' QMP command which returns a list
> of built-in accelerator names.
>
> - Accelerator is a QAPI enum of all existing accelerators,
>
> - AcceleratorInfo is a QAPI structure providing accelerator
> specific informati
On 4/30/21 11:45 AM, Luis Fernando Fujita Pires wrote:
I think we can already pass multiple files to decodetree.py and it will handle
them correctly. I just didn't find a way to do that from the meson build files,
which assume decodetree will always use a single input file.
Oh, riscv does thi
Some corrections to terminology confusion below...
On Wed, Apr 28, 2021 at 8:49 PM Shivaprasad G Bhat wrote:
>
> The nvdimm devices are expected to ensure write persistence during power
> failure kind of scenarios.
No, QEMU is not expected to make that guarantee. QEMU is free to lie
to the gues
moved RW callback parameters of _spr_register into an ifdef, to support
building without TCG in the future, and added definitions for
spr_register and spr_register_kvm, to keep the same call regardless of
build options
Signed-off-by: Bruno Larsen (billionai)
---
target/ppc/translate_init.c.inc |
Moved all SPR read/write callback, and some related functions, to a
new file specific for it. These callbacks are TCG only, so separating
them is required to support the build flag disable-tcg.
Making the spr_noaccess function not static, and moving the define to
internal.h is required, otherwise
Based-on: 20210429162130.2412-2-bruno.lar...@eldorado.org.br
([PATCH v2 1/7] target/ppc: move opcode table logic to translate.c)
which is based on: 20210426184706.48040-1-bruno.lar...@eldorado.org.br
([PATCH v4] target/ppc: code motion from translate_init.c.inc to gdbstub.c)
This patch series aims
Removed functions gen_read_xer and gen_write_xer, moving their logic
directly into spr_read_xer and spr_write_xer, respectively.
Signed-off-by: Bruno Larsen (billionai)
---
target/ppc/spr_tcg.c.inc | 70 ++--
1 file changed, 31 insertions(+), 39 deletions(-)
To be able to compile translate_init.c.inc as a standalone file,
we have to make the callbacks accessible outside of translate.c;
This patch does exactly that
Signed-off-by: Bruno Larsen (billionai)
---
target/ppc/spr_tcg.c.inc| 209
target/ppc/spr_tcg.h
Renamed all gen_spr_* and gen_* functions specifically related to
registering SPRs to register_*_sprs and register_*, to avoid future
confusion with other TCG related code.
Signed-off-by: Bruno Larsen (billionai)
Reviewed-by: Richard Henderson
---
target/ppc/translate_init.c.inc | 860 +
Since vscr is not an spr, its initialization was removed from the
spr registration functions, and moved to the relevant init_procs.
We may look into adding vscr to the reset path instead of the init
path (as suggested by David Gibson), but this looked like a good
enough solution for now.
Signed-o
finished isolation of CPU initialization logic from
translation logic. CPU initialization now only has common code
and may or may not call accelerator-specific code, as the
build options require.
Signed-off-by: Bruno Larsen (billionai)
---
target/ppc/{translate_init.c.inc => cpu_init.c} | 4
On 29/04/2021 22:15, Richard Henderson wrote:
Signed-off-by: Richard Henderson
---
target/ppc/translate.c | 34 ++
1 file changed, 18 insertions(+), 16 deletions(-)
Reviewed-by: Bruno Larsen (billionai)
--
Bruno Piazera Larsen
Instituto de Pesquisas ELDORA
"Lucas Mateus Castro (alqotel)" writes:
> The functions ppc_store_lpcr, ppc_hash64_filter_pagesizes and
> ppc_hash64_unmap_hptes have been moved to mmu-misc.h since they are
> not needed in a !TCG context and mmu-hash64 should not be compiled
> in such situation.
What TCG code do the mmu-* files
Based-on: 20210430132740.10391-1-peter.mayd...@linaro.org
("target/arm: Split translate-*.c.inc into separate compilation units")
Based-on: 20210427214108.88503-1-richard.hender...@linaro.org
("linux-user/aarch64: Enable hwcap for RND, BTI, and MTE")
Since I believe Peter has both queued on his t
For MUL, we can rely on generic support. For SMULH and UMULH,
create some trivial helpers. For PMUL, back in a21bb78e5817,
we organized helper_gvec_pmul_b in preparation for this use.
Signed-off-by: Richard Henderson
---
target/arm/helper.h| 10
target/arm/sve.decode | 10 +++
Signed-off-by: Richard Henderson
---
target/arm/helper-sve.h| 14
target/arm/sve.decode | 5 +
target/arm/sve_helper.c| 44 ++
target/arm/translate-sve.c | 39 +
4 files changed, 102 insertions(+)
Will be used for SVE2 isa subset enablement.
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
v2: Do not read zfr0 from kvm unless sve is available.
---
target/arm/cpu.h| 16
target/arm/helper.c | 3 +--
target/arm/kvm64.c | 11 +++
3 files changed, 2
Signed-off-by: Richard Henderson
---
v2: Fix sqabs, sqneg (laurent desnogues)
---
target/arm/helper-sve.h| 13 +++
target/arm/sve.decode | 7 ++
target/arm/sve_helper.c| 29 +++
target/arm/translate-sve.c | 47 ++
4
Split these operations out into a header that can be shared
between neon and sve. The "sat" pointer acts both as a boolean
for control of saturating behavior and controls the difference
in behavior between neon and sve -- QC bit or no QC bit.
Widen the shift operand in the new helpers, as the SVE
Signed-off-by: Richard Henderson
---
v2: Load all inputs before writing any output (laurent desnogues)
---
target/arm/helper-sve.h| 45 ++
target/arm/sve.decode | 8
target/arm/sve_helper.c| 76 ++
target/arm/translate-sve
Signed-off-by: Richard Henderson
---
v2: Shift values are always signed (laurent desnogues).
---
target/arm/helper-sve.h| 54 ++
target/arm/sve.decode | 17 +
target/arm/sve_helper.c| 78 ++
target/arm/translate-sve.
Signed-off-by: Richard Henderson
---
v2: Fix select offsets (laurent desnogues).
---
target/arm/helper-sve.h| 24
target/arm/sve.decode | 19
target/arm/sve_helper.c| 43 +++
target/arm/translate-sve.c | 46 +++
Signed-off-by: Richard Henderson
---
target/arm/helper-sve.h| 54 ++
target/arm/sve.decode | 11
target/arm/sve_helper.c| 39 +++
target/arm/translate-sve.c | 8 ++
4 files changed, 112 insertions(+)
diff --gi
Signed-off-by: Richard Henderson
---
v2: Fix sel indexing and argument order (laurent desnogues).
---
target/arm/helper-sve.h| 3 +++
target/arm/sve.decode | 6 ++
target/arm/sve_helper.c| 34 ++
target/arm/translate-sve.c | 23 ++
Signed-off-by: Richard Henderson
---
v2: Fix select offsets (laurent desnogues).
---
target/arm/helper-sve.h| 16
target/arm/sve.decode | 12
target/arm/sve_helper.c| 30 ++
target/arm/translate-sve.c | 20
Signed-off-by: Richard Henderson
---
target/arm/sve.decode | 6 ++
target/arm/translate-sve.c | 4
2 files changed, 10 insertions(+)
diff --git a/target/arm/sve.decode b/target/arm/sve.decode
index fbfd57b23a..12be0584a8 100644
--- a/target/arm/sve.decode
+++ b/target/arm/sve.decod
Signed-off-by: Richard Henderson
---
target/arm/helper-sve.h| 54 +++
target/arm/sve.decode | 11 +++
target/arm/sve_helper.c| 194 ++---
target/arm/translate-sve.c | 7 ++
4 files changed, 210 insertions(+), 56 deletions(-)
diff --git a/t
From: Stephen Long
Signed-off-by: Stephen Long
Reviewed-by: Richard Henderson
Signed-off-by: Richard Henderson
---
v2: Load all inputs before writing any output (laurent desnogues)
---
target/arm/helper-sve.h| 35 +
target/arm/sve.decode | 8 +++
targ
Signed-off-by: Richard Henderson
---
target/arm/helper-sve.h| 8 ++
target/arm/sve.decode | 8 ++
target/arm/sve_helper.c| 26 ++
target/arm/translate-sve.c | 159 +
4 files changed, 201 insertions(+)
diff --git a/target/arm/helper-sve.h
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 10 ++
target/arm/helper-sve.h| 1 +
target/arm/sve.decode | 2 ++
target/arm/translate-sve.c | 22 ++
target/arm/vec_helper.c| 24
5 files changed, 59 insertions(
Signed-off-by: Richard Henderson
---
target/arm/helper-sve.h| 24
target/arm/sve.decode | 12 ++
target/arm/sve_helper.c| 56 +
target/arm/translate-sve.c | 238 +
4 files changed, 330 insertions(+)
diff --git a/target/arm/helper-s
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 5 +++
target/arm/helper-sve.h| 15
target/arm/sve.decode | 6
target/arm/sve_helper.c| 73 ++
target/arm/translate-sve.c | 36 +++
5 files changed, 1
Signed-off-by: Richard Henderson
---
v2: Fix select offsetting and argument order (laurent desnogues).
---
target/arm/helper-sve.h| 14 ++
target/arm/sve.decode | 12 +
target/arm/sve_helper.c| 23
target/arm/translate-sve.c | 55 +
Signed-off-by: Richard Henderson
---
target/arm/sve.decode | 5 +
target/arm/translate-sve.c | 10 ++
2 files changed, 15 insertions(+)
diff --git a/target/arm/sve.decode b/target/arm/sve.decode
index d3c4ec6dd1..695a16551e 100644
--- a/target/arm/sve.decode
+++ b/target/arm/sv
Exclude PMULL from this category for the moment.
Signed-off-by: Richard Henderson
---
target/arm/helper-sve.h| 15 +++
target/arm/sve.decode | 9 +
target/arm/sve_helper.c| 31 +++
target/arm/translate-sve.c | 9 +
4 files ch
Signed-off-by: Richard Henderson
---
target/arm/helper-sve.h| 16 +++
target/arm/sve.decode | 4 ++
target/arm/sve_helper.c| 24 ++
target/arm/translate-sve.c | 93 ++
4 files changed, 137 insertions(+)
diff --git a/target/arm/helper-
Signed-off-by: Richard Henderson
---
v2: Fix typo in gen_shrnb_vec (laurent desnogues)
v3: Replace DO_RSHR with an inline function
---
target/arm/helper-sve.h| 16
target/arm/sve.decode | 8 ++
target/arm/sve_helper.c| 54 -
target/arm/translate-sve.c | 160 +
This completes the section "SVE2 bitwise shift right narrow".
Signed-off-by: Richard Henderson
---
target/arm/helper-sve.h| 16 ++
target/arm/sve.decode | 4 ++
target/arm/sve_helper.c| 24 +
target/arm/translate-sve.c | 105 +
4 f
Signed-off-by: Richard Henderson
---
target/arm/sve.decode | 6 ++
target/arm/translate-sve.c | 21 +
2 files changed, 27 insertions(+)
diff --git a/target/arm/sve.decode b/target/arm/sve.decode
index 695a16551e..32b15e4192 100644
--- a/target/arm/sve.decode
+++ b/t
Signed-off-by: Richard Henderson
---
v2: Fix subtraction ordering (laurent desnogues).
---
target/arm/helper-sve.h| 10 +
target/arm/sve.decode | 9
target/arm/sve_helper.c| 42 ++
target/arm/translate-sve.c | 31 +
Signed-off-by: Richard Henderson
---
v2: Fix decodetree typo
v3: Fix iteration counts (zhiwei).
v4: Update for PREDDESC.
---
target/arm/sve.decode | 3 ++
target/arm/translate-sve.c | 67 ++
2 files changed, 70 insertions(+)
diff --git a/target/arm/sve.d
Signed-off-by: Richard Henderson
---
target/arm/helper-sve.h| 5 +
target/arm/sve.decode | 5 +
target/arm/sve_helper.c| 20
target/arm/translate-sve.c | 19 +++
4 files changed, 49 insertions(+)
diff --git a/target/arm/helper-sve.h b/t
Signed-off-by: Richard Henderson
---
target/arm/sve.decode | 8
target/arm/translate-sve.c | 34 ++
2 files changed, 42 insertions(+)
diff --git a/target/arm/sve.decode b/target/arm/sve.decode
index 79046d81e3..d3c4ec6dd1 100644
--- a/target/arm/sve
Signed-off-by: Richard Henderson
---
target/arm/helper-sve.h| 6 ++
target/arm/sve.decode | 12 +++
target/arm/sve_helper.c| 50 +
target/arm/translate-sve.c | 213 +
4 files changed, 281 insertions(+)
diff --git a/target/arm/helper-sv
Rename the existing sve_while (less-than) helper to sve_whilel
to make room for a new sve_whileg helper for greater-than.
Signed-off-by: Richard Henderson
---
v2: Use a new helper function to implement this.
v4: Update for PREDDESC.
---
target/arm/helper-sve.h| 3 +-
target/arm/sve.decode
SVE2 has two additional sizes of the operation and unlike NEON,
there is no saturation flag. Create new entry points for SVE2
that do not set QC.
Signed-off-by: Richard Henderson
---
target/arm/helper.h| 17
target/arm/sve.decode | 5 ++
target/arm/translate-sve.c | 18 +++
From: Stephen Long
Reviewed-by: Richard Henderson
Signed-off-by: Stephen Long
Message-Id: <20200415145915.2859-1-stepl...@quicinc.com>
[rth: Expanded comment for do_match2]
Signed-off-by: Richard Henderson
---
v2: Apply esz_mask to input pg to fix output flags.
---
target/arm/helper-sve.h
Signed-off-by: Richard Henderson
---
target/arm/helper-sve.h| 16 +++
target/arm/sve.decode | 4 ++
target/arm/sve_helper.c| 35 ++
target/arm/translate-sve.c | 98 ++
4 files changed, 153 insertions(+)
diff --git a/target/arm/hel
Signed-off-by: Richard Henderson
---
target/arm/helper-sve.h| 28 ++
target/arm/sve.decode | 11 ++
target/arm/sve_helper.c| 18 +
target/arm/translate-sve.c | 76 ++
4 files changed, 133 insertions(+)
diff --git a/target/a
In addition, use the same vector generator interface for AdvSIMD.
This fixes a bug in which the AdvSIMD insn failed to clear the
high bits of the SVE register.
Signed-off-by: Richard Henderson
---
target/arm/helper-sve.h| 4 ++
target/arm/helper.h| 2 +
target/arm/translate-a64.h
Signed-off-by: Richard Henderson
---
target/arm/helper-sve.h| 14 ++
target/arm/sve.decode | 14 ++
target/arm/sve_helper.c| 30 +
target/arm/translate-sve.c | 54 ++
4 files changed, 112 insertions(+)
diff --gi
Signed-off-by: Richard Henderson
---
target/arm/sve.decode | 7 +++
target/arm/translate-sve.c | 30 ++
2 files changed, 37 insertions(+)
diff --git a/target/arm/sve.decode b/target/arm/sve.decode
index 74ac72bdbd..65cb0a2206 100644
--- a/target/arm/sve.deco
From: Stephen Long
Signed-off-by: Stephen Long
Message-Id: <20200417162231.10374-3-stepl...@quicinc.com>
Signed-off-by: Richard Henderson
---
v2: Fix round bit type (laurent desnogues)
---
target/arm/helper-sve.h| 8
target/arm/sve.decode | 2 ++
target/arm/sve_helper.c
From: Stephen Long
Add decoding logic for SVE2 64-bit/32-bit scatter non-temporal
store insns.
64-bit
* STNT1B (vector plus scalar)
* STNT1H (vector plus scalar)
* STNT1W (vector plus scalar)
* STNT1D (vector plus scalar)
32-bit
* STNT1B (vector plus scalar)
* STNT1H (vector plus scalar)
* STNT
Signed-off-by: Richard Henderson
---
target/arm/helper.h| 2 ++
target/arm/sve.decode | 4
target/arm/translate-sve.c | 16
target/arm/vec_helper.c| 18 ++
4 files changed, 40 insertions(+)
diff --git a/target/arm/helper.h b/target/arm/hel
From: Stephen Long
Signed-off-by: Stephen Long
Message-Id: <20200417162231.10374-2-stepl...@quicinc.com>
Signed-off-by: Richard Henderson
---
target/arm/helper-sve.h| 8
target/arm/sve.decode | 5 +
target/arm/sve_helper.c| 36
t
From: Stephen Long
Signed-off-by: Stephen Long
Message-Id: <20200417162231.10374-4-stepl...@quicinc.com>
Signed-off-by: Richard Henderson
---
target/arm/helper-sve.h| 8
target/arm/sve.decode | 2 ++
target/arm/sve_helper.c| 10 ++
target/arm/translate-sve.c |
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 5 +++
target/arm/helper.h| 4 +++
target/arm/sve.decode | 4 +++
target/arm/translate-sve.c | 16 +
target/arm/vec_helper.c| 68 ++
5 files changed, 97 insertions(+)
Signed-off-by: Richard Henderson
---
v2: Fix do_sqrdmlah_d (laurent desnogues)
---
target/arm/helper-sve.h| 18
target/arm/vec_internal.h | 5 +
target/arm/sve.decode | 5 +
target/arm/sve_helper.c| 42 ++
target/arm/tra
From: Stephen Long
Signed-off-by: Stephen Long
Message-Id: <20200422165503.13511-1-stepl...@quicinc.com>
[rth: Fix indexing in helpers, expand macro to straight functions.]
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 10 ++
target/arm/helper-sve.h| 3 ++
target/a
From: Stephen Long
Signed-off-by: Stephen Long
Message-Id: <20200416173109.8856-1-stepl...@quicinc.com>
Signed-off-by: Richard Henderson
---
v2: Fix overlap between output and input vectors.
v4: Fix histseg counting (zhiwei).
---
target/arm/helper-sve.h| 7 ++
target/arm/sve.decode
For SVE, we potentially have a 4th argument coming from the
movprfx instruction. Currently we do not optimize movprfx,
so the problem is not visible.
Signed-off-by: Richard Henderson
---
target/arm/helper.h | 20 +++
target/arm/translate-a64.c | 28 +
ta
Currently only used by FMUL, but will shortly be used more.
Signed-off-by: Richard Henderson
---
target/arm/sve.decode | 14 ++
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/target/arm/sve.decode b/target/arm/sve.decode
index 04ef38f148..a504b55dad 100644
--- a/targe
From: Stephen Long
This completes the section 'SVE2 integer add/subtract narrow high part'
Signed-off-by: Stephen Long
Message-Id: <20200417162231.10374-5-stepl...@quicinc.com>
Signed-off-by: Richard Henderson
---
v2: Fix round bit type (laurent desnogues)
---
target/arm/helper-sve.h| 8
Signed-off-by: Richard Henderson
---
target/arm/helper.h| 14 ++
target/arm/sve.decode | 8
target/arm/translate-sve.c | 8
target/arm/vec_helper.c| 88 ++
4 files changed, 118 insertions(+)
diff --git a/target/arm/helper.h b/t
Used by FMLA and DOT, but will shortly be used more.
Split FMLA from FMLS to avoid an extra sub field;
similarly for SDOT from UDOT.
Signed-off-by: Richard Henderson
---
target/arm/sve.decode | 29 +++--
target/arm/translate-sve.c | 38 ---
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