On Thu, Apr 29, 2021 at 04:08:22PM +0100, Daniel P. Berrangé wrote:
> On Thu, Apr 29, 2021 at 04:00:38PM +0100, Richard W.M. Jones wrote:
> > On Thu, Apr 29, 2021 at 03:41:29PM +0100, Stefan Hajnoczi wrote:
> > > On Thu, Apr 29, 2021 at 03:22:59PM +0100, Richard W.M. Jones wrote:
> > > > libvirt or
Commit 2943b53f6 (' virtio: force VIRTIO_F_IOMMU_PLATFORM') made sure
that vhost can't just reject VIRTIO_F_IOMMU_PLATFORM when it was
requested. However, just adding it back to the negotiated flags isn't
right either because it promises support to the guest that the device
actually doesn't support
Hi,
I’m seeing SPDK test failures with QEMU NVMe controllers that I’ve bisected to
QEMU commit 2605257a26 (“hw/block/nvme: add the dataset management command”).
The failing tests are related to write zeroes handling. If an NVMe controller
supports DSM, and DLFEAT indicates that deallocated blo
On Thu, Apr 29, 2021 at 06:17:32PM +0100, Richard W.M. Jones wrote:
> On Thu, Apr 29, 2021 at 04:08:22PM +0100, Daniel P. Berrangé wrote:
> > On Thu, Apr 29, 2021 at 04:00:38PM +0100, Richard W.M. Jones wrote:
> > > On Thu, Apr 29, 2021 at 03:41:29PM +0100, Stefan Hajnoczi wrote:
> > > > On Thu, Ap
On 4/29/21 10:07 AM, Luis Fernando Fujita Pires wrote:
-static inline void gen_stop_exception(DisasContext *ctx)
+static inline void gen_end_tb_exception(DisasContext *ctx, uint32_t
+excp)
{
-gen_update_nip(ctx, ctx->base.pc_next);
-ctx->exception = POWERPC_EXCP_STOP;
+/* No need t
VIRTIO_F_RING_PACKED and VIRTIO_F_IOMMU_PLATFORM need to be supported by
the vhost device, otherwise advertising it to the guest doesn't result
in a working configuration. They are currently not supported by the
vhost-user-blk export in QEMU.
Fixes: https://bugzilla.redhat.com/show_bug.cgi?id=1935
The SEV FW >= 0.23 added a new command that can be used to query the
attestation report containing the SHA-256 digest of the guest memory
and VMSA encrypted with the LAUNCH_UPDATE and sign it with the PEK.
Note, we already have a command (LAUNCH_MEASURE) that can be used to
query the SHA-256 diges
Thanks for looking into this. What reference did you use to check which
ISA "cmpb" is in?
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1926202
Title:
qemu-user can't run some ppc binaries
Status
* Alex Williamson (alex.william...@redhat.com) wrote:
> On Thu, 29 Apr 2021 09:44:51 +0100
> "Dr. David Alan Gilbert" wrote:
>
> > * Alex Williamson (alex.william...@redhat.com) wrote:
> > > On Wed, 28 Apr 2021 20:17:23 +0100
> > > "Dr. David Alan Gilbert" wrote:
> > >
> > > > * Dev Audsin (d
On Thu, Apr 29, 2021 at 04:52:21PM +0100, Stefan Hajnoczi wrote:
> The scsi=on|off property was deprecated in QEMU 5.0 and can be removed
> completely at this point.
>
> Drop the scsi=on|off option. It was only available on Legacy virtio-blk
> devices. Linux v5.6 already dropped support for it.
>
+Jiri, +Daniel, +Igor
On Thu, Apr 29, 2021 at 11:59:41AM +0200, Markus Armbruster wrote:
[...]
> I'm not sure there's anything to remove here, but anyway, Peter Maydell:
>
This one is mine.
There's no code to remove, but the intention is to eventually
change default_cpu_version to CPU_VERSION_L
On 4/29/21, 10:22 AM, "Klaus Jensen" wrote:
On Apr 29 16:51, Harris, James R wrote:
>Hi,
>
Hi Jim,
>I’m seeing SPDK test failures with QEMU NVMe controllers that I’ve
>bisected to QEMU commit 2605257a26 (“hw/block/nvme: add the dataset
>management command”).
"Bruno Larsen (billionai)" writes:
> Added macros for spr_register and spr_register_kvm that can
> ignore SPR RW callbacks, in preparation to support building
> without TCG.
>
> Signed-off-by: Bruno Larsen (billionai)
> ---
> target/ppc/translate_init.c.inc | 22 ++
> 1 file
Le 29/04/2021 à 19:20, Aaron Simmons a écrit :
> Thanks for looking into this. What reference did you use to check which
> ISA "cmpb" is in?
>
It's in the QEMU source, but you can check the specs:
POWER ISA 2.04 -> no cmpb
https://wiki.raptorcs.com/w/images/6/65/PowerISA_V2.04-FINAL.Public.pdf
"Bruno Larsen (billionai)" writes:
> Moved all SPR read/write callback, and some related functions, to a
> new file specific for it. These callbacks are TCG only, so separating
> them is required to support the flag disable-tcg.
>
> Making the spr_noaccess function not static, and moving the defi
"Bruno Larsen (billionai)" writes:
> To be able to compile translate_init.c.inc as a standalone file,
> we have to make the callbacks accessible outside of translate.c;
> This patch does that, making the callbacks not static and creating
> a new .h file
>
> Signed-off-by: Bruno Larsen (billionai)
Hello,
On behalf of the QEMU Team, I'd like to announce the availability of
the QEMU 6.0.0 release. This release contains 3300+ commits from 268
authors.
You can grab the tarball from our download page here:
https://www.qemu.org/download/#source
The full list of changes are available at:
h
On Wed, Mar 24, 2021 at 02:39:44PM -0400, Peter Xu wrote:
> This is v6 of the qemu dirty ring interface support.
>
> v6:
> - Fix slots_lock init [Keqian, Paolo]
> - Comment above KVM_CAP_MANUAL_DIRTY_LOG_PROTECT2 on todo (to enable
> KVM_CLEAR_DIRTY_LOG for dirty ring too) [Keqian, Paolo]
> - Fi
"Bruno Larsen (billionai)" writes:
> finished isolation of CPU initialization logic from
> translation logic. CPU initialization now only has common code
> which may or may not call accelerator-specific code, as the
> build options require, and is compiled separately.
>
> Signed-off-by: Bruno Lar
On 4/28/21 7:03 PM, Philippe Mathieu-Daudé wrote:
> TL;DR:
>
> This series restrict TCG-specific objects by moving them to
> the tcg/ subdir. Code is moved around to satisfy 3 cases:
> { generic sysemu / tcg sysemu / tcg user}.
> Philippe Mathieu-Daudé (30):
> target/mips: Simplify meson TCG ru
On Fri, 2021-04-16 at 18:21 +0100, Peter Maydell wrote:
> On Thu, 1 Apr 2021 at 03:41, Shashi Mallela <
> shashi.mall...@linaro.org> wrote:
> > Added register definitions relevant to ITS,implemented overall
> > ITS device framework with stubs for ITS control and translater
> > regions read/write,ex
On Mon, 2021-04-19 at 11:51 +0100, Peter Maydell wrote:
> On Thu, 1 Apr 2021 at 03:41, Shashi Mallela <
> shashi.mall...@linaro.org> wrote:
> > Added properties to enable ITS feature and define qemu system
> > address space memory in gicv3 common,setup distributor and
> > redistributor registers to
On Thu, 2021-04-29 at 17:46 -0400, shashi.mall...@linaro.org wrote:
On Fri, 2021-04-16 at 19:54 +0100, Peter Maydell wrote:
> On Thu, 1 Apr 2021 at 03:41, Shashi Mallela <
> shashi.mall...@linaro.org> wrote:
> > Defined descriptors for ITS device table,collection table and ITS
> > command queue ent
Added register definitions relevant to ITS,implemented overall
ITS device framework with stubs for ITS control and translater
regions read/write,extended ITS common to handle mmio init between
existing kvm device and newer qemu device.
Signed-off-by: Shashi Mallela
---
hw/intc/arm_gicv3_its.c
Included creation of ITS as part of virt platform GIC
initialization.This Emulated ITS model now co-exists with kvm
ITS and is enabled in absence of kvm irq kernel support in a
platform.
Signed-off-by: Shashi Mallela
---
hw/arm/virt.c | 27 +--
include/hw/arm/virt
On Thu, 2021-04-29 at 18:16 -0400, shashi.mall...@linaro.org wrote:
On Mon, 2021-04-19 at 13:44 +0100, Peter Maydell wrote:
> On Thu, 1 Apr 2021 at 03:41, Shashi Mallela <
> shashi.mall...@linaro.org> wrote:
> > Implemented lpi processing at redistributor to get lpi config info
> > from lpi configu
Added properties to enable ITS feature and define qemu system
address space memory in gicv3 common,setup distributor and
redistributor registers to indicate LPI support.
Signed-off-by: Shashi Mallela
---
hw/intc/arm_gicv3_common.c | 13 +
hw/intc/arm_gicv3_dist.c |
On Mon, 2021-04-19 at 11:30 +0100, Peter Maydell wrote:
> On Thu, 1 Apr 2021 at 03:41, Shashi Mallela <
> shashi.mall...@linaro.org> wrote:
> > Added functionality to trigger ITS command queue processing on
> > write to CWRITE register and process each command queue entry to
> > identify the comman
Added functionality to trigger ITS command queue processing on
write to CWRITE register and process each command queue entry to
identify the command type and handle commands like MAPD,MAPC,SYNC.
Signed-off-by: Shashi Mallela
---
hw/intc/arm_gicv3_its.c | 327
Implemented lpi processing at redistributor to get lpi config info
from lpi configuration table,determine priority,set pending state in
lpi pending table and forward the lpi to cpuif.Added logic to invoke
redistributor lpi processing with translated LPI which set/clear LPI
from ITS device as part o
On Mon, 2021-04-19 at 13:46 +0100, Peter Maydell wrote:
> On Thu, 1 Apr 2021 at 03:42, Shashi Mallela <
> shashi.mall...@linaro.org> wrote:
> > Included creation of ITS as part of virt platform GIC
> > initialization.This Emulated ITS model now co-exists with kvm
> > ITS and is enabled in absence o
Added ITS command queue handling for MAPTI,MAPI commands,handled ITS
translation which triggers an LPI via INT command as well as write
to GITS_TRANSLATER register,defined enum to differentiate between ITS
command interrupt trigger and GITS_TRANSLATER based interrupt trigger.
Each of these commands
Defined descriptors for ITS device table,collection table and ITS
command queue entities.Implemented register read/write functions,
extract ITS table parameters and command queue parameters,extended
gicv3 common to capture qemu address space(which host the ITS table
platform memories required for s
This patchset implements qemu device model for enabling physical
LPI support and ITS functionality in GIC as per GICv3 specification.
Both flat table and 2 level tables are implemented.The ITS commands
for adding/deleting ITS table entries,trigerring LPI interrupts are
implemented.Translated LPI in
Included creation of ITS as part of SBSA platform GIC
initialization.
Signed-off-by: Shashi Mallela
---
hw/arm/sbsa-ref.c | 26 +++---
1 file changed, 23 insertions(+), 3 deletions(-)
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
index 88dfb2284c..d05cbcae48 100644
---
From: Gustavo Noronha Silva
On Mac OS X the Option key maps to Alt and Command to Super/Meta. This change
swaps them around so that Alt is the key closer to the space bar and Meta/Super
is between Control and Alt, like on non-Mac keyboards.
It is a cocoa display option, enabled by default.
Sign
From: Gustavo Noronha Silva
Applications such as Gnome may use Alt-Tab and Super-Tab for different
purposes, some use Ctrl-arrows so we want to allow qemu to handle
everything when it captures the mouse/keyboard.
However, Mac OS handles some combos like Command-Tab and Ctrl-arrows
at an earlier
From: Gustavo Noronha Silva
This series adds two new options to the cocoa display:
- full-grab causes it to use a global tap to steal system combos
away from Mac OS X, so they can be handled by the VM
- swap-option-command does what it says on the tin; while that is
something you can do
Changes for v3:
* More changes for decodetree.
* Cleanup exception/is_jmp logic to the point exception is removed.
* Fold in Luis' isa check for prefixed insn support.
* Share trans_* between prefixed and non-prefixed instructions.
* Use macros to minimize the trans_* boilerplate.
* Fix
Form a hex constant of the appropriate insnwidth.
Begin using f-strings on changed lines.
Signed-off-by: Richard Henderson
---
scripts/decodetree.py | 66 +--
1 file changed, 38 insertions(+), 28 deletions(-)
diff --git a/scripts/decodetree.py b/scripts/d
Signed-off-by: Richard Henderson
---
target/ppc/translate.c | 34 ++
1 file changed, 18 insertions(+), 16 deletions(-)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 0984ce637b..ee25badba2 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/tr
Remove the synthetic "exception" after no more uses.
Signed-off-by: Richard Henderson
---
target/ppc/cpu.h | 1 -
target/ppc/translate.c | 27 +--
2 files changed, 9 insertions(+), 19 deletions(-)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index e73416da68..
Rather than force all structure members to be 'int',
allow the type of the member to be specified.
Signed-off-by: Richard Henderson
---
docs/devel/decodetree.rst | 11 ---
tests/decode/succ_argset_type1.decode | 1 +
scripts/decodetree.py | 45 +--
From: Luis Fernando Fujita Pires
Allow '64' to be specified for the instruction width command line params
and use the appropriate extract and deposit functions in that case.
This will be used to implement the new 64-bit Power ISA 3.1 instructions.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off
Two of the call sites that use gen_debug_exception have already
updated NIP. Only ppc_tr_breakpoint_check requires the update.
Signed-off-by: Richard Henderson
---
target/ppc/translate.c | 15 ++-
1 file changed, 2 insertions(+), 13 deletions(-)
diff --git a/target/ppc/translate.c
Rewrite ppc_tr_tb_stop to handle these new codes.
Convert ctx->exception into these new codes at the end of
ppc_tr_translate_insn, prior to pushing the change back
throughout translate.c.
Signed-off-by: Richard Henderson
---
target/ppc/translate.c | 75 --
Since POWERPC_SYSCALL is raised by gen_exception_err,
we will have also set DISAS_NORETURN.
Signed-off-by: Richard Henderson
---
target/ppc/translate.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 3607cc12f3..b26b6964a7 100644
--- a/tar
Signed-off-by: Richard Henderson
---
target/ppc/translate.c | 115 +++--
1 file changed, 64 insertions(+), 51 deletions(-)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index ee25badba2..ebe5afe7ae 100644
--- a/target/ppc/translate.c
+++ b/targe
Since ba3e7926691ed33, we switched the implementation of icount
to always reset can_do_io at the start of the following TB.
Most of them were removed in 9e9b10c64911, but some were missed.
Signed-off-by: Richard Henderson
---
target/ppc/translate_init.c.inc | 6 --
1 file changed, 6 deletion
Signed-off-by: Richard Henderson
---
scripts/decodetree.py | 50 ---
1 file changed, 23 insertions(+), 27 deletions(-)
diff --git a/scripts/decodetree.py b/scripts/decodetree.py
index 0861e5d503..d5da101167 100644
--- a/scripts/decodetree.py
+++ b/scripts/
Since POWERPC_EXCP_TRAP is raised by gen_exception_err,
we will have also set DISAS_NORETURN.
Signed-off-by: Richard Henderson
---
target/ppc/translate.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index b26b6964a7..5efa4d6566 100644
--- a/t
There are other valid settings for is_jmp besides
DISAS_NEXT and DISAS_NORETURN, so eliminating that
dichotomy from ppc_tr_translate_insn is helpful.
Signed-off-by: Richard Henderson
---
v3: Retain an exit from translator loop for ctx->exception.
Do not emit code for single-step or ppc_tr_tb_
These will be used by the decodetree trans_* functions
to early-exit when the instruction set is not enabled.
Signed-off-by: Richard Henderson
---
target/ppc/translate.c | 26 ++
1 file changed, 26 insertions(+)
diff --git a/target/ppc/translate.c b/target/ppc/translate.
When single-stepping, force max_insns to 1 in init_disas
so that we exit the translation loop immediately.
Combine the single-step checks in tb_stop, and give the
gdb exception priority over the cpu exception, just as
we already do in gen_lookup_and_goto_ptr.
Signed-off-by: Richard Henderson
---
Create a function to handle the details for interacting with icount.
Force the exit from the tb via DISAS_TOO_MANY, which allows chaining
to the next tb, where the code emitted for gen_tb_start() will
determine if we must exit. We can thus remove any matching
conditional call to gen_stop_exceptio
The translation of branch instructions always results in exit from
the TB. Remove the synthetic "exception" after no more uses.
Signed-off-by: Richard Henderson
---
target/ppc/cpu.h | 2 --
linux-user/ppc/cpu_loop.c | 3 ---
target/ppc/translate.c| 8 ++--
3 files changed, 2 in
Signed-off-by: Richard Henderson
---
target/ppc/insn32.decode | 2 ++
target/ppc/insn64.decode | 11 +++
target/ppc/translate/fixedpoint-impl.c.inc | 5 +
3 files changed, 18 insertions(+)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32
We do not need to emit an exit_tb after an exception,
as the latter will exit via longjmp.
Signed-off-by: Richard Henderson
---
target/ppc/translate.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index c018960ce9..fe3982e28
Now that we have removed all of the fake exceptions, and all real
exceptions exit via DISAS_NORETURN, we can remove this field.
Signed-off-by: Richard Henderson
---
target/ppc/translate.c | 22 ++
1 file changed, 2 insertions(+), 20 deletions(-)
diff --git a/target/ppc/trans
Remove the synthetic "exception" after no more uses.
Signed-off-by: Richard Henderson
---
target/ppc/cpu.h| 1 -
linux-user/ppc/cpu_loop.c | 3 ---
target/ppc/translate.c | 20 +---
target/ppc/translate_init.c.inc | 4 ++--
4 files changed, 7 ins
Signed-off-by: Richard Henderson
---
target/ppc/insn64.decode | 12
1 file changed, 12 insertions(+)
diff --git a/target/ppc/insn64.decode b/target/ppc/insn64.decode
index 4198e5c8f3..7a71a7a3bb 100644
--- a/target/ppc/insn64.decode
+++ b/target/ppc/insn64.decode
@@ -44,6 +44,18 @@
Signed-off-by: Richard Henderson
---
target/ppc/helper.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 6a4dccf70c..af5b3586d1 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -1,5 +1,5 @@
-DEF_HELPER_FLAGS_3(ra
Signed-off-by: Luis Pires
Signed-off-by: Richard Henderson
---
v3: Move page crossing check to its own patch,
fold in ISA310 check to is_prefix_insn
---
target/ppc/cpu.h | 1 +
target/ppc/insn32.decode | 18
target/ppc/insn64.decode
With prefixed instructions, the number of instructions
remaining until the page crossing is no longer constant.
Signed-off-by: Richard Henderson
---
target/ppc/translate.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
The special logging is unnecessary. It will have been done
immediately before in the log file.
Signed-off-by: Richard Henderson
---
target/ppc/translate.c | 6 +-
1 file changed, 1 insertion(+), 5 deletions(-)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index fe3982e289..1
These are all connected by macros in the legacy decoding.
Decode the D and DS forms into the PLS_D argument set so
that prefixed insns can share code.
Signed-off-by: Richard Henderson
---
target/ppc/insn32.decode | 37 ++
target/ppc/translate.c | 145 ++
Signed-off-by: Richard Henderson
---
target/ppc/insn64.decode | 15 +++
1 file changed, 15 insertions(+)
diff --git a/target/ppc/insn64.decode b/target/ppc/insn64.decode
index 5a82ce375e..4198e5c8f3 100644
--- a/target/ppc/insn64.decode
+++ b/target/ppc/insn64.decode
@@ -29,6 +29,21
Signed-off-by: Richard Henderson
---
target/ppc/insn32.decode | 12 +++
target/ppc/insn64.decode | 15 +
target/ppc/translate.c | 29
target/ppc/translate/fixedpoint-impl.c.inc | 39 ++
4 file
On 4/29/21 6:15 PM, Richard Henderson wrote:
With prefixed instructions, the number of instructions
remaining until the page crossing is no longer constant.
Signed-off-by: Richard Henderson
---
target/ppc/translate.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
Oops, this w
These are all connected by macros in the legacy decoding.
Signed-off-by: Richard Henderson
---
target/ppc/insn32.decode | 22 ++
target/ppc/translate.c | 83 +-
target/ppc/translate/fixedpoint-impl.c.inc | 24 +++
3 files changed,
Patchew URL:
https://patchew.org/QEMU/20210430011543.1017113-1-richard.hender...@linaro.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20210430011543.1017113-1-richard.hender...@linaro.org
Subject: [PATCH v3 00/30
On Thu, Apr 29, 2021 at 7:02 PM Mahesh J Salgaonkar
wrote:
>
> On 2021-04-28 22:33:45 Wed, Oliver O'Halloran wrote:
> > On Tue, Apr 27, 2021 at 9:56 PM Mahesh Salgaonkar
> > wrote:
> > >
> > > With upstream kernel, especially after commit 98ba956f6a389
> > > ("powerpc/pseries/eeh: Rework device
Thanks the review for v1 from Richard Henderson!
Changes since v1:
- Don't update FCS, FIP, FDS and FDP for x87 control instruction.
- Also write FCS, FDS and FDP for FSTENV.
- Clear FCS, FIP, FDS and FDP for FXSAVE as intel manual says.
Note:
During my test, I find that the implementatio
On 4/29/21 9:21 AM, Bruno Larsen (billionai) wrote:
This series requires the patch proposed in
<20210426184706.48040-1-bruno.lar...@eldorado.org.br>
FYI, for the benefit of tooling, use "Based-on: message-id" which will allow
patchew to construct a patch repository.
As is,
https://patchew.o
On 4/29/21 9:21 AM, Bruno Larsen (billionai) wrote:
code motion to remove opcode callback table from
translate_init.c.inc to translate.c in preparation to remove
the #include from translate.c. Also created
destroy_ppc_opcodes and removed that logic from ppc_cpu_unrealize
Signed-off-by: Bruno La
Hi Eduardo,
Thanks for your detailed comments.
On 2021/4/29 5:19, Eduardo Habkost wrote:
On Tue, Apr 27, 2021 at 04:09:48PM +0800, Like Xu wrote:
The last branch recording (LBR) is a performance monitor unit (PMU)
feature on Intel processors that records a running trace of the most
recent bran
On Thu, 2021-04-29 at 11:59 +0200, Markus Armbruster wrote:
> If you're cc'ed, you added a section to docs/system/deprecated.rst
> that
> is old enough to permit removal. This is *not* a demand to remove,
> it's
> a polite request to consider whether the time for removal has come.
> Extra points f
On 4/29/21 9:21 AM, Bruno Larsen (billionai) wrote:
diff --git a/target/ppc/spr_tcg.c.inc b/target/ppc/spr_tcg.c.inc
new file mode 100644
index 00..48274dd52b
--- /dev/null
+++ b/target/ppc/spr_tcg.c.inc
@@ -0,0 +1,1033 @@
+#include "exec/translator.h"
All new files must have copyright
On 4/29/21 9:21 AM, Bruno Larsen (billionai) wrote:
@@ -234,19 +235,19 @@ static void spr_read_tbu(DisasContext *ctx, int gprn, int
sprn)
}
ATTRIBUTE_UNUSED
-static void spr_read_atbl(DisasContext *ctx, int gprn, int sprn)
+void spr_read_atbl(DisasContext *ctx, int gprn, int sprn)
{
On 4/29/21 9:21 AM, Bruno Larsen (billionai) wrote:
Renamed all gen_spr_* and gen_* functions specifically related to
registering SPRs to register_*_sprs and register_*, to avoid future
confusion with other TCG related code.
Signed-off-by: Bruno Larsen (billionai)
---
target/ppc/translate_init
On 4/29/21 9:21 AM, Bruno Larsen (billionai) wrote:
@@ -49,7 +54,12 @@ static inline void vscr_init(CPUPPCState *env, uint32_t val)
{
/* Altivec always uses round-to-nearest */
set_float_rounding_mode(float_round_nearest_even, &env->vec_status);
-helper_mtvscr(env, val);
+/*
On 4/29/21 9:21 AM, Bruno Larsen (billionai) wrote:
To be able to compile translate_init.c.inc as a standalone file,
we have to make the callbacks accessible outside of translate.c;
This patch does that, making the callbacks not static and creating
a new .h file
Signed-off-by: Bruno Larsen (bill
On Mon, Apr 12, 2021 at 12:24 PM Yifei Jiang wrote:
>
> Only support supervisor external interrupt currently.
>
> Signed-off-by: Yifei Jiang
> Signed-off-by: Yipeng Yin
> ---
> hw/intc/sifive_plic.c| 29 -
> target/riscv/kvm-stub.c | 5 +
> target/riscv/kvm
Hi Drew,
On 2021/4/29 19:02, Andrew Jones wrote:
On Thu, Apr 29, 2021 at 04:56:06PM +0800, wangyanan (Y) wrote:
On 2021/4/29 15:16, Andrew Jones wrote:
On Thu, Apr 29, 2021 at 10:14:37AM +0800, wangyanan (Y) wrote:
On 2021/4/28 18:31, Andrew Jones wrote:
On Tue, Apr 13, 2021 at 04:31:45PM +0
On 4/29/21 5:52 PM, Stefan Hajnoczi wrote:
> The scsi=on|off property was deprecated in QEMU 5.0 and can be removed
> completely at this point.
>
> Drop the scsi=on|off option. It was only available on Legacy virtio-blk
> devices. Linux v5.6 already dropped support for it.
>
> Remove the hw_compa
Philippe Mathieu-Daudé writes:
> On 4/29/21 3:22 PM, Markus Armbruster wrote:
>> Philippe Mathieu-Daudé writes:
> Now than we can probe if the TCG accelerator is available
> at runtime with a QMP command, do it once at the beginning
> and only register the tests we can run.
> We
From: Sean Christopherson
EPC (Enclave Page Cahe) is a specialized type of memory used by Intel
SGX (Software Guard Extensions). The SDM desribes EPC as:
The Enclave Page Cache (EPC) is the secure storage used to store
enclave pages when they are a part of an executing enclave. For an
Since Sean Christopherson has left Intel and i am responsible for Qemu SGX
upstream work. His @intel.com address will be bouncing and his new email(
sea...@google.com) is also in CC lists.
This series is Qemu SGX virtualization implementation rebased on latest
Qemu release.
You can find Qemu repo
From: Sean Christopherson
SGX EPC is enumerated through CPUID, i.e. EPC "devices" need to be
realized prior to realizing the vCPUs themselves, which occurs long
before generic devices are parsed and realized. Because of this,
do not allow 'sgx-epc' devices to be instantiated after vCPUS have
bee
From: Sean Christopherson
Add a new RAMBlock flag to denote "protected" memory, i.e. memory that
looks and acts like RAM but is inaccessible via normal mechanisms,
including DMA. Use the flag to skip protected memory regions when
mapping RAM for DMA in VFIO.
Signed-off-by: Sean Christopherson
From: Sean Christopherson
Add CPUID defines for SGX and SGX Launch Control (LC), as well as
defines for their associated FEATURE_CONTROL MSR bits. Define the
Launch Enclave Public Key Hash MSRs (LE Hash MSRs), which exist
when SGX LC is present (in CPUID), and are writable when SGX LC is
enabled
From: Sean Christopherson
Note that SGX EPC is currently guaranteed to reside in a single
contiguous chunk of memory regardless of the number of EPC sections.
Signed-off-by: Sean Christopherson
Signed-off-by: Yang Zhong
---
hw/i386/pc.c | 4
1 file changed, 4 insertions(+)
diff --git a/
From: Sean Christopherson
CPUID leaf 12_0_EAX is an Intel-defined feature bits leaf enumerating
the CPU's SGX capabilities, e.g. supported SGX instruction sets.
Currently there are four enumerated capabilities:
- SGX1 instruction set, i.e. "base" SGX
- SGX2 instruction set for dynamic EPC ma
Add the new 'memory-backend-epc' user creatable QOM object in
the ObjectOptions to support SGX, or the sgx backend object
cannot bootup.
Signed-off-by: Yang Zhong
---
qapi/qom.json | 2 ++
1 file changed, 2 insertions(+)
diff --git a/qapi/qom.json b/qapi/qom.json
index cd0e76d564..fd6fbee597 10
From: Sean Christopherson
Because SGX EPC is enumerated through CPUID, EPC "devices" need to be
realized prior to realizing the vCPUs themselves, i.e. long before
generic devices are parsed and realized. From a virtualization
perspective, the CPUID aspect also means that EPC sections cannot be
h
From: Sean Christopherson
SGX adds multiple flags to FEATURE_CONTROL to enable SGX and Flexible
Launch Control.
Signed-off-by: Sean Christopherson
Signed-off-by: Yang Zhong
---
target/i386/kvm/kvm.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/target/i386/kvm/kvm.c b/target/i386/k
From: Sean Christopherson
Enable SGX EPC virtualization, which is currently only support by KVM.
Signed-off-by: Sean Christopherson
Signed-off-by: Yang Zhong
---
hw/i386/pc_piix.c | 4
1 file changed, 4 insertions(+)
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index 46cc951073..7
From: Sean Christopherson
On real hardware, on systems that supports SGX Launch Control, those
MSRs are initialized to digest of Intel's signing key; on systems that
don't support SGX Launch Control, those MSRs are not available but
hardware always uses digest of Intel's signing key in EINIT.
KV
From: Sean Christopherson
Request SGX an SGX Launch Control to be enabled in FEATURE_CONTROL
when the features are exposed to the guest. Our design is the SGX
Launch Control bit will be unconditionally set in FEATURE_CONTROL,
which is unlike host bios.
Signed-off-by: Sean Christopherson
Signed-
From: Sean Christopherson
CPUID leaf 12_0_EBX is an Intel-defined feature bits leaf enumerating
the platform's SGX extended capabilities. Currently there is a single
capabilitiy:
- EXINFO: record information about #PFs and #GPs in the enclave's SSA
Signed-off-by: Sean Christopherson
Signed-
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