Hi David,
On 2021/4/19 9:13, David Gibson wrote:
On Sat, Apr 17, 2021 at 10:36:20AM +0800, wangyanan (Y) wrote:
Hi David,
On 2021/4/16 12:52, David Gibson wrote:
On Tue, Apr 13, 2021 at 04:07:40PM +0800, Yanan Wang wrote:
From: Andrew Jones
qemu_fdt_add_path() works like qemu_fdt_add_subno
On Mon, Apr 19, 2021 at 2:17 PM Alistair Francis
wrote:
>
> From: Hou Weiying
>
> This commit adds support for ePMP v0.9.1.
>
> The ePMP spec can be found in:
> https://docs.google.com/document/d/1Mh_aiHYxemL0umN3GTTw8vsbmzHZ_nxZXgjgOUzbvc8
>
> Signed-off-by: Hongzheng-Li
> Signed-off-by: Hou We
On Sun, 18 Apr 2021 11:38:09 +0100
Mark Cave-Ayland wrote:
> On 17/04/2021 20:46, Peter Maydell wrote:
>
> >> On 14/04/2021 13:48, Thomas Huth wrote:
> >>> I've seen some intermittend, non-reproducible crashes with usermode QEMU
> >>> in some of
> >>> my CI runs, e.g.:
> >>>
> >>> https://git
Hello,
On 4/17/21 12:30 PM, Philippe Mathieu-Daudé wrote:
> Hi,
>
> This series is the result of a long thread with Peter:
> https://www.mail-archive.com/qemu-devel@nongnu.org/msg788366.html
> and IRC chats...
>
> AddressSpace are physical address view and shouldn't be using
> non-zero base addr
Markus Armbruster writes:
> Vitaly Kuznetsov writes:
>
>> When a migration blocker is added nothing is reported to the user,
>> inability to migrate such guest may come as a late surprise. As a bare
>> minimum, we can print a warning. To not pollute the output for those, who
>> have no intention
> Am 15.04.2021 um 17:22 schrieb Kevin Wolf :
>
> Peter, three years ago you changed 'qemu-img convert' to sacrifice some
> sparsification in order to get aligned requests on the target image. At
> the time, I thought the impact would be small, but it turns out that
> this can end up wasting gi
On Mon, Apr 19, 2021 at 4:31 PM Frank Chang <0xc0de0...@gmail.com> wrote:
>
> Alistair Francis 於 2021年4月19日 週一 下午2:28寫道：
>>
>> On Mon, Apr 19, 2021 at 4:02 PM wrote:
>> >
>> > From: Frank Chang
>> >
>> > Doing a negate (0x0 – 0x8000) using vssub.vv produces
>> > an incorrect result of 0x8000
This and the following serie of patches are based on Paolo's
v1 patches sent in 2017[*]. They have been ported to the current QEMU
version, but the goal remains the same:
- make the block layer thread-safe (patches 1-5), and
- remove aio_context_acquire/release (patches 6-8).
[*] = https://lists.
For simplicity, use bdrv_drained_begin/end to avoid concurrent
writes to the write threshold, or reading it while it is being set.
qmp_block_set_write_threshold is protected by the BQL.
Reviewed-by: Stefan Hajnoczi
Co-developed-by: Paolo Bonzini
Signed-off-by: Emanuele Giuseppe Esposito
---
bl
Reviewed-by: Stefan Hajnoczi
Co-developed-by: Paolo Bonzini
Signed-off-by: Emanuele Giuseppe Esposito
---
block/write-threshold.c | 28
1 file changed, 16 insertions(+), 12 deletions(-)
diff --git a/block/write-threshold.c b/block/write-threshold.c
index 85b78dc2a9
Reviewed-by: Stefan Hajnoczi
Signed-off-by: Paolo Bonzini
Signed-off-by: Emanuele Giuseppe Esposito
---
include/block/block_int.h | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/include/block/block_int.h b/include/block/block_int.h
index a1aad5ad2d..67a0777e12 100644
---
Note that calling rcu_read_lock() is left to the caller. In fact,
if the notifier is really only used within the BQL, it's unnecessary.
Even outside the BQL, RCU accessors can also be used with any API that has
the same contract as synchronize_rcu, i.e. it stops until all concurrent
readers compl
Make the (only) caller do it.
Reviewed-by: Stefan Hajnoczi
Signed-off-by: Paolo Bonzini
Signed-off-by: Emanuele Giuseppe Esposito
---
block.c | 22 +-
blockdev.c| 7 ++-
include/block/block.h | 1 +
3 files changed, 12 insertions(+), 18 delet
Replication functions are mostly called when the BDS is quiescent and
does not have any pending I/O. They do not need to synchronize on
anything since BDS and BB are now thread-safe.
Signed-off-by: Paolo Bonzini
Signed-off-by: Emanuele Giuseppe Esposito
---
block/replication.c | 54 ++-
Reopen needs to handle AioContext carefully due to calling
bdrv_drain_all_begin/end. By not taking AioContext around calls to
bdrv_reopen_multiple, we can drop the function's release/acquire
pair and the AioContext argument too.
Signed-off-by: Paolo Bonzini
Signed-off-by: Emanuele Giuseppe Espos
Reads access the list in RCU style, so be careful to avoid use-after-free
scenarios in the backup block job. Apart from this, all that's needed
is protecting updates with a mutex.
Reviewed-by: Stefan Hajnoczi
Signed-off-by: Paolo Bonzini
Signed-off-by: Emanuele Giuseppe Esposito
---
block.c
On Sun, 18 Apr 2021 at 21:16, Philippe Mathieu-Daudé wrote:
>
> +Markus
>
> On 4/9/21 8:13 PM, Peter Maydell wrote:
> > Maybe some mechanism for marking "these things which are my
> > QOM children I want to be reset when I am reset (so make them
> > reset children of me and don't reset them as par
Public bug reported:
Tested on: Fedora 34; Component: qemu-img-5.2.0-5.fc34.1.x86_64
Hello. A two decimal digits precision is most appropriated on systems
whose storage capacities have to be saved. That is one of the reason why
such precision is supported in the context of creation of virtual
mac
Hi Cornelia,
On 3/31/21 1:07 PM, Cornelia Huck wrote:
> On Mon, 22 Mar 2021 20:15:47 +0100
> Claudio Fontana wrote:
>
>> this allows to remove unneeded stubs for target/s390x.
>
> This patch doesn't seem to remove any, though?
The next patch does... I'll split more the patches so it becomes cl
> Am 19.04.2021 um 10:36 schrieb Peter Lieven :
>
>
>
>> Am 15.04.2021 um 17:22 schrieb Kevin Wolf :
>>
>> Peter, three years ago you changed 'qemu-img convert' to sacrifice some
>> sparsification in order to get aligned requests on the target image. At
>> the time, I thought the impact would
On Sun, 18 Apr 2021 at 17:31, Alex Bennée wrote:
>
>
> Peter Maydell writes:
>
> > This pullreq contains fixes for the remaining "not fixed yet" issues
> > in the 6.0 Planning page:
> > * Fix compile failures of C++ files with new glib headers
> > * mps3-an547: Use correct Cortex-M55 CPU and do
On 3/25/21 1:09 PM, Philippe Mathieu-Daudé wrote:
> Simplify memory layout when no pflash_cfi02 mapping requested.
> Philippe Mathieu-Daud=C3=A9 (2):
> hw/block/pflash_cfi02: Set romd mode in pflash_cfi02_realize()
> hw/block/pflash_cfi02: Do not create aliases when not necessary
Thanks, seri
On Fri, Apr 16, 2021 at 11:08:59AM +0300, Vladimir Sementsov-Ogievskiy wrote:
> Detecting monitor by current coroutine works bad when we are not in
> coroutine context. And that's exactly so in nbd reconnect code, where
> qio_channel_socket_connect_sync() is called from thread.
>
> Add a possibili
On Mon, Apr 19, 2021 at 01:34:47AM +0200, Philippe Mathieu-Daudé wrote:
> Forks run the same jobs than mainstream, which might be overkill.
> Allow them to easily rebase their custom set, while keeping using
> the mainstream templates, and ability to pick specific jobs from
> the mainstream set.
>
Hi,
This series introduce the memory_region_add_subregion_aliased()
helper which basically create a device which maps a subregion
multiple times.
Since v1:
- Split series in 2, keeping the I/O regions (showed with the q800
machine) part for 2nd part
- Added R-b tags
Examples are easier, so hav
To be able to manually map the flash region on the main memory
(in the next commit), first expand the pflash_cfi02_register
in place.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/arm/digic_boards.c | 27 +--
1 file changed, 21 insertions(+), 6 deletions(-)
diff --git a/h
// TODO explain here how buses work? when some address lines are
// not bound we get memory aliasing, high addresses are masked.
// etc...
Add a helper to manage this use case easily.
For example a having @span_size = @region_size / 4 we get such mapping:
^---^
|
Instead of using a device specific feature for mapping the
flash memory multiple times over a wider region, use the
generic memory_region_add_subregion_aliased() helper.
There is no change in the memory layout:
- before:
(qemu) info mtree
fe00- (prio 0, i/o): pfla
To be able to manually map the flash region on the main memory
(in the next commit), first expand the pflash_cfi02_register
in place.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/arm/musicpal.c | 27 +--
1 file changed, 21 insertions(+), 6 deletions(-)
diff --git a/hw/ar
Instead of using a device specific feature for mapping the
flash memory multiple times over a wider region, use the
generic memory_region_add_subregion_aliased() helper.
There is no change in the memory layout.
* before:
$ qemu-system-arm -M canon-a1100 -S -monitor stdio
QEMU 5.2.90 monitor
All boards calling pflash_cfi02_register() use nb_mappings=1,
which does not do any mapping:
$ git grep -wl pflash_cfi02_register hw/
hw/arm/xilinx_zynq.c
hw/block/pflash_cfi02.c
hw/lm32/lm32_boards.c
hw/ppc/ppc405_boards.c
hw/sh4/r2d.c
We can remove this now unneeded code.
Reviewed-
On 4/19/21 9:17 AM, Cédric Le Goater wrote:
> On 4/17/21 12:30 PM, Philippe Mathieu-Daudé wrote:
>> This series is the result of a long thread with Peter:
>> https://www.mail-archive.com/qemu-devel@nongnu.org/msg788366.html
>> and IRC chats...
>>
>> AddressSpace are physical address view and should
The previous commit removed the mapping code from TYPE_PFLASH_CFI02.
pflash_cfi02_register() doesn't use the 'nb_mappings' argument
anymore. Simply remove it to simplify.
Reviewed-by: David Gibson
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/block/flash.h | 1 -
hw/arm/digic_boards.c
On 4/18/21 7:17 AM, Philippe Mathieu-Daudé wrote:
> On 4/17/21 9:41 PM, Peter Maydell wrote:
>> This pullreq contains fixes for the remaining "not fixed yet" issues
>> in the 6.0 Planning page:
>> * Fix compile failures of C++ files with new glib headers
>> * mps3-an547: Use correct Cortex-M55 CP
On 4/19/21 11:40 AM, Daniel P. Berrangé wrote:
> On Mon, Apr 19, 2021 at 01:34:47AM +0200, Philippe Mathieu-Daudé wrote:
>> Forks run the same jobs than mainstream, which might be overkill.
>> Allow them to easily rebase their custom set, while keeping using
>> the mainstream templates, and ability
19.04.2021 12:34, Daniel P. Berrangé wrote:
On Fri, Apr 16, 2021 at 11:08:59AM +0300, Vladimir Sementsov-Ogievskiy wrote:
Detecting monitor by current coroutine works bad when we are not in
coroutine context. And that's exactly so in nbd reconnect code, where
qio_channel_socket_connect_sync() is
On Mon, Apr 19, 2021 at 10:40:53AM +0100, Daniel P. Berrangé wrote:
> On Mon, Apr 19, 2021 at 01:34:47AM +0200, Philippe Mathieu-Daudé wrote:
> > Forks run the same jobs than mainstream, which might be overkill.
> > Allow them to easily rebase their custom set, while keeping using
> > the mainstrea
On 19/04/2021 12.10, Erik Skultety wrote:
On Mon, Apr 19, 2021 at 10:40:53AM +0100, Daniel P. Berrangé wrote:
On Mon, Apr 19, 2021 at 01:34:47AM +0200, Philippe Mathieu-Daudé wrote:
Forks run the same jobs than mainstream, which might be overkill.
Allow them to easily rebase their custom set, w
From: Sean Christopherson
EPC (Enclave Page Cahe) is a specialized type of memory used by Intel
SGX (Software Guard Extensions). The SDM desribes EPC as:
The Enclave Page Cache (EPC) is the secure storage used to store
enclave pages when they are a part of an executing enclave. For an
Since Sean Christopherson has left Intel and i am responsible for Qemu SGX
upstream work. His @intel.com address will be bouncing and his new email(
sea...@google.com) is also in CC lists.
This series is Qemu SGX virtualization implementation rebased on latest
Qemu release.
You can find Qemu repo
From: Sean Christopherson
On real hardware, on systems that supports SGX Launch Control, those
MSRs are initialized to digest of Intel's signing key; on systems that
don't support SGX Launch Control, those MSRs are not available but
hardware always uses digest of Intel's signing key in EINIT.
KV
From: Sean Christopherson
Because SGX EPC is enumerated through CPUID, EPC "devices" need to be
realized prior to realizing the vCPUs themselves, i.e. long before
generic devices are parsed and realized. From a virtualization
perspective, the CPUID aspect also means that EPC sections cannot be
h
From: Sean Christopherson
Add a new RAMBlock flag to denote "protected" memory, i.e. memory that
looks and acts like RAM but is inaccessible via normal mechanisms,
including DMA. Use the flag to skip protected memory regions when
mapping RAM for DMA in VFIO.
Signed-off-by: Sean Christopherson
Add the new 'memory-backend-epc' user creatable QOM object in
the ObjectOptions to support SGX, or the sgx backend object
cannot bootup.
Signed-off-by: Yang Zhong
---
qapi/qom.json | 2 ++
1 file changed, 2 insertions(+)
diff --git a/qapi/qom.json b/qapi/qom.json
index cd0e76d564..fd6fbee597 10
From: Sean Christopherson
SGX adds multiple flags to FEATURE_CONTROL to enable SGX and Flexible
Launch Control.
Signed-off-by: Sean Christopherson
Signed-off-by: Yang Zhong
---
target/i386/kvm/kvm.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/target/i386/kvm/kvm.c b/target/i386/k
On 16/04/2021 18.27, Claudio Fontana wrote:
Skip the test_device_intro_concrete for now for ARM KVM-only build,
as on ARM we currently build devices for ARM that are not
compatible with a KVM-only build.
We can remove this workaround when we fix this in KConfig etc,
and we only list and build ma
From: Sean Christopherson
Add CPUID defines for SGX and SGX Launch Control (LC), as well as
defines for their associated FEATURE_CONTROL MSR bits. Define the
Launch Enclave Public Key Hash MSRs (LE Hash MSRs), which exist
when SGX LC is present (in CPUID), and are writable when SGX LC is
enabled
From: Sean Christopherson
SGX EPC is enumerated through CPUID, i.e. EPC "devices" need to be
realized prior to realizing the vCPUs themselves, which occurs long
before generic devices are parsed and realized. Because of this,
do not allow 'sgx-epc' devices to be instantiated after vCPUS have
bee
From: Sean Christopherson
Request SGX an SGX Launch Control to be enabled in FEATURE_CONTROL
when the features are exposed to the guest. Our design is the SGX
Launch Control bit will be unconditionally set in FEATURE_CONTROL,
which is unlike host bios.
Signed-off-by: Sean Christopherson
Signed-
From: Sean Christopherson
The SGX sub-leafs are enumerated at CPUID 0x12. Indices 0 and 1 are
always present when SGX is supported, and enumerate SGX features and
capabilities. Indices >=2 are directly correlated with the platform's
EPC sections. Because the number of EPC sections is dynamic a
From: Sean Christopherson
CPUID leaf 12_1_EAX is an Intel-defined feature bits leaf enumerating
the platform's SGX capabilities that may be utilized by an enclave, e.g.
whether or not an enclave can gain access to the provision key.
Currently there are six capabilities:
- INIT: set when the en
From: Sean Christopherson
CPUID leaf 12_0_EBX is an Intel-defined feature bits leaf enumerating
the platform's SGX extended capabilities. Currently there is a single
capabilitiy:
- EXINFO: record information about #PFs and #GPs in the enclave's SSA
Signed-off-by: Sean Christopherson
Signed-
From: Sean Christopherson
The ACPI Device entry for SGX EPC is essentially a hack whose primary
purpose is to provide software with a way to autoprobe SGX support,
e.g. to allow software to implement SGX support as a driver. Details
on the individual EPC sections are not enumerated through ACPI
From: Sean Christopherson
If the guest want to fully use SGX, the guest needs to be able to
access provisioning key. Add a new KVM_CAP_SGX_ATTRIBUTE to KVM to
support provisioning key to KVM guests.
Signed-off-by: Sean Christopherson
Signed-off-by: Yang Zhong
---
target/i386/cpu.c |
From: Sean Christopherson
CPUID leaf 12_0_EAX is an Intel-defined feature bits leaf enumerating
the CPU's SGX capabilities, e.g. supported SGX instruction sets.
Currently there are four enumerated capabilities:
- SGX1 instruction set, i.e. "base" SGX
- SGX2 instruction set for dynamic EPC ma
From: Sean Christopherson
Enable SGX EPC virtualization, which is currently only support by KVM.
Signed-off-by: Sean Christopherson
Signed-off-by: Yang Zhong
---
hw/i386/pc_piix.c | 4
1 file changed, 4 insertions(+)
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index 46cc951073..7
From: Sean Christopherson
Note that SGX EPC is currently guaranteed to reside in a single
contiguous chunk of memory regardless of the number of EPC sections.
Signed-off-by: Sean Christopherson
Signed-off-by: Yang Zhong
---
hw/i386/pc.c | 4
1 file changed, 4 insertions(+)
diff --git a/
From: Sean Christopherson
Expose SGX to the guest if and only if KVM is enabled and supports
virtualization of SGX. While the majority of ENCLS can be emulated to
some degree, because SGX uses a hardware-based root of trust, the
attestation aspects of SGX cannot be emulated in software, i.e.
ult
From: Sean Christopherson
KVM_CAP_SGX_ATTRIBUTE is a proposed capability for Intel SGX that can be
used by userspace to enable privileged attributes, e.g. access to the
PROVISIONKEY.
Signed-off-by: Sean Christopherson
Signed-off-by: Yang Zhong
---
linux-headers/linux/kvm.h | 1 +
1 file chang
The command can be used to show the SGX information in the monitor
when SGX is enabled on intel platform.
Signed-off-by: Yang Zhong
---
hmp-commands-info.hx | 15 +++
include/monitor/hmp.h | 1 +
monitor/hmp-cmds.c| 6 ++
3 files changed, 22 insertions(+)
diff --git a/hmp
Add the sgx_memory_backend_reset() interface to handle EPC backend
reset when VM is reset. This reset function will destroy previous
backend memory region and re-mmap the EPC section for guest.
Signed-off-by: Yang Zhong
---
backends/hostmem-epc.c | 16
include/hw/i386/pc.h |
From: Sean Christopherson
SGX capabilities are enumerated through CPUID_0x12.
Signed-off-by: Sean Christopherson
Signed-off-by: Yang Zhong
---
target/i386/cpu.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 63253bf606..41050960c5 100644
-
If the VM is reset, we need make sure sgx virt epc in clean status.
Once the VM is reset, and sgx epc virt device will be reseted by
reset callback registered by qemu_register_reset(). Since this epc
virt device depend on backend, this reset will call backend reset
interface to re-mmap epc to guest
The libvirt can use qmp_query_sgx_capabilities() to get the host
sgx capabilitis.
Signed-off-by: Yang Zhong
---
hw/i386/sgx-epc.c | 64 ++
include/hw/i386/pc.h | 1 +
monitor/qmp-cmds.c | 5 +++
qapi/misc.json | 19
Add the sgx_get_info() interface for hmp and QMP usage, which
will get the SGX info from this API.
Signed-off-by: Yang Zhong
---
hw/i386/sgx-epc.c | 22 ++
include/hw/i386/pc.h | 1 +
include/hw/i386/sgx-epc.h | 1 +
monitor/hmp-cmds.c| 20 +
From: Sean Christopherson
Add helpers to detect if SGX EPC exists above 4g, and if so, where SGX
EPC above 4g ends. Use the helpers to adjust the device memory range
if SGX EPC exists above 4g.
For multiple virtual EPC sections, we just put them together physically
contiguous for the simplicity
The Qemu should enable bit mask macro like Linux did in the
kernel, the GENMASK(h, l) and GENMASK_ULL(h, l) will set the
bit to 1 from l to h bit in the 32 bit or 64 bit long type.
Signed-off-by: Yang Zhong
---
include/qemu/bitops.h | 7 +++
1 file changed, 7 insertions(+)
diff --git a/incl
From: Sean Christopherson
Signed-off-by: Sean Christopherson
Signed-off-by: Yang Zhong
---
docs/intel-sgx.txt | 173 +
1 file changed, 173 insertions(+)
create mode 100644 docs/intel-sgx.txt
diff --git a/docs/intel-sgx.txt b/docs/intel-sgx.txt
new
Since there is no fill_device_info() callback support, and when we
execute "info memory-devices" command in the monitor, the segfault
will be found.
This patch will add this callback support and "info memory-devices"
will show sgx epc memory exposed to guest. The result as below:
qemu) info memor
From: Sean Christopherson
Enable SGX EPC virtualization, which is currently only support by KVM.
Signed-off-by: Sean Christopherson
Signed-off-by: Yang Zhong
---
hw/i386/pc_q35.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c
index 53450190f5..e7af2
Add new CONFIG_SGX for sgx support in the Qemu, and the Kconfig
default enable sgx in the i386 platform.
Signed-off-by: Yang Zhong
---
backends/meson.build | 2 +-
default-configs/devices/i386-softmmu.mak | 1 +
hw/i386/Kconfig | 5 +
hw/i386/m
On Thu, 1 Apr 2021 at 03:41, Shashi Mallela wrote:
>
> Added functionality to trigger ITS command queue processing on
> write to CWRITE register and process each command queue entry to
> identify the command type and handle commands like MAPD,MAPC,SYNC.
>
> Signed-off-by: Shashi Mallela
> ---
>
This QMP query command can be used by some userspaces to retrieve
the SGX information when SGX is enabled on Intel platform.
Signed-off-by: Yang Zhong
---
monitor/qmp-cmds.c | 6 ++
qapi/misc.json | 42 ++
tests/qtest/qmp-cmd-test.c |
On 4/19/21 12:22 PM, Thomas Huth wrote:
> On 16/04/2021 18.27, Claudio Fontana wrote:
>> Skip the test_device_intro_concrete for now for ARM KVM-only build,
>> as on ARM we currently build devices for ARM that are not
>> compatible with a KVM-only build.
>>
>> We can remove this workaround when we
Mahmoud Mandour writes:
> Added a table-like output which contains the total number of calls
> for each used syscall along with the number of errors that occurred.
>
> Per-call tracing is still available through supplying the argument
> ``print`` to the plugin.
>
> Signed-off-by: Mahmoud Mandou
On 4/19/21 12:29 PM, Thomas Huth wrote:
> On 19/04/2021 12.24, Claudio Fontana wrote:
>> On 4/19/21 12:22 PM, Thomas Huth wrote:
>>> On 16/04/2021 18.27, Claudio Fontana wrote:
Skip the test_device_intro_concrete for now for ARM KVM-only build,
as on ARM we currently build devices for ARM
On Thu, 1 Apr 2021 at 03:41, Shashi Mallela wrote:
>
> Added properties to enable ITS feature and define qemu system
> address space memory in gicv3 common,setup distributor and
> redistributor registers to indicate LPI support.
>
> Signed-off-by: Shashi Mallela
> ---
> hw/intc/arm_gicv3_common.
On 19/04/2021 00.50, Philippe Mathieu-Daudé wrote:
Add a new job to cross-build the mips64el target without
the TCG accelerator (IOW: only KVM accelerator enabled).
Only build the mips64el target which is known to work
and has users.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathi
On Thu, 1 Apr 2021 at 03:41, Shashi Mallela wrote:
>
> Added ITS command queue handling for MAPTI,MAPI commands,handled ITS
> translation which triggers an LPI via INT command as well as write
> to GITS_TRANSLATER register,defined enum to differentiate between ITS
> command interrupt trigger and G
On Mon, Apr 19, 2021 at 12:20:55PM +0200, Thomas Huth wrote:
> On 19/04/2021 12.10, Erik Skultety wrote:
> > On Mon, Apr 19, 2021 at 10:40:53AM +0100, Daniel P. Berrangé wrote:
> > > On Mon, Apr 19, 2021 at 01:34:47AM +0200, Philippe Mathieu-Daudé wrote:
> > > > Forks run the same jobs than mainstr
On 17/04/2021 21.41, Peter Maydell wrote:
This pullreq contains fixes for the remaining "not fixed yet" issues
in the 6.0 Planning page:
* Fix compile failures of C++ files with new glib headers
* mps3-an547: Use correct Cortex-M55 CPU and don't disable its FPU
* accel/tcg: Fix assertion fa
On 19/04/2021 12.24, Claudio Fontana wrote:
On 4/19/21 12:22 PM, Thomas Huth wrote:
On 16/04/2021 18.27, Claudio Fontana wrote:
Skip the test_device_intro_concrete for now for ARM KVM-only build,
as on ARM we currently build devices for ARM that are not
compatible with a KVM-only build.
We can
On 4/19/21 12:10 PM, Erik Skultety wrote:
> On Mon, Apr 19, 2021 at 10:40:53AM +0100, Daniel P. Berrangé wrote:
>> On Mon, Apr 19, 2021 at 01:34:47AM +0200, Philippe Mathieu-Daudé wrote:
>>> Forks run the same jobs than mainstream, which might be overkill.
>>> Allow them to easily rebase their cust
I can confirm the issue also with latest official QEMU sources.
Related issue URLs:
https://github.com/tesseract-ocr/tesseract/issues/2838
https://bugs.launchpad.net/qemu/+bug/1924912
Instructions and files required to reproduce the issue:
https://qemu.weilnetz.de/test/bugs/1924912/
Michael,
On Mon, Apr 19, 2021 at 12:20:55PM +0200, Thomas Huth wrote:
> On 19/04/2021 12.10, Erik Skultety wrote:
> > On Mon, Apr 19, 2021 at 10:40:53AM +0100, Daniel P. Berrangé wrote:
> > > On Mon, Apr 19, 2021 at 01:34:47AM +0200, Philippe Mathieu-Daudé wrote:
> > > > Forks run the same jobs than mainstr
On 19/04/2021 12.36, Daniel P. Berrangé wrote:
On Mon, Apr 19, 2021 at 12:20:55PM +0200, Thomas Huth wrote:
On 19/04/2021 12.10, Erik Skultety wrote:
On Mon, Apr 19, 2021 at 10:40:53AM +0100, Daniel P. Berrangé wrote:
On Mon, Apr 19, 2021 at 01:34:47AM +0200, Philippe Mathieu-Daudé wrote:
For
On Mon, Apr 19, 2021 at 12:48:25PM +0200, Thomas Huth wrote:
> On 19/04/2021 12.36, Daniel P. Berrangé wrote:
> > On Mon, Apr 19, 2021 at 12:20:55PM +0200, Thomas Huth wrote:
> > > On 19/04/2021 12.10, Erik Skultety wrote:
> > > > On Mon, Apr 19, 2021 at 10:40:53AM +0100, Daniel P. Berrangé wrote:
Currently IO Command Set Profile feaure is supported, but
feature support flag not set and this feature is changable
add support for that.
Remove filling default value of feature in CQE CDW0 with zero,
since it fallbacks to default case and it is zero initialized,
if feature default value not set
On 19/04/2021 12.51, Daniel P. Berrangé wrote:
On Mon, Apr 19, 2021 at 12:48:25PM +0200, Thomas Huth wrote:
On 19/04/2021 12.36, Daniel P. Berrangé wrote:
On Mon, Apr 19, 2021 at 12:20:55PM +0200, Thomas Huth wrote:
On 19/04/2021 12.10, Erik Skultety wrote:
On Mon, Apr 19, 2021 at 10:40:53AM
On Apr 19 16:18, Gollu Appalanaidu wrote:
Currently IO Command Set Profile feaure is supported, but
feature support flag not set and this feature is changable
add support for that.
Remove filling default value of feature in CQE CDW0 with zero,
since it fallbacks to default case and it is zero in
Am 19.04.2021 um 10:36 hat Peter Lieven geschrieben:
>
>
> > Am 15.04.2021 um 17:22 schrieb Kevin Wolf :
> >
> > Peter, three years ago you changed 'qemu-img convert' to sacrifice some
> > sparsification in order to get aligned requests on the target image. At
> > the time, I thought the impact
Am 19.04.21 um 12:39 schrieb Stefan Weil:
I can confirm the issue also with latest official QEMU sources.
Related issue URLs:
https://github.com/tesseract-ocr/tesseract/issues/2838
Sorry, that URL was a copy+paste error. The correct one is
https://github.com/SerenityOS/serenity/issues/6422
On Sat, Apr 17, 2021 at 10:02 AM Markus Armbruster wrote:
>
> Marc-André Lureau writes:
>
> > Hi
> >
> > On Fri, Apr 16, 2021 at 6:59 PM Marc-André Lureau <
> > marcandre.lur...@gmail.com> wrote:
> >
> >> Hi
> >>
> >> On Fri, Apr 16, 2021 at 6:51 PM Markus Armbruster
> >> wrote:
> >>
> >>> Marc-
On Wed, 14 Apr 2021 19:40:36 -
Ed Davison <1923...@bugs.launchpad.net> wrote:
> The patch may be a bit beyond me at the moment as I use a package to
> install this and would have to figure out how to download source, get it
> configure, patched and compiled. Whew! Maybe ...
>
> But here is
On Fri, 16 Apr 2021 at 17:02, Gerd Hoffmann wrote:
> Hi,
>
> > I learned that the callback passed in AUD_open_out, (lets call it the
> write
> > audio callback,) is supposed to mix and write the
> > buffers to HWVoiceOut. I have written that, the basic algorithm being:
> >
> > 1. Pop element f
Am 19.04.2021 um 11:13 hat Peter Lieven geschrieben:
>
>
> > Am 19.04.2021 um 10:36 schrieb Peter Lieven :
> >
> >
> >
> >> Am 15.04.2021 um 17:22 schrieb Kevin Wolf :
> >>
> >> Peter, three years ago you changed 'qemu-img convert' to sacrifice some
> >> sparsification in order to get aligned
On Mon, 19 Apr 2021 at 18:00, Shreyansh Chouhan <
chouhan.shreyansh2...@gmail.com> wrote:
>
> On Fri, 16 Apr 2021 at 17:02, Gerd Hoffmann wrote:
>
>> Hi,
>>
>> > I learned that the callback passed in AUD_open_out, (lets call it the
>> write
>> > audio callback,) is supposed to mix and write th
On 4/16/21 7:38 PM, Patrick Venture wrote:
> On Fri, Apr 16, 2021 at 9:40 AM Cédric Le Goater wrote:
>>
>> Patrick,
>>
>> On 4/16/21 6:24 PM, Patrick Venture wrote:
>>> The Quanta-Q71l BMC board is a board supported by OpenBMC.
>>>
>>> Tested: Booted quanta-q71l firmware.
>>> Signed-off-by: Patric
On Thu, 1 Apr 2021 at 03:41, Shashi Mallela wrote:
>
> Included creation of ITS as part of SBSA platform GIC
> initialization.
>
> Signed-off-by: Shashi Mallela
> ---
> hw/arm/sbsa-ref.c | 26 +++---
> 1 file changed, 23 insertions(+), 3 deletions(-)
Reviewed-by: Peter Mayde
On Thu, 1 Apr 2021 at 03:41, Shashi Mallela wrote:
>
> Implemented lpi processing at redistributor to get lpi config info
> from lpi configuration table,determine priority,set pending state in
> lpi pending table and forward the lpi to cpuif.Added logic to invoke
> redistributor lpi processing wit
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