Move tlb_helper.c to the tcg/sysemu/ subdir, along with
the following 3 declarations to tcg-internal.h:
- cpu_mips_tlb_flush()
- cpu_mips_translate_address()
- r4k_invalidate_tlb()
Simplify tlb_helper.c #ifdef'ry because files in tcg/sysemu/
are only build when sysemu mode is configured.
Reviewed
Move the Special opcodes helpers to tcg/sysemu/special_helper.c.
Since mips_io_recompile_replay_branch() is set as
CPUClass::io_recompile_replay_branch handler in cpu.c,
we need to declare its prototype in "tcg-internal.h".
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
--
Move cp0_helper.c and mips-semi.c to the new tcg/sysemu/ folder,
adapting the Meson machinery.
Move the opcode definitions to tcg/sysemu_helper.h.inc.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/helper.h | 166 +
target/mips/tcg/sysemu_helper.h
Move helper_cache() to tcg/sysemu/special_helper.c.
The CACHE opcode is privileged and is not accessible in user
emulation. However we get a link failure when restricting the
symbol to sysemu. For now, add a stub helper to satisfy linking,
which abort if ever called.
Signed-off-by: Philippe Mathi
Move TLB management helpers to tcg/sysemu/tlb_helper.c.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/helper.h| 10 -
target/mips/internal.h | 7 -
target/mips/tcg/sysemu_helper.h.inc | 9 +
target/mips/op_helper.c
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/internal.h | 13 ---
target/mips/tcg/tcg-internal.h | 14 +++
target/mips/cpu.c | 113 --
target/mips/exception.c| 169 +
target
Only the malta and loongson3-virt machines support KVM.
Restrict the other machines to TCG:
- mipssim
- magnum
- pica61
- fuloong2e
- boston
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
hw/mips/meson.build | 11 +++
1 file changed, 7 insertions(+), 4 d
Opcodes accessing Coprocessor 0 are privileged.
Move the CP0 helpers to sysemu/ and simplify the #ifdef'ry.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/internal.h | 9 +--
target/mips/cpu.c | 103 ---
target
To ease maintenance, move all TCG specific files under the tcg/
sub-directory. Adapt the Meson machinery.
The following prototypes:
- mips_tcg_init()
- mips_cpu_do_unaligned_access()
- mips_cpu_do_transaction_failed()
can now be restricted to the "tcg-internal.h" header.
Reviewed-by: Richard Hend
Add a new job to cross-build the mips64el target without
the TCG accelerator (IOW: only KVM accelerator enabled).
Only build the mips64el target which is known to work
and has users.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
.gitlab-ci.d/crossbuilds.yml | 8 +
Patchew URL: https://patchew.org/QEMU/20210418225058.1257014-1-f4...@amsat.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20210418225058.1257014-1-f4...@amsat.org
Subject: [PATCH v2 00/29] target/mips: Re-org to al
TL;DR: Patch 13 is an experiment to dynamically generate pipelines.
Hi,
This series is an intent to allow git forks to use different set
of jobs than the ones used by the mainstream repository.
Currently, a fork gets the mainstream CI pipeline YAML configuration
and runs its set of jobs by defau
From: Philippe Mathieu-Daudé
'extends' is an alternative to using YAML anchors
and is a little more flexible and readable. See:
https://docs.gitlab.com/ee/ci/yaml/#extends
Reviewed-by: Wainer dos Santos Moschetta
Reviewed-by: Thomas Huth
Signed-off-by: Philippe Mathieu-Daudé
---
.gitlab-ci.d
From: Philippe Mathieu-Daudé
'extends' is an alternative to using YAML anchors
and is a little more flexible and readable. See:
https://docs.gitlab.com/ee/ci/yaml/#extends
Reviewed-by: Wainer dos Santos Moschetta
Signed-off-by: Philippe Mathieu-Daudé
---
.gitlab-ci.yml | 40 ++
Extract the build stages used by our job templates to a new file
(stages.yml) to be able to include it with the other templates,
without having to run all the jobs included in the default
.gitlab-ci.yml, which are mainly useful for mainstream CI.
Signed-off-by: Philippe Mathieu-Daudé
---
.gitlab
From: Philippe Mathieu-Daudé
'extends' is an alternative to using YAML anchors
and is a little more flexible and readable. See:
https://docs.gitlab.com/ee/ci/yaml/#extends
Reviewed-by: Wainer dos Santos Moschetta
Signed-off-by: Philippe Mathieu-Daudé
---
.gitlab-ci.yml | 64 ++
From: Philippe Mathieu-Daudé
'extends' is an alternative to using YAML anchors
and is a little more flexible and readable. See:
https://docs.gitlab.com/ee/ci/yaml/#extends
Reviewed-by: Wainer dos Santos Moschetta
Signed-off-by: Philippe Mathieu-Daudé
---
.gitlab-ci.yml | 20 ++
From: Philippe Mathieu-Daudé
The acceptance tests aren't accepting anything,
rename them as integration tests.
Reviewed-by: Wainer dos Santos Moschetta
Reviewed-by: Willian Rampazzo
Signed-off-by: Philippe Mathieu-Daudé
---
.gitlab-ci.yml | 20 ++--
1 file changed, 10 inserti
It is not possible to use the previously extracted templates
without this set of core containers. Extract them into a new
file (container-core.yml) to be able to build them without
having to build all the other containers by default.
Signed-off-by: Philippe Mathieu-Daudé
---
.gitlab-ci.d/contain
Extract the container job template to a new file
(container-template.yml) to be able to reuse it
without having to run all the jobs included, which
are mainly useful for mainstream CI.
Signed-off-by: Philippe Mathieu-Daudé
---
.gitlab-ci.d/container-template.yml | 22 ++
.git
Extract the build/test jobs run by default on the mainstream
CI into a new file (buildtest.yml) and their templates into
(buildtest-template.yml), to be able to reuse the templates
without having to run all these mainstream jobs by default.
Signed-off-by: Philippe Mathieu-Daudé
---
.gitlab-ci.d/
Extract the DCO / checkpatch jobs to a new file (checks.yml)
to be able to run them without having to run all the jobs
included in the default .gitlab-ci.yml, which are mainly useful
for mainstream CI.
Signed-off-by: Philippe Mathieu-Daudé
---
.gitlab-ci.d/checks.yml | 24 +++
This is an example to use a different set of jobs than the
mainstream one (currently 116 jobs).
Here I only select 2 jobs:
- cross-s390x-kvm-only
- build-libvhost-user
Including their dependencies, I have to run 8 jobs.
Result (build time 15 minutes and 25 seconds):
https://gitlab.com/philmd/q
Extract the crossbuild job templates to a new file
(crossbuild-template.yml) to be able to reuse them
without having to run all the jobs included, which
are mainly useful for mainstream CI.
Signed-off-by: Philippe Mathieu-Daudé
---
.gitlab-ci.d/crossbuild-template.yml | 41 ++
Forks run the same jobs than mainstream, which might be overkill.
Allow them to easily rebase their custom set, while keeping using
the mainstream templates, and ability to pick specific jobs from
the mainstream set.
To switch to your set, simply add your .gitlab-ci.yml as
.gitlab-ci.d/${CI_PROJEC
To allow forks to easily decide which jobs they want to run,
but without disrupting the current default, move the current
set of jobs to a new file corresponding to the jobs run by
the mainstream project CI:
https://gitlab.com/qemu-project/qemu/-/pipelines
Signed-off-by: Philippe Mathieu-Daudé
--
Switch to the dynamically generated pipeline scheme described in:
https://docs.gitlab.com/ee/ci/parent_child_pipelines.html#dynamic-child-pipelines
Signed-off-by: Philippe Mathieu-Daudé
---
.gitlab-ci.yml | 23 +--
1 file changed, 21 insertions(+), 2 deletions(-)
diff --git
On Sat, Apr 17, 2021 at 12:30:21PM +0200, Philippe Mathieu-Daudé wrote:
> The ASIC PCI bridge chipset from Motorola is named 'Raven'.
> This chipset is used in the PowerPC Reference Platform (PReP),
> but not restricted to it. Rename it accordingly.
>
> Signed-off-by: Philippe Mathieu-Daudé
Acke
On Sat, Apr 17, 2021 at 12:30:22PM +0200, Philippe Mathieu-Daudé wrote:
> Rather than using the magic 0x8000 number for the PCI I/O BAR
> physical address on the main system bus, use a definition.
>
> Signed-off-by: Philippe Mathieu-Daudé
Acked-by: David Gibson
> ---
> hw/pci-host/raven.c
On Sat, Apr 17, 2021 at 12:30:23PM +0200, Philippe Mathieu-Daudé wrote:
> Commit 1ae1dc5ba24 ("raven: Set a correct PCI I/O memory region")
> abused an AddressSpace API weakness which allows set non-zero base
> address to AddressSpace root region. We will fix that in the next
> commit. First add an
On Fri, Apr 16, 2021 at 11:13:48AM -0300, Matheus K. Ferst wrote:
> On 16/04/2021 00:52, David Gibson wrote:
> > On Thu, Apr 15, 2021 at 06:41:35PM -0300, matheus.fe...@eldorado.org.br
> > wrote:
> > > From: Matheus Ferst
> > >
> > > Based-on: <20210413211129.457272-1-luis.pi...@eldorado.org.br>
On Sat, Apr 17, 2021 at 10:36:20AM +0800, wangyanan (Y) wrote:
> Hi David,
>
> On 2021/4/16 12:52, David Gibson wrote:
> > On Tue, Apr 13, 2021 at 04:07:40PM +0800, Yanan Wang wrote:
> > > From: Andrew Jones
> > >
> > > qemu_fdt_add_path() works like qemu_fdt_add_subnode(), except
> > > it also
On Fri, Apr 16, 2021 at 06:09:41PM -0300, Daniel Henrique Barboza wrote:
> The Linux kernel will call set-indicator to move a DRC to 'unisolate' in
> the case a device removal fails. Setting a DRC that is already
Only issue I have with this patch is that this isn't quite accurate
yet. Can you rew
[Expired for QEMU because there has been no activity for 60 days.]
** Changed in: qemu
Status: Incomplete => Expired
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https://bugs.launchpad.net/bugs/1815445
Title:
change and
[Expired for QEMU because there has been no activity for 60 days.]
** Changed in: qemu
Status: Incomplete => Expired
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https://bugs.launchpad.net/bugs/1816189
Title:
Unable to c
[Expired for QEMU because there has been no activity for 60 days.]
** Changed in: qemu
Status: Incomplete => Expired
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https://bugs.launchpad.net/bugs/1815263
Title:
hvf acceler
On Thu, Apr 15, 2021 at 01:23:43PM +0530, Vaibhav Jain wrote:
> Add support for H_SCM_PERFORMANCE_STATS described at [1] for
> spapr nvdimms. This enables guest to fetch performance stats[2] like
> expected life of an nvdimm ('MemLife ') etc and display them to the
> user. Linux kernel support for
On Mon, Apr 12, 2021 at 05:14:32PM +0530, Ravi Bangoria wrote:
> Power10 is introducing second DAWR. Use real register names (with
> suffix 0) from ISA for current macros and variables used by Qemu.
>
> One exception to this is KVM_REG_PPC_DAWR[X]. This is from kernel
> uapi header and thus not ch
On Mon, Apr 12, 2021 at 05:14:33PM +0530, Ravi Bangoria wrote:
> As per the PAPR, bit 0 of byte 64 in pa-features property indicates
> availability of 2nd DAWR registers. i.e. If this bit is set, 2nd
> DAWR is present, otherwise not. Use KVM_CAP_PPC_DAWR1 capability to
> find whether kvm supports 2
On 16/04/2021 22.34, Nir Soffer wrote:
On Fri, Apr 16, 2021 at 8:23 AM Thomas Huth wrote:
A customer reported that running
qemu-img convert -t none -O qcow2 -f qcow2 input.qcow2 output.qcow2
fails for them with the following error message when the images are
stored on a GPFS file system:
On Wed, Apr 14, 2021 at 06:28:26PM +, Lucas Mateus Martins Araujo e Castro
wrote:
> Hi, I have been working on billionai's patch to enable the --disable-tcg
> option on PowerPC and one of the problems is that 5 files in hw/ppc use
> functions implemented in mmu-hash64.c which is not compiled
On 19/04/2021 01.34, Philippe Mathieu-Daudé wrote:
From: Philippe Mathieu-Daudé
The acceptance tests aren't accepting anything,
rename them as integration tests.
Reviewed-by: Wainer dos Santos Moschetta
Reviewed-by: Willian Rampazzo
Signed-off-by: Philippe Mathieu-Daudé
---
.gitlab-ci.yml
On 19/04/2021 01.34, Philippe Mathieu-Daudé wrote:
Extract the DCO / checkpatch jobs to a new file (checks.yml)
to be able to run them without having to run all the jobs
included in the default .gitlab-ci.yml, which are mainly useful
for mainstream CI.
Signed-off-by: Philippe Mathieu-Daudé
---
On Tue, Apr 13, 2021 at 06:38:57PM -0300, Fabiano Rosas wrote:
> Bruno Piazera Larsen writes:
>
> >> I'm actually not sure if we'll want translate_init.c for !tcg builds.
> >> It's *primarily* for TCG, but we still need at least some of the cpu
> >> state structure for KVM, and some of that is in
On Fri, Apr 09, 2021 at 12:19:15PM -0300, Bruno Larsen (billionai) wrote:
> This file basically adds all stubs required to build the project
> with disable-tcg. most of these are not going to remain stubs by the
> end, but this part is where it got complicated, and I wanted to get
> an RFC ASAP. Mo
On Tue, Apr 13, 2021 at 05:43:02PM +, Bruno Piazera Larsen wrote:
> > I'm actually not sure if we'll want translate_init.c for !tcg builds.
> > It's *primarily* for TCG, but we still need at least some of the cpu
> > state structure for KVM, and some of that is initialized in
> > translate_init
On 19/04/2021 01.34, Philippe Mathieu-Daudé wrote:
Extract the build/test jobs run by default on the mainstream
CI into a new file (buildtest.yml) and their templates into
(buildtest-template.yml), to be able to reuse the templates
without having to run all these mainstream jobs by default.
Sign
On 19/04/2021 01.34, Philippe Mathieu-Daudé wrote:
It is not possible to use the previously extracted templates
without this set of core containers. Extract them into a new
file (container-core.yml) to be able to build them without
having to build all the other containers by default.
Signed-off-
On Thu, Apr 08, 2021 at 05:40:49PM -0300, Daniel Henrique Barboza wrote:
> Certain SMP topologies stress, e.g. 1 thread/core, 2048 cores and
> 1 socket, stress the current maximum size of the pSeries FDT:
>
> Calling ibm,client-architecture-support...qemu-system-ppc64: error
> creating device tree
On Thu, Apr 08, 2021 at 05:40:48PM -0300, Daniel Henrique Barboza wrote:
> Up to this patch, 'max_cpus' value is hardcoded to 1024 (commit
> 6244bb7e5811). In theory this patch would simply bump it to 2048, since
> it's the default NR_CPUS kernel setting for ppc64 servers nowadays, but
> the whole
On 19/04/2021 01.34, Philippe Mathieu-Daudé wrote:
Forks run the same jobs than mainstream, which might be overkill.
Allow them to easily rebase their custom set, while keeping using
the mainstream templates, and ability to pick specific jobs from
the mainstream set.
To switch to your set, simpl
From: Frank Chang
In IEEE 754-2008 spec:
Invalid operation exception is signaled when doing:
fusedMultiplyAdd(0, Inf, c) or fusedMultiplyAdd(Inf, 0, c)
unless c is a quiet NaN; if c is a quiet NaN then it is
implementation defined whether the invalid operation exception
is signaled.
In
** Changed in: qemu
Status: Fix Released => Fix Committed
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https://bugs.launchpad.net/bugs/1919036
Title:
Assertion failure in fifo8_push_all() through am53c974
Status in QEMU:
** Changed in: qemu
Status: Fix Released => Fix Committed
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https://bugs.launchpad.net/bugs/1919035
Title:
Assertion failure in fifo8_pop_buf() through am53c974
Status in QEMU:
From: Frank Chang
Doing a negate (0x0 – 0x8000) using vssub.vv produces
an incorrect result of 0x8000 (should saturate to 0x7fff)
Fix this bug by treating zero as a positive number.
Signed-off-by: Frank Chang
---
target/riscv/vector_helper.c | 8
1 file changed, 4 inserti
From: Frank Chang
ETYPE may be type of uint64_t, thus index variable has to be declared as
type of uint64_t, too. Otherwise the value read from vs1 register may be
truncated to type of uint32_t.
Signed-off-by: Frank Chang
---
target/riscv/vector_helper.c | 6 --
1 file changed, 4 insertion
Looking through old bug tickets... is this still an issue with the
latest version of QEMU? Or could we close this ticket nowadays?
** Changed in: qemu
Status: New => Incomplete
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h
I think we fixed this at one point in time during the past two years ...
can we close this issue now, or could you still reproduce this with the
latest version of QEMU?
** Changed in: qemu
Status: New => Incomplete
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de
This series adds support for ePMP v0.9.1 to the QEMU RISC-V target.
This is based on previous patches, but has been rebased on the latest
master and updated for the latest spec.
The spec is avaliable at:
https://docs.google.com/document/d/1Mh_aiHYxemL0umN3GTTw8vsbmzHZ_nxZXgjgOUzbvc8
This was te
From: Hou Weiying
Use address 0x390 and 0x391 for the ePMP CSRs.
Signed-off-by: Hongzheng-Li
Signed-off-by: Hou Weiying
Signed-off-by: Myriad-Dreamin
Reviewed-by: Alistair Francis
Message-Id:
[ Changes by AF:
- Tidy up commit message
]
Signed-off-by: Alistair Francis
Reviewed-by: Bin Men
The spec is avaliable at:
https://docs.google.com/document/d/1Mh_aiHYxemL0umN3GTTw8vsbmzHZ_nxZXgjgOUzbvc8
Signed-off-by: Alistair Francis
Reviewed-by: Bin Meng
---
target/riscv/cpu.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 842d3ab810..13
The physical Ibex CPU has ePMP support and it's enabled for the
OpenTitan machine so let's enable ePMP support for the Ibex CPU in QEMU.
Signed-off-by: Alistair Francis
Reviewed-by: Bin Meng
---
target/riscv/cpu.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/cpu.c b/target/r
The RISC-V spec says:
if PMP entry i is locked and pmpicfg.A is set to TOR, writes to
pmpaddri-1 are ignored.
The current QEMU code ignores accesses to pmpaddri-1 and pmpcfgi-1 which
is incorrect.
Update the pmp_is_locked() function to not check the supporting fields
and instead enforce t
From: Hou Weiying
Signed-off-by: Hongzheng-Li
Signed-off-by: Hou Weiying
Signed-off-by: Myriad-Dreamin
Message-Id:
[ Changes by AF:
- Rebase on master
- Fix build errors
- Fix some style issues
]
Signed-off-by: Alistair Francis
Reviewed-by: Bin Meng
---
target/riscv/cpu.h| 1 +
From: Hou Weiying
Add a config option to enable experimental support for ePMP. This
is disabled by default and can be enabled with 'x-epmp=true'.
Signed-off-by: Hongzheng-Li
Signed-off-by: Hou Weiying
Signed-off-by: Myriad-Dreamin
Message-Id:
Signed-off-by: Alistair Francis
Reviewed-by: Bi
From: Hou Weiying
This commit adds support for ePMP v0.9.1.
The ePMP spec can be found in:
https://docs.google.com/document/d/1Mh_aiHYxemL0umN3GTTw8vsbmzHZ_nxZXgjgOUzbvc8
Signed-off-by: Hongzheng-Li
Signed-off-by: Hou Weiying
Signed-off-by: Myriad-Dreamin
Message-Id:
[ Changes by AF:
- Re
Signed-off-by: Alistair Francis
Reviewed-by: Bin Meng
---
target/riscv/pmp.c | 4
1 file changed, 4 deletions(-)
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index e1f5776316..78203291de 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -19,10 +19,6 @@
* this program.
On Mon, Apr 19, 2021 at 4:02 PM wrote:
>
> From: Frank Chang
>
> Doing a negate (0x0 – 0x8000) using vssub.vv produces
> an incorrect result of 0x8000 (should saturate to 0x7fff)
>
> Fix this bug by treating zero as a positive number.
>
> Signed-off-by: Frank Chang
Thanks for the pa
Alistair Francis 於 2021年4月19日 週一 下午2:28寫道：
> On Mon, Apr 19, 2021 at 4:02 PM wrote:
> >
> > From: Frank Chang
> >
> > Doing a negate (0x0 – 0x8000) using vssub.vv produces
> > an incorrect result of 0x8000 (should saturate to 0x7fff)
> >
> > Fix this bug by treating zero as a positi
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