When fdatasync() fails on a file backend we set a flag that
short-circuits any future attempts to call fdatasync(). The
first failure returns the true errno, but the later short-
circuited calls return a generic EIO. The latter is unhelpful
because fdatasync() can return a variety of errnos, includ
The VM stop process has to flush outstanding I/O and this is a critical
failure scenario that is hard to diagnose. Add a probe point that
records the flush return code.
Signed-off-by: Daniel P. Berrangé
---
softmmu/cpus.c | 7 ++-
softmmu/trace-events | 3 +++
2 files changed, 9 insert
** Description changed:
QEMU release version: v6.0.0-rc2
command line:
qemu-system-arm -machine mps3-an547 -nographic -kernel .elf
-semihosting -semihosting-config enable=on,target=native
host operating system: Linux ISCNR90TMR1S 5.4.72-microsoft-standard-WSL2
#1 SMP Wed Oct 28 23
Does your code enable the FPU (via the CPACR and, if running in
NonSecure) the NSACR? If not then a fault is exactly what you should
expect. (I believe the FVP has a non-standard behaviour where it will
enable the FPU by default even though real hardware does not behave that
way.)
--
You received
--8<---cut here---start->8---
Peter Maydell writes:
> On Thu, 15 Apr 2021 at 14:18, Peter Maydell wrote:
>>
>> On Thu, 18 Feb 2021 at 09:47, Alex Bennée wrote:
>> >
>> > There is no real need to use CF_NOCACHE here. As long as the TB isn't
>> > linked to oth
On 4/14/21 6:23 PM, Max Filippov wrote:
I see a few places where target/xtensa may do that. E.g. it does that on entry
to an exception handler to allow for debugging its first instruction.
No guest code
is consumed to make this decision, would size 1 work in that case?
I'll take a look.
Yes, an
Peter Maydell writes:
> On Wed, 14 Apr 2021 at 08:07, Markus Armbruster wrote:
>> In my opinion, management applications are better off with -nodefaults.
>> It's easier to understand than the complicated mess I'm going to
>> describe under "Long answer" below.
>
> Is there a mechanism to get QEM
On Thu, 15 Apr 2021 at 15:32, Alex Bennée wrote:
> --8<---cut here---start->8---
> accel/tcg: avoid re-translating one-shot instructions
>
> By definition a single instruction is capable of being an IO
> instruction. This avoids a problem of triggering a cpu_io_
Philippe Mathieu-Daudé writes:
> On 4/14/21 9:17 PM, Peter Maydell wrote:
>> (cc'ing people related to the recent 'extern "C"' patches and also
>> randomly Markus as somebody who's had opinions on header cleanups
>> in the past...)
>>
>> osdep.h as it stands today is a mix of two things:
>> (1)
On Thu, Apr 15, 2021 at 03:01:48PM +0200, Philippe Mathieu-Daudé wrote:
> We want the ARM maintainers and the qemu-arm@ list to be
> notified when this file is modified. Add an entry to the
> 'ARM TCG CPUs' section in the MAINTAINERS file.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> MAINTA
On Thu, 15 Apr 2021 at 02:24, Max Filippov wrote:
> I see a few places where target/xtensa may do that. E.g. it does that on entry
> to an exception handler to allow for debugging its first instruction.
That should now be handled by the common code, I think (see commits
a7ba744f4082ab and ba3c35d
Philippe Mathieu-Daudé writes:
> Introduce the 'query-accels' QMP command which returns a list
> of built-in accelerator names.
>
> - Accelerator is a QAPI enum of all existing accelerators,
>
> - AcceleratorInfo is a QAPI structure providing accelerator
> specific information. Currently the co
Ping
On Tue, Apr 13, 2021 at 11:37 PM Li Zhang wrote:
>
> For some scenarios, it needs to hot-add a monitor device.
> But QEMU doesn't support hotplug yet. It also works by adding
> a monitor with null backend by default and then change its
> backend to socket by QMP command "chardev-change".
>
>
"Zhang, Chen" writes:
>> -Original Message-
>> From: Qemu-devel > bounces+chen.zhang=intel@nongnu.org> On Behalf Of Dr. David Alan
>> Gilbert
>> Sent: Wednesday, March 24, 2021 4:01 AM
>> To: Zhang, Chen
>> Cc: Lukas Straub ; Li Zhijian
>> ; Jason Wang ; qemu-
>> dev ; Markus Armbrus
Added a table-like output which contains the total number of calls
for each used syscall along with the number of errors that occurred.
Per-call tracing is still available through supplying the argument
``print`` to the plugin.
Signed-off-by: Mahmoud Mandour
---
tests/plugin/syscall.c | 94
Peter, three years ago you changed 'qemu-img convert' to sacrifice some
sparsification in order to get aligned requests on the target image. At
the time, I thought the impact would be small, but it turns out that
this can end up wasting gigabytes of storagee (like converting a fully
zeroed 10 GB im
In order to avoid RMW cycles, is_allocated_sectors() treats zeroed areas
like non-zero data if the end of the checked area isn't aligned. This
can improve the efficiency of the conversion and was introduced in
commit 8dcd3c9b91a.
However, it comes with a correctness problem: qemu-img convert is
su
This demonstrates what happens when the block status changes in
sub-min_sparse granularity, but all of the parts are zeroed out. The
alignment logic in is_allocated_sectors() prevents that the target image
remains fully sparse as expected, but turns it into a data cluster of
explicit zeros.
Signed
On 4/15/21 2:44 AM, Markus Armbruster wrote:
John Snow writes:
Rename QAPIError to QAPISourceError, and then create a new QAPIError
class that serves as the basis for all of our other custom exceptions.
Isn't the existing QAPIError such a base class already? Peeking
ahead... aha, your new
On Wed, Apr 14, 2021 at 8:40 PM Doug Evans wrote:
> ... in preparation for adding ipv6 host forwarding support.
>
> Tested:
> avocado run tests/acceptance/hostfwd.py
>
> Signed-off-by: Doug Evans
> ---
>
> [...]
>
> diff --git a/tests/acceptance/hostfwd.py b/tests/acceptance/hostfwd.py
> new fil
On Thu, 15 Apr 2021 15:03:01 +0200
Ilya Leoshkevich wrote:
> If arch-specific code generates a translation block of size 0,
> tb_gen_code() may generate a spurious exception.
>
> Fix s390x (patch 1), ARM (patch 2) and xtensa (patch 3) and add an
> assertion in order to catch such situations earl
When a migration blocker is added nothing is reported to the user,
inability to migrate such guest may come as a late surprise. As a bare
minimum, we can print a warning. To not pollute the output for those, who
have no intention to migrate their guests, introduce '--no-migration'
option which both
Commit 561dbb41b1d7 "i386: Make migration fail when Hyper-V reenlightenment
was enabled but 'user_tsc_khz' is unset" forbade migrations with when guest
has opted for reenlightenment notifications but 'tsc-frequency' wasn't set
explicitly on the command line. This works but the migration fails late
Yes, I think I did:
SCB->NSACR |= (3U << 10U);/* enable Non-secure access to
CP10 and CP11 coprocessors */
__DSB();
__ISB();
SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */
(3U << 11U*2U) ); /* enable CP11 Full A
On 4/15/21 3:00 AM, Markus Armbruster wrote:
John Snow writes:
On 3/30/21 1:18 PM, John Snow wrote:
Realizing now that this commit topic is wrong :)
A prior version modified the assertion, I decided it was less churn to
simply add one.
I think ideally we'd have no assertions here and we'd r
On 4/15/21 3:15 AM, Markus Armbruster wrote:
John Snow writes:
No functional change.
Signed-off-by: John Snow
---
scripts/qapi/error.py | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/scripts/qapi/error.py b/scripts/qapi/error.py
index 2183b8c6b7..6ba54821c
On 4/15/21 4:54 PM, Peter Maydell wrote:
> On Thu, 15 Apr 2021 at 15:32, Alex Bennée wrote:
>> --8<---cut here---start->8---
>> accel/tcg: avoid re-translating one-shot instructions
>>
>> By definition a single instruction is capable of being an IO
>> instructio
On Thu, Apr 15, 2021 at 05:44:02PM +0200, Vitaly Kuznetsov wrote:
> When a migration blocker is added nothing is reported to the user,
> inability to migrate such guest may come as a late surprise. As a bare
> minimum, we can print a warning. To not pollute the output for those, who
> have no inten
Hi Drew,
On 4/15/21 3:23 PM, Andrew Jones wrote:
> On Thu, Apr 15, 2021 at 02:57:37PM +0200, Philippe Mathieu-Daudé wrote:
>> Use the recently added generic qtest_has_accel() method to
>> check if KVM is available.
>>
>> Suggested-by: Claudio Fontana
>> Signed-off-by: Philippe Mathieu-Daudé
>> -
Do you have a guest binary and QEMU commandline I can use to reproduce
the issue ?
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1923861
Title:
Hardfault when accessing FPSCR register
Status in QE
By definition a single instruction is capable of being an IO
instruction. This avoids a problem of triggering a cpu_io_recompile on
a non-recorded translation which then fails because it expects
tcg_tb_lookup() to succeed unconditionally. The normal use case
requires a TB to be able to resolve mach
On Thu, Apr 15, 2021 at 12:04 PM Daniel P. Berrangé wrote:
>
> On Thu, Apr 15, 2021 at 05:44:02PM +0200, Vitaly Kuznetsov wrote:
> > When a migration blocker is added nothing is reported to the user,
> > inability to migrate such guest may come as a late surprise. As a bare
> > minimum, we can pri
Hi,
This series aims at having accelerator-independent qtests
by querying a QEMU instance at runtime to check the list
of built-in accelerators.
First we add the 'query-accels' QMP command,
then we add the qtest_has_accel() method to libqtest,
finally we use this new method to allow running
bios-
* Daniel P. Berrangé (berra...@redhat.com) wrote:
> This is a critical failure scenario for migration that is hard to
> diagnose from existing probes. Most likely it is caused by an error
> from bdrv_flush(), but we're not logging the errno anywhere, hence
> this new probe.
>
> Signed-off-by: Dani
We want the ARM maintainers and the qemu-arm@ list to be
notified when this file is modified. Add an entry to the
'ARM TCG CPUs' section in the MAINTAINERS file.
Signed-off-by: Philippe Mathieu-Daudé
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
in
Introduce the qtest_has_accel() method which allows a runtime
query on whether a QEMU instance has an accelerator built-in.
Reviewed-by: Eric Blake
Signed-off-by: Philippe Mathieu-Daudé
---
Since v2:
- reworded (Eric)
Since v1:
- rename qtest_probe_accel() -> qtest_has_accel()
- run with -machin
* Daniel P. Berrangé (berra...@redhat.com) wrote:
> The VM stop process has to flush outstanding I/O and this is a critical
> failure scenario that is hard to diagnose. Add a probe point that
> records the flush return code.
>
> Signed-off-by: Daniel P. Berrangé
Reviewed-by: Dr. David Alan Gilbe
sve_tests_sve_off_kvm() and test_query_cpu_model_expansion_kvm()
tests are now only being run if KVM is available. Drop the TCG
fallback.
Suggested-by: Andrew Jones
Signed-off-by: Philippe Mathieu-Daudé
---
tests/qtest/arm-cpu-features.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
di
Now than we can probe if the TCG accelerator is available
at runtime with a QMP command, do it once at the beginning
and only register the tests we can run.
We can then replace the #ifdef'ry by an assertion.
Reviewed-by: Eric Blake
Signed-off-by: Philippe Mathieu-Daudé
---
Since v1: use global t
Now than we can probe if the TCG accelerator is available
at runtime with a QMP command, do it once at the beginning
and only register the tests we can run.
We can then replace the #ifdef'ry by a runtime check.
Suggested-by: Paolo Bonzini
Signed-off-by: Philippe Mathieu-Daudé
---
tests/qtest/qm
Introduce the 'query-accels' QMP command which returns a list
of built-in accelerator names.
- Accelerator is a QAPI enum of all existing accelerators,
- AcceleratorInfo is a QAPI structure providing accelerator
specific information. Currently the common structure base
provides the name of th
Now than we can probe if the TCG accelerator is available
at runtime with a QMP command, only run these tests if TCG
is built into the QEMU binary.
Suggested-by: Andrew Jones
Signed-off-by: Philippe Mathieu-Daudé
---
tests/qtest/arm-cpu-features.c | 16 +---
1 file changed, 9 insert
* Daniel P. Berrangé (berra...@redhat.com) wrote:
> A flush failure is a critical failure scenario for some operations.
> For example, it will prevent migration from completing, as it will
> make vm_stop() report an error. Thus it is important to have a
> trace point present for debugging.
>
> Sig
From: Philippe Mathieu-Daudé
The previous attempt (commit f77147cd4de) doesn't work as
expected, as we still have CONFIG_TCG=1 when using:
configure --disable-system --disable-user
Now than we have removed the use of CONFIG_TCG from target-dependent
files in tests/qtest/, we can remove the un
Use the recently added generic qtest_has_accel() method to
check if KVM is available.
Suggested-by: Claudio Fontana
Signed-off-by: Philippe Mathieu-Daudé
---
tests/qtest/arm-cpu-features.c | 25 +
1 file changed, 1 insertion(+), 24 deletions(-)
diff --git a/tests/qtest/
From: Alessandro Di Federico
Signed-off-by: Alessandro Di Federico
---
target/hexagon/README | 5 +
target/hexagon/idef-parser/README.rst | 447 ++
2 files changed, 452 insertions(+)
create mode 100644 target/hexagon/idef-parser/README.rst
diff --git
From: Alessandro Di Federico
This patchset introduces the idef-parser for target/hexagon.
It's the fourth iteration of the patchset and includes fixes suggested
in previous iterations.
`idef-parser` is a build-time tool built using flex and bison. Its aim
is to generate a large part of the tiny
From: Paolo Montesel
Make certain helper functions non-static, making them available outside
genptr.c. These functions are required by code generated by the
idef-parser.
Signed-off-by: Alessandro Di Federico
Signed-off-by: Paolo Montesel
---
target/hexagon/genptr.c | 7 ---
target/hexagon
The sve_tests_sve_off_kvm() test is KVM specific.
Only run it if KVM is available.
Suggested-by: Andrew Jones
Signed-off-by: Philippe Mathieu-Daudé
---
tests/qtest/arm-cpu-features.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/tests/qtest/arm-cpu-features.c b/tests/q
From: Alessandro Di Federico
Introduce infrastructure necessary to produce a file suitable for being
parsed by the idef-parser.
Signed-off-by: Alessandro Di Federico
---
target/hexagon/gen_idef_parser_funcs.py | 114 ++
target/hexagon/idef-parser/macros.inc | 150
From: Niccolò Izzo
These helpers will be employed by the idef-parser generated code.
Signed-off-by: Alessandro Di Federico
Signed-off-by: Niccolò Izzo
---
target/hexagon/genptr.c | 188
target/hexagon/genptr.h | 22 +
target/hexagon/macros.h | 9
From: Niccolò Izzo
Signed-off-by: Alessandro Di Federico
Signed-off-by: Niccolò Izzo
---
tests/tcg/hexagon/Makefile.target | 36 -
tests/tcg/hexagon/crt.S| 28 +
tests/tcg/hexagon/test_abs.S | 20 ++
tests/tcg/hexagon/test_add.S | 20
We might have a s390x/ppc64 QEMU binary built without the KVM
accelerator (configured with --disable-kvm).
Checking for /dev/kvm accessibility isn't enough, also check for the
accelerator in the binary.
Signed-off-by: Philippe Mathieu-Daudé
---
Cc: David Gibson
Cc: Greg Kurz
Cc: Halil Pasic
Cc
From: Paolo Montesel
Signed-off-by: Alessandro Di Federico
Signed-off-by: Paolo Montesel
---
target/hexagon/idef-parser/idef-parser.h | 254
target/hexagon/idef-parser/idef-parser.lex| 611 ++
target/hexagon/meson.build| 4 +
tests/docker
From: Paolo Montesel
Signed-off-by: Alessandro Di Federico
Signed-off-by: Paolo Montesel
---
target/hexagon/idef-parser/idef-parser.y | 947 +++
target/hexagon/idef-parser/parser-helpers.c | 2374 +
target/hexagon/idef-parser/parser-helpers.h | 347 +++
target/he
On Thu, Apr 15, 2021 at 12:30:11PM -0400, Eduardo Habkost wrote:
> On Thu, Apr 15, 2021 at 12:04 PM Daniel P. Berrangé
> wrote:
> >
> > On Thu, Apr 15, 2021 at 05:44:02PM +0200, Vitaly Kuznetsov wrote:
> > > When a migration blocker is added nothing is reported to the user,
> > > inability to mig
Since commit 82bf7ae84ce ("target/arm: Remove KVM support for
32-bit Arm hosts") we can remove the comment / check added in
commit ab6b6a4 and directly run the bios-tables-test.
Reviewed-by: Eric Blake
Signed-off-by: Philippe Mathieu-Daudé
---
tests/qtest/meson.build | 3 +--
1 file changed
* Daniel P. Berrangé (berra...@redhat.com) wrote:
> Signed-off-by: Daniel P. Berrangé
Reviewed-by: Dr. David Alan Gilbert
> ---
> block/file-posix.c | 2 --
> 1 file changed, 2 deletions(-)
>
> diff --git a/block/file-posix.c b/block/file-posix.c
> index 6aafeda44f..2538e43299 100644
> --- a/
From: Alessandro Di Federico
Extend gen_tcg_funcs.py in order to emit calls to the functions emitted
by the idef-parser, if available.
Signed-off-by: Alessandro Di Federico
---
target/hexagon/gen_tcg_funcs.py | 28 ++--
target/hexagon/hex_common.py| 10 ++
t
On Thu, Apr 15, 2021 at 06:32:57PM +0200, Philippe Mathieu-Daudé wrote:
> The sve_tests_sve_off_kvm() test is KVM specific.
> Only run it if KVM is available.
>
> Suggested-by: Andrew Jones
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> tests/qtest/arm-cpu-features.c | 4 ++--
> 1 file changed
From: Alessandro Di Federico
Signed-off-by: Alessandro Di Federico
---
MAINTAINERS | 8
1 file changed, 8 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 36055f14c5..158badbd18 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -193,11 +193,19 @@ Hexagon TCG CPUs
M: Taylor Simp
On Thu, Apr 15, 2021 at 06:32:56PM +0200, Philippe Mathieu-Daudé wrote:
> Use the recently added generic qtest_has_accel() method to
> check if KVM is available.
>
> Suggested-by: Claudio Fontana
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> tests/qtest/arm-cpu-features.c | 25 +--
On 4/15/21 3:30 PM, Greg Kurz wrote:
> On Thu, 15 Apr 2021 14:39:55 +0200
> Philippe Mathieu-Daudé wrote:
>
>> On 4/9/21 6:03 PM, Greg Kurz wrote:
>>> Despite its simple name and common usage of "getting a pointer to
>>> the machine" in system-mode emulation, qdev_get_machine() has some
>>> subti
On Thu, 15 Apr 2021 18:45:45 +0200
Philippe Mathieu-Daudé wrote:
> On 4/15/21 3:30 PM, Greg Kurz wrote:
> > On Thu, 15 Apr 2021 14:39:55 +0200
> > Philippe Mathieu-Daudé wrote:
> >
> >> On 4/9/21 6:03 PM, Greg Kurz wrote:
> >>> Despite its simple name and common usage of "getting a pointer to
>
From: Paolo Montesel
Signed-off-by: Alessandro Di Federico
Signed-off-by: Paolo Montesel
---
target/hexagon/genptr.c | 6 --
target/hexagon/macros.h | 2 +-
2 files changed, 5 insertions(+), 3 deletions(-)
diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c
index 7481f4c1dd..fd
On Thu, Apr 15, 2021 at 06:32:58PM +0200, Philippe Mathieu-Daudé wrote:
> sve_tests_sve_off_kvm() and test_query_cpu_model_expansion_kvm()
> tests are now only being run if KVM is available. Drop the TCG
> fallback.
>
> Suggested-by: Andrew Jones
> Signed-off-by: Philippe Mathieu-Daudé
> ---
>
Command line is
qemu-system-arm -machine mps3-an547 -nographic -kernel test.elf -semihosting
-semihosting-config enable=on,target=native
Binary is attached. It does
int main(int argc, char* argv[])
{
SCB->NSACR |= (3U << 10U);/* enable Non-secure access to
CP10 and CP11 copr
From: Alessandro Di Federico
This commit moves into a separate file routines used to manipulate
TCGCond. These will be employed by the idef-parser.
Signed-off-by: Alessandro Di Federico
Signed-off-by: Paolo Montesel
---
include/tcg/tcg-cond.h | 101 +
i
On 4/14/21 12:11 PM, Richard Henderson wrote:
This approach seems like it will work fine for MLS and MMIR prefixes. For 8LS,
8RR, and MRR prefixes, we'll need some extra help within ppc_tr_translate_insn.
E.g.
insn = translator_ldl_swap(env, ctx->base.pc_next,
On Apr 15 15:13, Philippe Mathieu-Daudé wrote:
On 4/15/21 2:00 PM, Gollu Appalanaidu wrote:
Make uniform hexadecimal numbers format.
Signed-off-by: Gollu Appalanaidu
---
-v2: Address review comments (Klaus)
use lower case hexa format for the code and in comments
use the same format as used in
From: Paolo Montesel
Signed-off-by: Alessandro Di Federico
Signed-off-by: Paolo Montesel
---
target/hexagon/translate.c | 3 ++-
target/hexagon/translate.h | 1 +
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c
index eeaad5f
Hi Paolo,
Can you specify how to reproduce the issue ? We need more details about
environment.
In my case, everything seems to work fine for the newest version of glib (2.68).
Thank you,
Aleksandar
> qemu/osdep.h is quite special in that, despite being part of QEMU sources,
> it is included by
* Daniel P. Berrangé (berra...@redhat.com) wrote:
> On Thu, Apr 15, 2021 at 05:44:02PM +0200, Vitaly Kuznetsov wrote:
> > When a migration blocker is added nothing is reported to the user,
> > inability to migrate such guest may come as a late surprise. As a bare
> > minimum, we can print a warning
On Thu, Apr 15, 2021 at 06:32:59PM +0200, Philippe Mathieu-Daudé wrote:
> Now than we can probe if the TCG accelerator is available
> at runtime with a QMP command, only run these tests if TCG
> is built into the QEMU binary.
>
> Suggested-by: Andrew Jones
> Signed-off-by: Philippe Mathieu-Daudé
On Thu, 15 Apr 2021 at 18:18, Cédric Le Goater wrote:
>
> On 4/15/21 5:55 PM, Philippe Mathieu-Daudé wrote:
> > On 4/15/21 4:54 PM, Peter Maydell wrote:
> >> On Thu, 15 Apr 2021 at 15:32, Alex Bennée wrote:
> >>> --8<---cut here---start->8---
> >>> accel/tcg: a
On Thu, Apr 15, 2021 at 05:40:40PM +0100, Daniel P. Berrangé wrote:
> On Thu, Apr 15, 2021 at 12:30:11PM -0400, Eduardo Habkost wrote:
> > On Thu, Apr 15, 2021 at 12:04 PM Daniel P. Berrangé
> > wrote:
> > >
> > > Is it possible to query the migration blockers via QMP ?
> >
> > I don't think it
On Thu, Apr 15, 2021 at 5:13 AM Corey Minyard wrote:
>
> On Mon, Apr 12, 2021 at 12:45:18PM -0700, Patrick Venture wrote:
> > The i2c mux device pca954x implements two devices:
> > - the pca9546 and pca9548.
>
> This looks good, I have pulled it into my queue. 6.0 is about to be
> released, I'll
On 4/15/21 5:55 PM, Philippe Mathieu-Daudé wrote:
> On 4/15/21 4:54 PM, Peter Maydell wrote:
>> On Thu, 15 Apr 2021 at 15:32, Alex Bennée wrote:
>>> --8<---cut here---start->8---
>>> accel/tcg: avoid re-translating one-shot instructions
>>>
>>> By definition a s
Hi all,
This patch makes locally used symbols static to enable more compiler
optimizations on them. Some of the symbols turned out to not be used
at all so I marked them with ATTRIBUTE_UNUSED (as I wasn't sure if
they were ok to delete).
The symbols have been identified with a pet project of mine
On Thu, 15 Apr 2021 at 17:25, Alex Bennée wrote:
>
> By definition a single instruction is capable of being an IO
> instruction. This avoids a problem of triggering a cpu_io_recompile on
> a non-recorded translation which then fails because it expects
> tcg_tb_lookup() to succeed unconditionally.
On 4/15/21 9:24 AM, Alex Bennée wrote:
By definition a single instruction is capable of being an IO
instruction. This avoids a problem of triggering a cpu_io_recompile on
a non-recorded translation which then fails because it expects
tcg_tb_lookup() to succeed unconditionally. The normal use case
Peter Maydell writes:
> On Thu, 15 Apr 2021 at 17:25, Alex Bennée wrote:
>>
>> By definition a single instruction is capable of being an IO
>> instruction. This avoids a problem of triggering a cpu_io_recompile on
>> a non-recorded translation which then fails because it expects
>> tcg_tb_look
SSE-300 currently shares the SSE-200 Property array. This is
bad principally because the default values of the CPU0_FPU
and CPU0_DSP properties disable the FPU and DSP on the CPU.
That is correct for the SSE-300 but not the SSE-200.
Give the SSE-300 its own Property array with the correct
SSE-300 s
Public bug reported:
QEMU cmdline:
=
./x86_64-softmmu/qemu-system-x86_64 -machine accel=kvm -m 2G -hda
/gautam/centos75_1.qcow2 -name gautam,process=gautam -enable-kvm -netdev
vhost-vdpa,id=mynet0,vhostdev=/dev/vhost-vdpa-0 -device
virtio-net-pci,netdev=mynet0,mac=02:AA:BB:DD:00:20
On Thu, 15 Apr 2021 at 19:13, Alex Bennée wrote:
>
>
> Peter Maydell writes:
>
> > On Thu, 15 Apr 2021 at 17:25, Alex Bennée wrote:
> >>
> >> By definition a single instruction is capable of being an IO
> >> instruction. This avoids a problem of triggering a cpu_io_recompile on
> >> a non-record
QEMU version: 5.1.0
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https://bugs.launchpad.net/bugs/1924603
Title:
Incorrect feature negotiation for vhost-vdpa netdevice
Status in QEMU:
New
Bug description:
QEMU cmdline:
==
Thanks. This is a bug in the AN547 model -- we were accidentally turning
off the FPU. I'll write a patch.
NB that with that bug fixed your code then hits an UNDEF trying to do:
0x0996: eef7 1a10 vmrs r1, mvfr0
Only A-profile CPUs have MVFR0 accessible via the vmrs instruction. For
M-p
On Thu, 15 Apr 2021 at 19:23, Peter Maydell wrote:
>
> SSE-300 currently shares the SSE-200 Property array. This is
> bad principally because the default values of the CPU0_FPU
> and CPU0_DSP properties disable the FPU and DSP on the CPU.
> That is correct for the SSE-300 but not the SSE-200.
Sho
The bug fix for the QEMU part of this is
https://patchew.org/QEMU/20210415182353.8173-1-peter.mayd...@linaro.org/
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https://bugs.launchpad.net/bugs/1923861
Title:
Hardfault when accessi
Hi all!
Recently I've implemented fast-cancelling of mirror job: do
bdrv_cancel_in_flight() in mirror_cancel().
Now I'm in doubt: is it a correct thing? I heard, that mirror-cancel is a kind
of valid mirror completion..
Looking at documentation:
# Note that if you issue 'block-job-cancel' af
On 4/15/21 6:56 PM, Greg Kurz wrote:
> On Thu, 15 Apr 2021 18:45:45 +0200
> Philippe Mathieu-Daudé wrote:
>
>> On 4/15/21 3:30 PM, Greg Kurz wrote:
>>> On Thu, 15 Apr 2021 14:39:55 +0200
>>> Philippe Mathieu-Daudé wrote:
>>>
On 4/9/21 6:03 PM, Greg Kurz wrote:
> Despite its simple name
* Paolo Bonzini (pbonz...@redhat.com) wrote:
> On 06/04/21 13:42, Vitaly Kuznetsov wrote:
> > older machine types are still available (I disable it for <= 5.1 but we
> > can consider disabling it for 5.2 too). The feature is upstream since
> > Linux 5.8, I know that QEMU supports much older kernels
On 4/15/21 8:58 AM, Daniel P. Berrangé wrote:
I spent a while debugging a tricky migration failure today which was
ultimately caused by fdatasync() getting EACCESS. The existing probes
were not sufficient to diagnose this, so I had to resort to GDB. This
improves probes and block error reporting
On 4/15/21 8:23 PM, Peter Maydell wrote:
> SSE-300 currently shares the SSE-200 Property array. This is
> bad principally because the default values of the CPU0_FPU
> and CPU0_DSP properties disable the FPU and DSP on the CPU.
> That is correct for the SSE-300 but not the SSE-200.
> Give the SSE-30
On Thu, Apr 15, 2021 at 6:03 AM Ilya Leoshkevich wrote:
>
> tb_gen_code() assumes that tb->size must never be zero, otherwise it
> may produce spurious exceptions. For xtensa this may happen when
> decoding an unknown instruction, when handling a write into the
> CCOUNT or CCOMPARE special registe
On Thu, Apr 15, 2021 at 8:03 AM Peter Maydell wrote:
>
> On Thu, 15 Apr 2021 at 02:24, Max Filippov wrote:
> > I see a few places where target/xtensa may do that. E.g. it does that on
> > entry
> > to an exception handler to allow for debugging its first instruction.
>
> That should now be handl
target/xtensa used to generate an extra EXCP_DEBUG exception before the
first instruction executed after an interrupt or an exception is taken
to allow single-stepping that instruction in the debugger.
This is no longer needed after the following commits:
a7ba744f4082 ("tcg/cpu-exec: precise single
The premise behind the original behavior is that it would save people
from downloading Avocado (and other dependencies) if already installed
on the system. To be honest, I think it's extremely rare that the
same versions described as dependencies will be available on most
systems. But, the bigges
These tests' setUp do not do anything beyong what their base class do.
And while they do decorate the setUp() we can decorate the classes
instead, so no functionality is lost here.
Signed-off-by: Cleber Rosa
---
tests/acceptance/linux_ssh_mips_malta.py | 7 ++-
1 file changed, 2 insertions(+
Different users (or even companies) have different interests, and
may want to run a reduced set of tests during development, or a
larger set of tests during QE.
To cover these use cases, this introduces some example (but
functional) jobs.
It's expected that some common jobs will come up from comm
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