When posix access acls are set on a file, it can lead to adjusting file
permissions (mode) as well. If caller does not have CAP_FSETID and it
also does not have membership of owner group, this will lead to clearing
SGID bit in mode.
Current fuse code is written in such a way that it expects file s
Hi Vaibhav,
Great to see you around :-)
On Mon, 29 Mar 2021 21:52:59 +0530
Vaibhav Jain wrote:
> Add support for H_SCM_HEALTH hcall described at [1] for spapr
> nvdimms. This enables guest to detect the 'unarmed' status of a
> specific spapr nvdimm identified by its DRC and if its unarmed, mark
On 30/03/21 16:13, Stefan Hajnoczi wrote:
On Tue, Mar 30, 2021 at 01:55:48PM +0200, Thomas Huth wrote:
On 30/03/2021 13.19, Daniel P. Berrangé wrote:
On Mon, Mar 29, 2021 at 03:10:36PM +0100, Stefan Hajnoczi wrote:
Hi,
I wanted to follow up with a summary of the CI jobs:
1. Containers & Conta
On Tue, Mar 30, 2021 at 04:23:35PM +0200, Paolo Bonzini wrote:
> On 30/03/21 16:13, Stefan Hajnoczi wrote:
> > On Tue, Mar 30, 2021 at 01:55:48PM +0200, Thomas Huth wrote:
> > > On 30/03/2021 13.19, Daniel P. Berrangé wrote:
> > > > On Mon, Mar 29, 2021 at 03:10:36PM +0100, Stefan Hajnoczi wrote:
>
On Tuesday, 2021-03-30 at 14:36:03 +02, Vitaly Kuznetsov wrote:
> Commit 561dbb41b1d7 "i386: Make migration fail when Hyper-V reenlightenment
> was enabled but 'user_tsc_khz' is unset" forbade migrations with when guest
> has opted for reenlightenment notifications but 'tsc-frequency' wasn't set
>
From: Paolo Montesel
Make certain helper functions non-static, making them available outside
genptr.c. These functions are required by code generated by the
idef-parser.
Signed-off-by: Alessandro Di Federico
Signed-off-by: Paolo Montesel
---
target/hexagon/genptr.c | 7 ---
target/hexagon
From: Alessandro Di Federico
This commit moves into a separate file routines used to manipulate
TCGCond. These will be employed by the idef-parser.
Signed-off-by: Alessandro Di Federico
Signed-off-by: Paolo Montesel
---
include/tcg/tcg-cond.h | 101 +
i
Hi
On Tue, Mar 30, 2021 at 4:12 PM Peter Maydell
wrote:
> On Tue, 30 Mar 2021 at 09:29, Marc-André Lureau
> wrote:
> >
> > Hi
> >
> > On Mon, Mar 29, 2021 at 9:54 PM Peter Maydell
> wrote:
> >> aarch64 CI machine, which has python 3.8.5 and sphinx-build 1.8.5.
> >> My guess is that it might be
From: Alessandro Di Federico
Signed-off-by: Alessandro Di Federico
---
target/hexagon/README | 5 +
target/hexagon/idef-parser/README.rst | 447 ++
2 files changed, 452 insertions(+)
create mode 100644 target/hexagon/idef-parser/README.rst
diff --git
From: Paolo Montesel
Signed-off-by: Alessandro Di Federico
Signed-off-by: Paolo Montesel
---
target/hexagon/translate.c | 3 ++-
target/hexagon/translate.h | 1 +
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c
index eeaad5f
From: Paolo Montesel
Signed-off-by: Alessandro Di Federico
Signed-off-by: Paolo Montesel
---
target/hexagon/genptr.c | 6 --
target/hexagon/macros.h | 2 +-
2 files changed, 5 insertions(+), 3 deletions(-)
diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c
index 7481f4c1dd..fd
From: Paolo Montesel
Signed-off-by: Alessandro Di Federico
Signed-off-by: Paolo Montesel
---
target/hexagon/idef-parser/idef-parser.h | 240 +++
target/hexagon/idef-parser/idef-parser.lex| 611 ++
target/hexagon/meson.build| 4 +
tests/docker/
From: Alessandro Di Federico
This patchset introduces the idef-parser for target/hexagon.
It's the third iteration of the patchset and includes fixes suggested
in the previous iteration.
`idef-parser` is a build-time tool built using flex and bison. Its aim
is to generate a large part of the ti
From: Alessandro Di Federico
Signed-off-by: Alessandro Di Federico
---
MAINTAINERS | 8
1 file changed, 8 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 554be84b32..13de7ecc36 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -194,11 +194,19 @@ Hexagon TCG CPUs
M: Taylor Simp
From: Alessandro Di Federico
Introduce infrastructure necessary to produce a file suitable for being
parsed by the idef-parser.
Signed-off-by: Alessandro Di Federico
---
target/hexagon/gen_idef_parser_funcs.py | 114 ++
target/hexagon/idef-parser/macros.inc | 150
From: Niccolò Izzo
Signed-off-by: Alessandro Di Federico
Signed-off-by: Niccolò Izzo
---
tests/tcg/hexagon/Makefile.target | 35 -
tests/tcg/hexagon/crt.S| 28 +
tests/tcg/hexagon/test_abs.S | 20 ++
tests/tcg/hexagon/test_add.S | 20
tags/linux-user-for-6.0-pull-request
for you to fetch changes up to 13e340c886679fb17df02a35e7d82cb8beb6e9f4:
linux-user: NETLINK_LIST_MEMBERSHIPS: Allow bad ptr if its length is 0 (202=
1-03-29 21:56:18 +0200)
linux-user Pull reques
From: Niccolò Izzo
These helpers will be employed by the idef-parser generated code.
Signed-off-by: Alessandro Di Federico
Signed-off-by: Niccolò Izzo
---
target/hexagon/genptr.c | 173
target/hexagon/genptr.h | 17
target/hexagon/macros.h | 9
From: Alessandro Di Federico
Extend gen_tcg_funcs.py in order to emit calls to the functions emitted
by the idef-parser, if available.
Signed-off-by: Alessandro Di Federico
---
target/hexagon/gen_tcg_funcs.py | 28 ++--
target/hexagon/hex_common.py| 10 ++
t
From: Frédéric Fortier
getsockopt(fd, SOL_NETLINK, NETLINK_LIST_MEMBERSHIPS, *optval, *optlen)
syscall allows optval to be NULL/invalid if optlen points to a size of
zero. This allows userspace to query the length of the array they should
use to get the full membership list before allocating memo
From: Paolo Montesel
Signed-off-by: Alessandro Di Federico
Signed-off-by: Paolo Montesel
---
target/hexagon/idef-parser/idef-parser.y | 940 +++
target/hexagon/idef-parser/parser-helpers.c | 2230 +
target/hexagon/idef-parser/parser-helpers.h | 344 +++
target/he
On Tue, 30 Mar 2021 15:23:49 +0530
Ravi Bangoria wrote:
> Power10 is introducing second DAWR. Use real register names (with
> suffix 0) from ISA for current macros and variables used by Qemu.
>
> One exception to this is KVM_REG_PPC_DAWR[X]. This is from kernel
> uapi header and thus not changed
On 3/29/21 10:54 PM, David Gibson wrote:
B) Just the hflags patches from my / Richard's tree
https://gitlab.com/dgibson/qemu/-/pipelines/278497244
Look closer at this one -- it's an s390x test that's failing:
make: *** [/builds/dgibson/qemu/tests/Makefile.include:63:
run-tcg-tests-s3
On 3/29/21 5:02 AM, Alex Bennée wrote:
Currently our gitlab registry is x86_64 only so attempting to pull an
image from it on something else will end in tears.
Signed-off-by: Alex Bennée
---
tests/docker/Makefile.include | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
Reviewed-by:
On 3/29/21 5:02 AM, Alex Bennée wrote:
You don't usually notice this is broken on developer system on x86 as
we use the normal host compiler. However on other systems the -pc was
extraneous. Also for 32 bit only i686 packages exist now so we should
use those when available.
Signed-off-by: Alex B
On 3/29/21 5:03 AM, Alex Bennée wrote:
Newer compilers might end up putting some data in .data.rel.local
which was getting skipped resulting in hilarious confusion on some
tests. Fix that.
Signed-off-by: Alex Bennée
---
tests/tcg/i386/system/kernel.ld | 2 +-
1 file changed, 1 insertion(+), 1
On Thu, Mar 25, 2021 at 12:29:36PM +0100, Paolo Bonzini wrote:
> From: David Edmondson
>
> If a new bitmap entry is allocated, requiring the entire block to be
> written, avoiding leaking the buffer allocated for the block should
> the write fail.
>
> Reviewed-by: Philippe Mathieu-Daudé
> Signe
On Thu, Mar 25, 2021 at 12:29:38PM +0100, Paolo Bonzini wrote:
> From: David Edmondson
>
> When taking the slow path for mutex acquisition, set the coroutine
> value in the CoWaitRecord in push_waiter(), rather than both there and
> in the caller.
>
> Reviewed-by: Paolo Bonzini
> Reviewed-by: P
On Thu, Mar 25, 2021 at 12:29:37PM +0100, Paolo Bonzini wrote:
> From: David Edmondson
>
> Given that the block size is read from the header of the VDI file, a
> wide variety of sizes might be seen. Rather than re-using a block
> sized memory region when writing the VDI header, allocate an
> appr
On Tue, 30 Mar 2021 at 13:40, Max Reitz wrote:
>
> The following changes since commit ec2e6e016d24bd429792d08cf607e4c5350dcdaa:
>
> Merge remote-tracking branch
> 'remotes/vivier2/tags/linux-user-for-6.0-pull-request' into staging
> (2021-03-28 19:49:57 +0100)
>
> are available in the Git repo
* Vitaly Kuznetsov (vkuzn...@redhat.com) wrote:
> Commit 561dbb41b1d7 "i386: Make migration fail when Hyper-V reenlightenment
> was enabled but 'user_tsc_khz' is unset" forbade migrations with when guest
> has opted for reenlightenment notifications but 'tsc-frequency' wasn't set
> explicitly on th
Patchew URL: https://patchew.org/QEMU/20210330143750.3037824-1-ale.q...@rev.ng/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20210330143750.3037824-1-ale.q...@rev.ng
Subject: [PATCH v3 00/12] target/hexagon: introduce
On 3/29/21 5:03 AM, Alex Bennée wrote:
Newer compilers complain about non-matching constraints:
test-i386.c:1393:5: error: asm operand 2 probably doesn’t match constraints
[-Werror]
1393 | asm volatile ("lcall %1, %2"
| ^~~
The problem is that the newer compiler is def
On Tue, Mar 30, 2021 at 7:33 AM Daniel P. Berrangé
wrote:
> The use of submodules has imposed significant pain on QEMU developers over
> the years, and as such I think our general goal should be to have zero git
> submodules over the long term. Usage of submodules ought to be considered
> a short
On 30/03/2021 15.27, Daniel P. Berrangé wrote:
On Tue, Mar 30, 2021 at 03:19:49PM +0200, Paolo Bonzini wrote:
On 30/03/21 15:12, Daniel P. Berrangé wrote:
Now, but that may change already in 6.1 in order to add CFI support.
We can bundle a newer version, but we don't need to require a newer
ve
On Tue, 30 Mar 2021 at 17:00, Warner Losh wrote:
> submodules have caused me significant pain in rebasing the bsd-user work.
> The way QEMU does things, you wind up with unclean trees after a build,
> which causes grief at times... I for one, would shed no tears at the number of
> submodules dropp
On Fri, Mar 26, 2021 at 2:22 AM Bin Meng wrote:
>
> As of today, the QEMU Windows installer does not include the
> following two RISC-V BIOS images:
>
> - opensbi-riscv64-generic-fw_dynamic.elf
> - opensbi-riscv32-generic-fw_dynamic.elf
>
> Update the installer script to include them.
>
> Signed-o
On Tue, Mar 30, 2021 at 10:11 AM Peter Maydell
wrote:
> On Tue, 30 Mar 2021 at 17:00, Warner Losh wrote:
> > submodules have caused me significant pain in rebasing the bsd-user work.
> > The way QEMU does things, you wind up with unclean trees after a build,
> > which causes grief at times... I
On Sun, Mar 28, 2021 at 11:48 PM Dylan Jhong wrote:
>
> Use target_ulong to instead of uint64_t on reset vector address
> to adapt on both 32/64 machine.
>
> Signed-off-by: Dylan Jhong
> Signed-off-by: Ruinland ChuanTzu Tsai
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/cpu.c
On 3/29/21 6:14 AM, FelixCuioc wrote:
Flatview_simplify() can merge many small memory ranges
into a large one and contains EHCI dma buffers.
For example,the merged range maybe0xc-0xbfff.
When seabios write PAM register to change the properties
of part of the merged range from RW to readon
On 30.03.21 15:25, Vladimir Sementsov-Ogievskiy wrote:
30.03.2021 15:51, Max Reitz wrote:
On 30.03.21 12:51, Vladimir Sementsov-Ogievskiy wrote:
30.03.2021 12:49, Max Reitz wrote:
On 25.03.21 20:12, Vladimir Sementsov-Ogievskiy wrote:
ping. Do we want it for 6.0?
I’d rather wait. I think t
On 30/03/21 18:33, Richard Henderson wrote:
Flatview_simplify() can merge many small memory ranges
into a large one and contains EHCI dma buffers.
For example,the merged range maybe0xc-0xbfff.
When seabios write PAM register to change the properties
of part of the merged range from RW t
29.03.2021 16:26, Max Reitz wrote:
169 and 199 have been renamed and moved to tests/ (commit a44be0334be:
"iotests: rename and move 169 and 199 tests"), so we can drop them from
the skip list.
Signed-off-by: Max Reitz
Reviewed-by: Vladimir Sementsov-Ogievskiy
--
Best regards,
Vladimir
On Tue, 23 Mar 2021 16:51:29 +0100
Philippe Mathieu-Daudé wrote:
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> Cc: Cornelia Huck
> Cc: Thomas Huth
> Cc: qemu-s3...@nongnu.org
> ---
> meson.build | 2 ++
> pc-bios/meson.build | 9 +++--
> 2 files changed, 9 insertions(+), 2 delet
29.03.2021 16:26, Max Reitz wrote:
pylint complains that discards1_sha256 and all_discards_sha256 are first
set in non-__init__ methods. Let's make it happy.
Signed-off-by: Max Reitz
---
tests/qemu-iotests/tests/migrate-bitmaps-postcopy-test | 3 +++
1 file changed, 3 insertions(+)
diff --
On Tue, 30 Mar 2021 15:23:50 +0530
Ravi Bangoria wrote:
> As per the PAPR, bit 0 of byte 64 in pa-features property indicates
> availability of 2nd DAWR registers. i.e. If this bit is set, 2nd
> DAWR is present, otherwise not. Use KVM_CAP_PPC_DAWR1 capability to
> find whether kvm supports 2nd DA
On Thu, Mar 25, 2021 at 12:29:39PM +0100, Paolo Bonzini wrote:
> An invariant of the current rwlock is that if multiple coroutines hold a
> reader lock, all must be runnable. The unlock implementation relies on
> this, choosing to wake a single coroutine when the final read lock
> holder exits the
29.03.2021 16:26, Max Reitz wrote:
There are a couple of things pylint takes issue with:
- The "time" import is unused
- The import order (iotests should come last)
- get_bitmap_hash() doesn't use @self and so should be a function
- Semicolons at the end of some lines
Wow that's funny :) My old
29.03.2021 16:26, Max Reitz wrote:
297 so far does not check the named tests, which reside in the tests/
directory (i.e. full path tests/qemu-iotests/tests). Fix it.
Thanks to the previous two commits, all named tests pass its scrutiny,
so we do not have to add anything to SKIP_FILES.
Signed-o
Thanks for looking into this patch Greg. My responses below inline.
Greg Kurz writes:
> Hi Vaibhav,
>
> Great to see you around :-)
:-)
>
> On Mon, 29 Mar 2021 21:52:59 +0530
> Vaibhav Jain wrote:
>
>> Add support for H_SCM_HEALTH hcall described at [1] for spapr
>> nvdimms. This enables g
>
> are available in the Git repository at:
>
> https://git.linaro.org/people/pmaydell/qemu-arm.git pull-target-arm-20210330
>
> for you to fetch changes up to b9e3f1579a4b06fc63dfa8cdb68df1c58eeb0cf1:
>
> hw/timer/renesas_tmr: Add default-case
On 30.03.21 18:47, Vladimir Sementsov-Ogievskiy wrote:
29.03.2021 16:26, Max Reitz wrote:
pylint complains that discards1_sha256 and all_discards_sha256 are first
set in non-__init__ methods. Let's make it happy.
Signed-off-by: Max Reitz
---
tests/qemu-iotests/tests/migrate-bitmaps-postcopy
Signed-off-by: John Snow
---
scripts/qapi/error.py | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/scripts/qapi/error.py b/scripts/qapi/error.py
index 126dda7c9b..38bd7c4dd6 100644
--- a/scripts/qapi/error.py
+++ b/scripts/qapi/error.py
@@ -19,7 +19,7 @@ class QAPIError(Except
No functional change.
Signed-off-by: John Snow
---
scripts/qapi/error.py | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/scripts/qapi/error.py b/scripts/qapi/error.py
index 2183b8c6b7..6ba54821c9 100644
--- a/scripts/qapi/error.py
+++ b/scripts/qapi/error.py
@@ -1
Signed-off-by: John Snow
---
scripts/qapi/pylintrc | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/scripts/qapi/pylintrc b/scripts/qapi/pylintrc
index fb0386d529..88efbf71cb 100644
--- a/scripts/qapi/pylintrc
+++ b/scripts/qapi/pylintrc
@@ -2,8 +2,7 @@
# Add files or dire
Rename QAPIError to QAPISourceError, and then create a new QAPIError
class that serves as the basis for all of our other custom exceptions.
Add docstrings to explain the intended function of each error class.
Signed-off-by: John Snow
---
docs/sphinx/qapidoc.py | 3 ++-
scripts/qapi/error.py |
Eventually, we'll be able to prove that 'info.line' must be an int and
is never None at static analysis time, and this assert can go
away. Until then, it's a type error to assume that self.info is not
None.
Signed-off-by: John Snow
---
scripts/qapi/error.py | 1 +
1 file changed, 1 insertion(+)
Hi, this series adds static type hints to the QAPI module.
This is part four, and focuses on error.py.
Part 4: https://gitlab.com/jsnow/qemu/-/tree/python-qapi-cleanup-pt4
Requirements:
- Python 3.6+
- mypy >= 0.770
- pylint >= 2.6.0 (2.7.0+ when using Python 3.9+)
Every commit should pass with:
if its length is 0 (202=
> 1-03-29 21:56:18 +0200)
>
> ----
> linux-user Pull request 20210330
>
> Fix NETLINK_LIST_MEMBERSHIPS with NULL/invalid pointer and 0 length
>
>
>
Signed-off-by: John Snow
---
(This can be squashed with the previous commit when staged.)
Signed-off-by: John Snow
---
scripts/qapi/mypy.ini | 5 -
1 file changed, 5 deletions(-)
diff --git a/scripts/qapi/mypy.ini b/scripts/qapi/mypy.ini
index 7797c83432..54ca4483d6 100644
--- a/scripts/
It's already treated as optional, with some callers and subclasses
passing 'None'. Make it officially optional, which requires moving the
position of the argument to come after all required parameters.
QAPISemError becomes functionally identical to QAPISourceError. Keep the
name to preserve its se
Keeping it in error.py will create some cyclic import problems when we
add types to the QAPISchemaParser. Callers don't need to know the
details of QAPIParseError unless they are parsing or dealing directly
with the parser, so this won't create any harsh new requirements for
callers in the general
30.03.2021 20:18, Max Reitz wrote:
On 30.03.21 18:47, Vladimir Sementsov-Ogievskiy wrote:
29.03.2021 16:26, Max Reitz wrote:
pylint complains that discards1_sha256 and all_discards_sha256 are first
set in non-__init__ methods. Let's make it happy.
Signed-off-by: Max Reitz
---
tests/qemu-io
On Thu, Mar 25, 2021 at 12:29:35PM +0100, Paolo Bonzini wrote:
> This is a resubmit of David Edmondson's series at
> https://patchew.org/QEMU/20210309144015.557477-1-david.edmond...@oracle.com/.
> After closer analysis on IRC, the CoRwlock's attempt to ensure
> fairness turned out to be flawed. Th
Always pass the id to chardev_new, since it is needed to register
the yank instance for the chardev. Also, after checking that
nothing calls chardev_new with id=NULL, assert() that id!=NULL.
This fixes a crash when using chardev-change to change a chardev
to chardev-socket, which attempts to regis
On Mar 22 01:24, Joelle van Dyne wrote:
> The check for `n->namespace.blkconf.blk` always fails because
> this is in the initialization function.
>
> Signed-off-by: Joelle van Dyne
> ---
> hw/block/nvme.c | 8 +++-
> 1 file changed, 3 insertions(+), 5 deletions(-)
>
> diff --git a/hw/block/
Hello Everyone,
These patches increase test coverage for yank, add tests and fix bugs and
crashes in yank in combination with chardev-change.
Please Review.
Regards,
Lukas Straub
Changes:
-v8:
-test: use custom thread to accept() instead of qio_net_listener
-v7:
-test: fix patchew error by not
Move object_property_try_add_child out of chardev_new into it's
callers. This is a preparation for the next patches to fix yank
with the chardev-change case.
Signed-off-by: Lukas Straub
Reviewed-by: Marc-André Lureau
Tested-by: Li Zhang
---
chardev/char.c | 42 -
When changing from chardev-socket (which supports yank) to
chardev-socket again, it fails, because the new chardev attempts
to register a new yank instance. This in turn fails, as there
still is the yank instance from the current chardev. Also,
the old chardev shouldn't unregister the yank instance
Add tests for yank with the chardev-change case.
Signed-off-by: Lukas Straub
Reviewed-by: Marc-André Lureau
Tested-by: Li Zhang
---
MAINTAINERS| 1 +
tests/unit/meson.build | 3 +-
tests/unit/test-yank.c | 249 +
3 files changed, 252 inse
Hmm actually the fedora-i386-cross image is:
gcc (GCC) 10.2.1 20201125 (Red Hat 10.2.1-9)
with CROSS_CC_GUEST_CFLAGS=-m32 so I wonder what the difference is
between that and:
i686-linux-gnu-gcc -m32
i686-linux-gnu-gcc --version
i686-linux-gnu-gcc (Ubuntu 9.3.0-17ubuntu1~20.04) 9.3.0
Copyrig
On Sun, Mar 28, 2021 at 11:39 PM Dylan Jhong wrote:
>
> Use target_ulong to instead of uint64_t on reset vector address
> to adapt on both 32/64 machine.
>
> Signed-off-by: Dylan Jhong
> Signed-off-by: Ruinland ChuanTzu Tsai
Thanks!
Applied to riscv-to-apply.next
Alistair
> ---
> target/ris
30.03.2021 19:39, Max Reitz wrote:
On 30.03.21 15:25, Vladimir Sementsov-Ogievskiy wrote:
30.03.2021 15:51, Max Reitz wrote:
On 30.03.21 12:51, Vladimir Sementsov-Ogievskiy wrote:
30.03.2021 12:49, Max Reitz wrote:
On 25.03.21 20:12, Vladimir Sementsov-Ogievskiy wrote:
ping. Do we want it fo
The problem is that Xfwm's built-in compositor and virgl don't play nice
together.
Work-around: Boot the VM with virgl=off (on the video device) or gl=off
(on the display), run xfwm4-tweaks-settings in the VM, select the
"Compositor" tab, and uncheck "Enable display compositing". Then shut
down t
Public bug reported:
For kernel memory accesses that span across two memory granules, QEMU's
MTE implementation only checks the tag of the first granule but not of
the second one.
To reproduce this, build the Linux kernel with CONFIG_KASAN_HW_TAGS
enabled, apply the patch below, and boot the kern
On 3/29/21 3:04 PM, Peter Maydell wrote:
On Mon, 29 Mar 2021 at 21:07, Derrick McKee wrote:
Hi,
I am running across a scenario where a PAC signed code pointer (using
pacia) sometimes does not successfully authenticate despite the signed
pointer and the salt used to sign the pointer are correc
On 3/29/21 8:59 AM, Alex Bennée wrote:
No changes to the text, just plain rst-ification of the original
source text. Notably:
- fixed up indentation of bullet points
- proper :: escapes for code samples
- added titles to paper links
- moved events into a table
Signed-off-by: Alex Be
On 3/30/21 12:20 PM, Alex Bennée wrote:
Hmm actually the fedora-i386-cross image is:
gcc (GCC) 10.2.1 20201125 (Red Hat 10.2.1-9)
with CROSS_CC_GUEST_CFLAGS=-m32 so I wonder what the difference is
between that and:
i686-linux-gnu-gcc -m32
i686-linux-gnu-gcc --version
i686-linux-gnu-gcc
On 3/30/21 1:30 AM, Max Filippov wrote:
import_core.sh was not updated to change meson.build when new xtensa
core is imported. Fix that.
Cc: qemu-sta...@nongnu.org # v5.2.0
Signed-off-by: Max Filippov
---
target/xtensa/import_core.sh | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
On Tue, 30 Mar 2021 at 21:27, Richard Henderson
wrote:
>
> On 3/30/21 12:20 PM, Alex Bennée wrote:
> > Hmm actually the fedora-i386-cross image is:
> >
> >gcc (GCC) 10.2.1 20201125 (Red Hat 10.2.1-9)
> >
> > with CROSS_CC_GUEST_CFLAGS=-m32 so I wonder what the difference is
> > between that an
On 3/30/21 2:46 PM, Peter Maydell wrote:
On Tue, 30 Mar 2021 at 21:27, Richard Henderson
wrote:
On 3/30/21 12:20 PM, Alex Bennée wrote:
Hmm actually the fedora-i386-cross image is:
gcc (GCC) 10.2.1 20201125 (Red Hat 10.2.1-9)
with CROSS_CC_GUEST_CFLAGS=-m32 so I wonder what the differen
[Sorry for the resend; original seems to have been corrupted]
On 11/2/20 12:27 PM, Philippe Mathieu-Daudé wrote:
> The nanoMIPS ISA has been announced in 2018 for various projects:
>
> GCC: https://gcc.gnu.org/legacy-ml/gcc/2018-05/msg00012.html
> Linux: https://lwn.net/Articles/753605/
> QEMU:
On 3/29/21 8:51 PM, Igor Mammedov wrote:
On Tue, 23 Mar 2021 12:03:58 +1100
David Gibson wrote:
On Fri, Mar 19, 2021 at 03:34:52PM -0300, Daniel Henrique Barboza wrote:
Kernel commit 4bce545903fa ("powerpc/topology: Update
topology_core_cpumask") cause a regression in the pseries machine w
Hi Pavel,
Thanks for the patch.
On Mon, Mar 29, 2021 at 10:42:41AM +0300, Pavel Dovgalyuk wrote:
> This patch adds icount handling to mfspr/mtspr instructions
> that may deal with hardware timers.
>
> Signed-off-by: Pavel Dovgalyuk
> ---
> target/openrisc/translate.c | 15 +++
>
ranch
'remotes/pmaydell/tags/pull-target-arm-20210330' into staging (Peter Maydell)
4a0ba67c77: Merge remote-tracking branch
'remotes/maxreitz/tags/pull-block-2021-03-30' into staging (Peter Maydell)
b9e3f1579a: hw/timer/renesas_tmr: Add default-case asserts in read_tcnt()
(Peter Ma
On Tue, Mar 30, 2021 at 1:32 PM Richard Henderson
wrote:
> On 3/30/21 1:30 AM, Max Filippov wrote:
> > -grep -q core-${NAME}.o "$BASE"/Makefile.objs || \
> > -echo "obj-y += core-${NAME}.o" >> "$BASE"/Makefile.objs
> > +grep -q core-${NAME}.c "$BASE"/meson.build || \
> > +echo "xtensa_ss.a
I believe that you're correct, and that I mis-read the MTE
specification.
I believed that exactly one mte tag check was made for any single memory
access. But I missed that unaligned accesses are as-if a sequence of byte
accesses -- in the Arm ARM, see aarch64/functions/memory/Mem[].
I'm still t
The flags that you need to pass to FVP to enable MTE are listed near the
end of the README here:
https://cs.android.com/android/platform/superproject/+/master:device/generic/goldfish/fvpbase/README.md
--
You received this bug notification because you are a member of qemu-
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On Tue, Mar 30, 2021 at 10:37:06PM +0530, Vaibhav Jain wrote:
>
> Thanks for looking into this patch Greg. My responses below inline.
>
>
> Greg Kurz writes:
>
> > Hi Vaibhav,
> >
> > Great to see you around :-)
>
> :-)
>
> >
> > On Mon, 29 Mar 2021 21:52:59 +0530
> > Vaibhav Jain wrote:
>
On Tue, Mar 30, 2021 at 01:28:31AM +0200, Igor Mammedov wrote:
> On Wed, 24 Mar 2021 16:09:59 -0300
> Daniel Henrique Barboza wrote:
>
> > On 3/23/21 10:40 PM, David Gibson wrote:
> > > On Tue, Mar 23, 2021 at 02:10:22PM -0300, Daniel Henrique Barboza wrote:
> > >>
> > >>
> > >> On 3/22/21 10:1
On Mon, Mar 29, 2021 at 07:04:24PM +0530, Ravi Bangoria wrote:
> Hi David,
>
> > > @@ -241,6 +241,31 @@ static void spapr_dt_pa_features(SpaprMachineState
> > > *spapr,
> > > /* 60: NM atomic, 62: RNG */
> > > 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */
> > > };
>
On Tue, Mar 30, 2021 at 03:23:49PM +0530, Ravi Bangoria wrote:
> Power10 is introducing second DAWR. Use real register names (with
> suffix 0) from ISA for current macros and variables used by Qemu.
>
> One exception to this is KVM_REG_PPC_DAWR[X]. This is from kernel
> uapi header and thus not ch
On Tue, Mar 30, 2021 at 06:48:38PM +0200, Greg Kurz wrote:
> On Tue, 30 Mar 2021 15:23:50 +0530
> Ravi Bangoria wrote:
>
> > As per the PAPR, bit 0 of byte 64 in pa-features property indicates
> > availability of 2nd DAWR registers. i.e. If this bit is set, 2nd
> > DAWR is present, otherwise not.
On Mon, Mar 29, 2021 at 02:53:47PM +0530, Shivaprasad G Bhat wrote:
>
> On 3/24/21 8:37 AM, David Gibson wrote:
> > On Tue, Mar 23, 2021 at 09:47:38AM -0400, Shivaprasad G Bhat wrote:
> > > machine vmstate.
> > >
> > > Signed-off-by: Shivaprasad G Bhat
> > An overal question: surely the same issu
On Tue, Mar 30, 2021 at 08:01:13AM -0700, Richard Henderson wrote:
> On 3/29/21 10:54 PM, David Gibson wrote:
> >B) Just the hflags patches from my / Richard's tree
> > https://gitlab.com/dgibson/qemu/-/pipelines/278497244
>
> Look closer at this one -- it's an s390x test that's failing:
On Mon, Mar 29, 2021 at 03:32:37PM -0300, Daniel Henrique Barboza wrote:
>
>
> On 3/29/21 12:32 PM, Cédric Le Goater wrote:
> > On 3/29/21 6:20 AM, David Gibson wrote:
> > > On Thu, Mar 25, 2021 at 09:56:04AM +0100, Cédric Le Goater wrote:
> > > > On 3/25/21 3:10 AM, David Gibson wrote:
> > > > >
On Thu, Mar 25, 2021 at 02:25:33PM +1100, Alexey Kardashevskiy wrote:
>
>
> On 25/03/2021 13:52, David Gibson wrote:
> > On Tue, Mar 23, 2021 at 01:58:30PM +1100, Alexey Kardashevskiy wrote:
> > > The PAPR platform which describes an OS environment that's presented by
> > > a combination of a hyp
hmode32() should return -RISCV_EXCP_ILLEGAL_INST for RV64.
Signed-off-by: Bin Meng
---
target/riscv/csr.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index d2585395bf..2bad396f64 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/c
The following check:
if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
return -RISCV_EXCP_ILLEGAL_INST;
}
is redundant in fflags/frm/fcsr read/write routines, as the check was
already done in fs().
Signed-off-by: Bin Meng
---
target/riscv/csr.c | 24
SLOF instantiates RTAS since
744a928ccee9 ("spapr: Stop providing RTAS blob")
so the max address applies to the FDT only.
This renames the macro and fixes up the comment.
This should not cause any behavioral change.
Signed-off-by: Alexey Kardashevskiy
---
hw/ppc/spapr.c | 8
1 file ch
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