On Wed, Mar 24, 2021 at 2:30 PM Jason Wang wrote:
>
>
> 在 2021/3/23 上午9:56, Cindy Lu 写道:
> > Add configure notifier support in virtio and related driver
> > When peer is vhost vdpa, setup the configure interrupt function
> > vhost_net_start and release the resource when vhost_net_stop
>
>
> So thi
On Wed, Mar 24, 2021 at 2:35 PM Jason Wang wrote:
>
>
> 在 2021/3/23 上午9:56, Cindy Lu 写道:
> > Add call back function for configure interrupt.
> > Set the notifier's fd to the kernel driver when vdpa start.
> > also set -1 while vdpa stop. then the kernel will release
> > the related resource
> >
>
From: Xingang Wang
This helps to find max bus number of a root bus.
Signed-off-by: Xingang Wang
Signed-off-by: Jiahui Cen
---
hw/pci/pci.c | 34 ++
include/hw/pci/pci.h | 1 +
2 files changed, 35 insertions(+)
diff --git a/hw/pci/pci.c b/hw/pci/pci.c
From: Xingang Wang
This add iommu option for pci root bus, including primary bus
and pxb root bus. The option is valid only if there is a virtual
iommu device.
Signed-off-by: Xingang Wang
Signed-off-by: Jiahui Cen
---
hw/arm/virt.c | 25 +
hw/i386
From: Xingang Wang
The pci host iommu property is useful to check whether
the iommu is enabled on the pci root bus.
Signed-off-by: Xingang Wang
Signed-off-by: Jiahui Cen
---
hw/pci/pci.c | 18 +-
hw/pci/pci_host.c | 2 ++
include/hw/pci/pci.h | 1 +
From: Xingang Wang
These patches add support for configure iommu on/off for pci root bus,
including primary bus and pxb root bus. At present, All root bus
will go through iommu when iommu is configured, which is not flexible.
So this add option to enable/disable iommu for primary bus and pxb
roo
From: Xingang Wang
The idmap of smmuv3 and root complex covers the whole RID space for now,
this patch add explicit idmap info according to root bus number range.
This add smmuv3 idmap for certain bus which has enabled the iommu property.
Signed-off-by: Xingang Wang
Signed-off-by: Jiahui Cen
-
From: Xingang Wang
When building amd IVRS table, only devices attached to root bus with
IOMMU flag should be scanned.
Signed-off-by: Xingang Wang
Signed-off-by: Jiahui Cen
---
hw/i386/acpi-build.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/i386/acpi-build.c b/hw/i3
From: Xingang Wang
In DMAR table, the drhd is set to cover all pci devices when intel_iommu
is on. This patch add explicit scope data, including only the pci devices
that go through iommu.
Signed-off-by: Xingang Wang
Signed-off-by: Jiahui Cen
---
hw/i386/acpi-build.c | 68
25.03.2021 00:13, no-re...@patchew.org wrote:
Patchew URL:
https://patchew.org/QEMU/20210324205132.464899-1-vsement...@virtuozzo.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20210324205132.464899-1-vsement...@
On 3/24/21 11:38 PM, Klaus Heinrich Kiwi wrote:
> Complement the Aspeed HACE support with Scatter-Gather hash support for
> sha256 and sha512. Scatter-Gather is only supported on AST2600-series.
>
> Signed-off-by: Klaus Heinrich Kiwi
this looks good. A few extra comments,
> ---
> hw/misc/aspee
25.03.2021 10:42, Vladimir Sementsov-Ogievskiy wrote:
25.03.2021 00:13, no-re...@patchew.org wrote:
Patchew URL:
https://patchew.org/QEMU/20210324205132.464899-1-vsement...@virtuozzo.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type:
On 3/25/21 3:10 AM, David Gibson wrote:
> On Tue, Mar 23, 2021 at 02:21:33PM -0300, Daniel Henrique Barboza wrote:
>>
>>
>> On 3/22/21 10:03 PM, David Gibson wrote:
>>> On Fri, Mar 19, 2021 at 03:34:52PM -0300, Daniel Henrique Barboza wrote:
Kernel commit 4bce545903fa ("powerpc/topology: Updat
Hi Jason,
This was discussed earlier on the previous series of patches.
https://lists.gnu.org/archive/html/qemu-devel/2021-02/msg01829.html
There were strong objections from both Daniel and Michael and I feel
that the series was rejected.
There was Michael's claim:
"We did what this patch is tryin
On 3/25/21 6:43 AM, Thomas Huth wrote:
> On 24/03/2021 22.58, Philippe Mathieu-Daudé wrote:
>> On 3/24/21 7:33 PM, Philippe Mathieu-Daudé wrote:
>>> On 3/24/21 7:01 PM, Philippe Mathieu-Daudé wrote:
Hi,
Peter's current workflow is push to /staging and if his
testing succeeds, he
Hi All,
Please ignore this patch.
There is a compile error while building 32bit qemu.
The error occurs in ./target/riscv/cpu.c:557
"DEFINE_PROP_UINT64("resetvec", RISCVCPU, cfg.resetvec, DEFAULT_RSTVEC)"
It should be written differently according to 32bit or 64bit machine.
I'll send patch
Hi Taylor,
On 3/25/21 3:50 AM, Taylor Simpson wrote:
> Address feedback from Richard Henderson
If you look at the git history, we use the following tags:
- Reported-by: Richard Henderson
- Suggested-by: Richard Henderson
and tools know how to use them:
https://repo.or.cz/git-dm.git/blob/5ccc4d
On 23.03.21 21:49, Peter Xu wrote:
On Fri, Mar 19, 2021 at 11:12:25AM +0100, David Hildenbrand wrote:
Let's pass flags instead of bools to prepare for passing other flags and
update the documentation of qemu_ram_mmap(). Introduce new QEMU_MAP_
flags that abstract the mmap() PROT_ and MAP_ flag h
Signed-off-by: Dylan Jhong
Signed-off-by: Ruinland ChuanTzu Tsai
---
target/riscv/cpu.c | 6 +-
target/riscv/cpu.h | 2 +-
2 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 7d6ed80f6b..8a5f18bcb0 100644
--- a/target/riscv/cpu.c
+++ b
On 3/25/21 10:29 AM, Philippe Mathieu-Daudé wrote:
> On 3/25/21 6:43 AM, Thomas Huth wrote:
>> On 24/03/2021 22.58, Philippe Mathieu-Daudé wrote:
>>> On 3/24/21 7:33 PM, Philippe Mathieu-Daudé wrote:
On 3/24/21 7:01 PM, Philippe Mathieu-Daudé wrote:
> Hi,
>
> Peter's current workfl
On Wed, Mar 24, 2021 at 08:42:27PM +, Peter Maydell wrote:
> On Wed, 24 Mar 2021 at 20:18, Vladimir Sementsov-Ogievskiy
> wrote:
> >
> > 24.03.2021 21:05, Peter Maydell wrote:
> > > On Wed, 24 Mar 2021 at 14:52, Stefan Hajnoczi wrote:
> > >>
> > >> Vladimir Sementsov-Ogievskiy (2):
> > >>
This patch adds a first set of SMMU functional tests using
a Fedora cloud-init image. Given the kernel in use,
range invalidation is not tested yet. However different
guest kernel configurations are tested: standard, strict=0
and passthrough mode.
The patch applies on top of Cleber's series:
PATCH
Add new tests checking the good behavior of the SMMUv3 protecting
2 virtio pci devices (block and net). We check the guest boots and
we are able to install a package. Different guest configs are tested:
standard, passthrough an strict=0. Given the version of the guest
kernel in use (5.3.7 at this m
On 24.03.2021 18:41, Peter Xu wrote:
On Wed, Mar 24, 2021 at 11:09:27AM +0300, Andrey Gruzdev wrote:
I'm also looking into introducing UFFD_FEATURE_WP_UNALLOCATED so as to
wr-protect page holes too for a uffd-wp region when the feature bit is set.
With that feature we should be able to avoid pre
24.03.2021 16:39, Valeriy Vdovin wrote:
Introducing new qapi method 'query-cpu-model-cpuid'. This method can be used to
get virtualized cpu model info generated by QEMU during VM initialization in
the form of cpuid representation.
Diving into more details about virtual cpu generation: QEMU first
On 3/25/21 5:56 AM, Cédric Le Goater wrote:
On 3/25/21 3:10 AM, David Gibson wrote:
On Tue, Mar 23, 2021 at 02:21:33PM -0300, Daniel Henrique Barboza wrote:
On 3/22/21 10:03 PM, David Gibson wrote:
On Fri, Mar 19, 2021 at 03:34:52PM -0300, Daniel Henrique Barboza wrote:
Kernel commit 4bc
25.03.2021 12:56, Stefan Hajnoczi wrote:
On Wed, Mar 24, 2021 at 08:42:27PM +, Peter Maydell wrote:
On Wed, 24 Mar 2021 at 20:18, Vladimir Sementsov-Ogievskiy
wrote:
24.03.2021 21:05, Peter Maydell wrote:
On Wed, 24 Mar 2021 at 14:52, Stefan Hajnoczi wrote:
Vladimir Sementsov-Ogievski
On Thu, Mar 25, 2021 at 5:42 PM Dylan Jhong wrote:
>
> Signed-off-by: Dylan Jhong
> Signed-off-by: Ruinland ChuanTzu Tsai
> ---
> target/riscv/cpu.c | 6 +-
> target/riscv/cpu.h | 2 +-
> 2 files changed, 6 insertions(+), 2 deletions(-)
>
Reviewed-by: Bin Meng
On Wed, 24 Mar 2021 10:17:55 +0100
Paolo Bonzini wrote:
> On 24/03/21 00:35, Philippe Mathieu-Daudé wrote:
> > Hmmm does this assert() matches your comment?
> >
> > -- >8 --
> > diff --git a/hw/core/qdev.c b/hw/core/qdev.c
> > index cefc5eaa0a9..41cbee77d14 100644
> > --- a/hw/core/qdev.c
> > ++
On Thu, 25 Mar 2021 at 09:33, Philippe Mathieu-Daudé wrote:
> v6.0 is at the door and I was wondering what is missing to have the
> CI used as a gate.
It needs to be faster. Mostly I do check the gitlab CI pipeline
status, but in the run-up to getting rc0 out I stopped waiting
for the gitlab CI j
Le 24/03/2021 à 19:51, Andreas Krebbel a écrit :
> When setting up the pointer for the sigreturn stub in the return
> address register (r14) we currently use the host frame address instead
> of the guest frame address.
>
> Note: This only caused problems if Qemu has been built with
> --disable-pie
25.03.2021 13:11, Vladimir Sementsov-Ogievskiy wrote:
24.03.2021 16:39, Valeriy Vdovin wrote:
Introducing new qapi method 'query-cpu-model-cpuid'. This method can be used to
get virtualized cpu model info generated by QEMU during VM initialization in
the form of cpuid representation.
Diving int
On 25/03/21 11:34, Peter Maydell wrote:
It needs to be faster. Mostly I do check the gitlab CI pipeline
status, but in the run-up to getting rc0 out I stopped waiting
for the gitlab CI job to finish, because I was continually finding
that I kicked off a run, my local build-tests would complete wi
On Thu, 25 Mar 2021 at 11:05, Paolo Bonzini wrote:
>
> On 25/03/21 11:34, Peter Maydell wrote:
> > It needs to be faster. Mostly I do check the gitlab CI pipeline
> > status, but in the run-up to getting rc0 out I stopped waiting
> > for the gitlab CI job to finish, because I was continually findi
Am Mon, 22 Mar 2021 18:09:17 -0400
schrieb John Snow :
> My understanding is that XEN has some extra disks that it unplugs when
> it later figures out it doesn't need them. How exactly this works is
> something I've not looked into too closely.
It has no extra disks, why would it?
I assume eac
On Thu, Mar 25, 2021 at 12:05:32PM +0100, Paolo Bonzini wrote:
> On 25/03/21 11:34, Peter Maydell wrote:
> > It needs to be faster. Mostly I do check the gitlab CI pipeline
> > status, but in the run-up to getting rc0 out I stopped waiting
> > for the gitlab CI job to finish, because I was continua
This is a resubmit of David Edmondson's series at
https://patchew.org/QEMU/20210309144015.557477-1-david.edmond...@oracle.com/.
After closer analysis on IRC, the CoRwlock's attempt to ensure
fairness turned out to be flawed. Therefore, this series
reimplements CoRwlock without using a CoQueue. Tr
From: David Edmondson
If a new bitmap entry is allocated, requiring the entire block to be
written, avoiding leaking the buffer allocated for the block should
the write fail.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: David Edmondson
Message-Id: <20210309144015.557477-2-david.edmond...
From: David Edmondson
Test that downgrading an rwlock does not result in a failure to
schedule coroutines queued on the rwlock.
The diagram associated with test_co_rwlock_downgrade() describes the
intended behaviour, but what was observed previously corresponds to:
| c1 | c2 | c3
An invariant of the current rwlock is that if multiple coroutines hold a
reader lock, all must be runnable. The unlock implementation relies on
this, choosing to wake a single coroutine when the final read lock
holder exits the critical section, assuming that it will wake a
coroutine attempting to
From: David Edmondson
Given that the block size is read from the header of the VDI file, a
wide variety of sizes might be seen. Rather than re-using a block
sized memory region when writing the VDI header, allocate an
appropriately sized buffer.
Signed-off-by: David Edmondson
Message-Id: <20210
From: David Edmondson
When taking the slow path for mutex acquisition, set the coroutine
value in the CoWaitRecord in push_waiter(), rather than both there and
in the caller.
Reviewed-by: Paolo Bonzini
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: David Edmondson
Message-Id: <20210309144
Test that rwlock upgrade is fair, and that readers go back to sleep if
a writer is in line.
Signed-off-by: Paolo Bonzini
---
tests/unit/test-coroutine.c | 62 +
1 file changed, 62 insertions(+)
diff --git a/tests/unit/test-coroutine.c b/tests/unit/test-corout
On 3/24/21 11:29 PM, Richard Henderson wrote:
> On 3/23/21 9:46 AM, Claudio Fontana wrote:
>> move exception code out of tcg/
>> as we need part of it for KVM too.
>>
>> put the exception code into separate cpu modules as appropriate,
>> including:
>>
>> cpu-sysemu.c
>> tcg/tcg-cpu.c
>> tcg/sysemu/
This is now merged and while be available in the 6.0 release.
** Changed in: qemu
Status: In Progress => Fix Committed
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https://bugs.launchpad.net/bugs/1915925
Title:
ARM semih
I think this is fixed now - it would be useful if the OP could confirm
with the current state of master.
** Changed in: qemu
Status: In Progress => Fix Committed
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https://bugs.lau
On 3/24/21 12:29 PM, Philippe Mathieu-Daudé wrote:
Since commit 078778c5a55 ("piix4: Add an i8259 Interrupt Controller")
the TYPE_PIIX4_PCI_DEVICE exposes the ISA input IRQs as "isa" alias.
Use this alias to get IRQ for the power management PCI function.
Signed-off-by: Philippe Mathieu-Daudé
--
On 3/24/21 11:54 AM, Philippe Mathieu-Daudé wrote:
Named IRQs are easier to understand in the monitor.
Name the single output interrupt as 'intr'.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/isa/vt82c686.c | 2 +-
hw/mips/fuloong2e.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-
Simplify memory layout when no pflash_cfi02 mapping requested.
For example using the r2d machine:
(qemu) info mtree
address-space: memory
- (prio 0, i/o): system
-00ff (prio 0, i/o): pflash
-0
The ROMD mode isn't related to mapping setup.
Ideally we'd set this mode when the state machine resets,
but for now simply move it to pflash_cfi02_realize() to
not introduce logical change.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/block/pflash_cfi02.c | 2 +-
1 file changed, 1 insertion(+),
When no mapping is requested, it is pointless to create
alias regions.
Only create them when multiple mappings are requested to
simplify the memory layout. The flatview is not changed.
For example using 'qemu-system-sh4 -M r2d -S -monitor stdio',
* before:
(qemu) info mtree
address-space: me
"Dr. David Alan Gilbert" wrote:
> * Thomas Huth (th...@redhat.com) wrote:
>> On 15/03/2021 22.05, Philippe Mathieu-Daudé wrote:
>> > Hi Thomas,
>> >
>> > +Alex
>> >
>> > On 3/15/21 8:07 PM, Thomas Huth wrote:
>> > > The CONFIG_VFIO switch only works in target specific code. Since
>> > > migratio
Haibo Xu wrote:
> MTE spec provide instructions to retrieve the memory tags:
> (1) LDG, at 16 bytes granularity, and available in both user
> and kernel space;
> (2) LDGM, at 256 bytes granularity in maximum, and only
> available in kernel space
>
> To improve the performance, KVM has expo
On 3/24/21 11:54 AM, Philippe Mathieu-Daudé wrote:
Instead of creating an input IRQ with qemu_allocate_irqs()
to pass it as output IRQ of the PIC, with its handler simply
dispatching into the "intr" output IRQ, simplify by directly
connecting the PIC to the "intr" named output.
Fixes: 3dc31cb849
On 3/24/21 11:54 AM, Philippe Mathieu-Daudé wrote:
Signed-off-by: Philippe Mathieu-Daudé
---
hw/ide/via.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
Reviewed-by: Richard Henderson
r~
Viresh Kumar writes:
> On 25-03-21, 13:09, Jie Deng wrote:
>>
>> On 2021/3/24 15:33, Viresh Kumar wrote:
>> > +
>> > +/* Definitions from virtio-i2c specifications */
>> > +#define VHOST_USER_I2C_MAX_QUEUES 1
>> > +
>> > +/* Status */
>> > +#define VIRTIO_I2C_MSG_OK 0
>> >
On 3/24/21 11:54 AM, Philippe Mathieu-Daudé wrote:
The 2 cascaded 8259 PIC are managed by the PCI function #0
(ISA bridge). Expose the 16 IRQs on this function, so other
functions from the same chipset can access them.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/isa/vt82c686.c | 13 ++
On 3/24/21 11:54 AM, Philippe Mathieu-Daudé wrote:
To avoid abusing isa_get_irq(NULL) using a hidden ISA bridge
under the hood, let the IDE function expose 2 output IRQs,
and connect them to the ISA function inputs when creating
the south bridge chipset model in vt82c686b_southbridge_init.
Signe
Hi,
I'm using KVM from command line to run a VM and I have to create a ivshmem
between host and guest. The options that I pass are:
-device ivshmem-plain, memdev=id -object
memory-backend-file,size=1M,share,mem-path=/dev/shm/ivshmem,id=id
Now, from host side I can read and write the shmem. From gue
On 3/24/21 9:15 PM, Robert Hoo wrote:
+} else if (env->xcr0 & XFEATURE_AVX) {
This is normally a 2-bit test.
I beg your pardon. What 2 bits?
I forget the names, but isn't the usual test xcr0 & 6 == 6?
BTW, checkpatch didn't warn me on this. It escaped.:)
Heh.
r~
Haibo Xu wrote:
> Signed-off-by: Haibo Xu
> ---
> hw/arm/virt.c | 22 +++---
> 1 file changed, 19 insertions(+), 3 deletions(-)
>
> diff --git a/hw/arm/virt.c b/hw/arm/virt.c
> index 76658b93a3..36cfdb29e9 100644
> --- a/hw/arm/virt.c
> +++ b/hw/arm/virt.c
> @@ -79,6 +79,7 @@
>
On 3/24/21 12:51 PM, Andreas Krebbel wrote:
When setting up the pointer for the sigreturn stub in the return
address register (r14) we currently use the host frame address instead
of the guest frame address.
Note: This only caused problems if Qemu has been built with
--disable-pie (as it is in d
On 3/25/21 6:09 AM, Philippe Mathieu-Daudé wrote:
The ROMD mode isn't related to mapping setup.
Ideally we'd set this mode when the state machine resets,
but for now simply move it to pflash_cfi02_realize() to
not introduce logical change.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/block/pfl
On 3/25/21 6:09 AM, Philippe Mathieu-Daudé wrote:
When no mapping is requested, it is pointless to create
alias regions.
Only create them when multiple mappings are requested to
simplify the memory layout. The flatview is not changed.
For example using 'qemu-system-sh4 -M r2d -S -monitor stdio',
Hi Cleber,
On 3/24/21 11:23 PM, Cleber Rosa wrote:
> On Wed, Mar 24, 2021 at 10:07:31AM +0100, Auger Eric wrote:
>> Hi Cleber,
>>
>> On 3/23/21 11:15 PM, Cleber Rosa wrote:
>>> Both the virtiofs submounts and the linux ssh mips malta tests
>>> contains useful methods related to ssh that deserve to
On 3/24/21 8:49 PM, Taylor Simpson wrote:
Simplify TCG generation of hex_reg_written
Address feedback from Richard Henderson
Signed-off-by: Taylor Simpson
---
target/hexagon/genptr.c | 12 +---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/target/hexagon/genptr.c b/
On 23/03/2021 22:57, Peter Maydell wrote:
On Tue, 23 Mar 2021 at 21:21, Mark Cave-Ayland
wrote:
I'm not sure what the right solution is here. In my mind there hasn't really
been any
difference between TYPE_DEVICE and TYPE_SYS_BUS_DEVICE other than the APIs that
expose the memory regions and I
On 3/24/21 8:49 PM, Taylor Simpson wrote:
Address feedback from Richard Henderson
Signed-off-by: Taylor Simpson
---
linux-user/hexagon/cpu_loop.c | 2 +-
target/hexagon/cpu.c | 9 -
target/hexagon/cpu.h | 6 ++
target/hexagon/decode.c | 6 +++---
t
On Thu, 25 Mar 2021 at 12:57, Mark Cave-Ayland
wrote:
> Thanks for the analysis: I can certainly see how the above commit would have
> changed
> the behaviour. Looking at hw/ppc/e590plat.c in e500plat_machine_class_init()
> I see
> that line 101 reads "machine_class_allow_dynamic_sysbus_dev(mc,
I think there's still work to do here -- we don't properly tell
semihosting where the memory is on M-profile or in all A-profile cases.
I don't think that "look at the stack pointer" is a very good heuristic.
--
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John Snow writes:
> On 2/25/21 10:28 AM, Markus Armbruster wrote:
>> John Snow writes:
>>
>>> There's not a big obvious difference between the types of checks that
>>> happen in the main function versus the kind that happen in the
>>> functions. Now they're in one place for each of the main typ
If Alex is interested in having a fuzz-proof device as a starting point
for fuzzing QEMU's SCSI layer then I don't mind doing the basic work as
I've spent a few months deep in the internals of the ESP controller, and
it makes sense to look at this whilst it is all still fresh. I'd say
there's at le
S390 PCI currently has no backup, add one. Add an additional backup
for vfio-ccw and refresh the backup for vfio-ap.
Signed-off-by: Matthew Rosato
---
MAINTAINERS | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 554be84..5620fc8 100644
---
On 3/25/21 2:55 PM, Matthew Rosato wrote:
S390 PCI currently has no backup, add one. Add an additional backup
for vfio-ccw and refresh the backup for vfio-ap.
Signed-off-by: Matthew Rosato
---
MAINTAINERS | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/MAINTAINER
On 3/25/21 9:55 AM, Matthew Rosato wrote:
S390 PCI currently has no backup, add one. Add an additional backup
for vfio-ccw and refresh the backup for vfio-ap.
Signed-off-by: Matthew Rosato
Acked-by: Eric Farman
---
MAINTAINERS | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(
The VT8231 south bridge is very similar to VT82C686B but there are
some differences in register addresses and functionality, e.g. the
VT8231 only has one serial port. This commit adds VT8231_SUPERIO
subclass based on the abstract VIA_SUPERIO class to emulate the
superio part of VT8231.
Signed-off-
Add new machine called pegasos2 emulating the Genesi/bPlan Pegasos II,
a PowerPC board based on the Marvell MV64361 system controller and the
VIA VT8231 integrated south bridge/superio chips. It can run Linux,
AmigaOS and a wide range of MorphOS versions. Currently a firmware ROM
image is needed to
The Marvell Discovery II aka. MV64361 is a PowerPC system controller
chip that is used on the pegasos2 PPC board. This adds emulation of it
that models the device enough to boot guests on this board. The
mv643xx.h header with register definitions is taken from Linux 4.15.10
only fixing white space
Add emulation of VT8231 south bridge ISA part based on the similar
VT82C686B but implemented in a separate subclass that holds the
differences while reusing parts that can be shared.
Signed-off-by: BALATON Zoltan
Reviewed-by: Philippe Mathieu-Daudé
---
hw/isa/vt82c686.c | 84 +++
Hello,
This is adding a new PPC board called pegasos2. More info on it can be
found at:
https://osdn.net/projects/qmiga/wiki/SubprojectPegasos2
Currently it needs a firmware ROM image that I cannot include due to
original copyright holder (bPlan) did not release it under a free
licence but I hav
To allow reusing ISA bridge emulation for vt8231_isa move the device
state of vt82c686b_isa emulation in an abstract via_isa class. This
change breaks migration back compatibility but this is not an issue
for Fuloong2E machine which is not versioned or migration supported.
Signed-off-by: BALATON Z
Collect superio functionality and its controlling config registers
handling in an abstract VIA_SUPERIO class that is a subclass of
ISA_SUPERIO and put vt82c686b specific parts in a subclass of this
abstract class.
Signed-off-by: BALATON Zoltan
Reviewed-by: Mark Cave-Ayland
---
hw/isa/vt82c686.c
On Thu, 25 Mar 2021, David Gibson wrote:
On Tue, Mar 23, 2021 at 01:57:25PM +0100, BALATON Zoltan wrote:
On Tue, 23 Mar 2021, David Gibson wrote:
On Wed, Mar 17, 2021 at 02:17:51AM +0100, BALATON Zoltan wrote:
Hello,
This is adding a new PPC board called pegasos2. More info on it can be
found
From: Philippe Mathieu-Daudé
TYPE_VIA_PM calls apm_init() in via_pm_realize(), so
requires APM to be selected.
Reported-by: BALATON Zoltan
Signed-off-by: Philippe Mathieu-Daudé
Signed-off-by: BALATON Zoltan
---
hw/isa/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/isa/Kconfig
John Snow writes:
> mypy does not know the types of values stored in Dicts that masquerade
> as objects. Help the type checker out by constraining the type.
>
> Signed-off-by: John Snow
> ---
> scripts/qapi/expr.py | 26 +++---
> 1 file changed, 23 insertions(+), 3 deletions
On 2021/3/9 18:27, Eric Auger wrote:
If the whole SID range (32b) is invalidated (SMMU_CMD_CFGI_ALL),
@end overflows and we fail to handle the command properly.
Once this gets fixed, the current code really is awkward in the
sense it loops over the whole range instead of removing the
currently c
John Snow writes:
> It needs to be an object (dict), not anything else.
>
> Signed-off-by: John Snow
>
> ---
>
> Note: this actually doesn't ... work, but on-list, we discussed wanting
> tests first, then the fix. That can't happen here, because QAPI crashes
> at runtime. So uh, just squash this
On Thu, 25 Mar 2021 09:55:09 -0400
Matthew Rosato wrote:
> S390 PCI currently has no backup, add one. Add an additional backup
> for vfio-ccw and refresh the backup for vfio-ap.
>
> Signed-off-by: Matthew Rosato
Acked-by: Halil Pasic
Suggest
qapi/expr.py: Check type of union and alternate 'data' member
John Snow writes:
> We don't actually check, so the user can get some unpleasant stacktraces.
Let's point to the new tests here.
> Formalize it.
Huh?
> Signed-off-by: John Snow
> ---
> scripts/qapi/expr.py
On 3/24/21 11:07 PM, Richard Henderson wrote:
> On 3/23/21 9:46 AM, Claudio Fontana wrote:
>> this function is used for kvm too, add it to the
>> cpu-common module.
>>
>> Signed-off-by: Claudio Fontana
>
> Reviewed-by: Richard Henderson
>
>> /* #endif TARGET_AARCH64 , see matching comment abo
They were introduced in commit 9bde7f0674fe ("hw/arm/smmuv3: Implement
translate callback") but never actually used. Drop them.
Signed-off-by: Zenghui Yu
---
hw/arm/smmuv3-internal.h | 7 ---
1 file changed, 7 deletions(-)
diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h
ind
On 3/25/21 1:29 PM, Richard Henderson wrote:
> On 3/24/21 11:54 AM, Philippe Mathieu-Daudé wrote:
>> To avoid abusing isa_get_irq(NULL) using a hidden ISA bridge
>> under the hood, let the IDE function expose 2 output IRQs,
>> and connect them to the ISA function inputs when creating
>> the south b
On 3/24/21 11:17 PM, Richard Henderson wrote:
> On 3/23/21 9:46 AM, Claudio Fontana wrote:
>> -static void arm_cpu_dump_state(CPUState *cs, FILE *f, int flags)
>> -{
>> -ARMCPU *cpu = ARM_CPU(cs);
>> -CPUARMState *env = &cpu->env;
>> -int i;
>> -
>> -if (is_a64(env)) {
>> -a
Hi,
On 3/23/21 7:15 PM, Cleber Rosa wrote:
The LinuxTest specifically targets users that need to interact with Linux
guests. So, it makes sense to give a connection by default, and avoid
requiring it as boiler-plate code.
Signed-off-by: Cleber Rosa
---
tests/acceptance/avocado_qemu/__init__
John Snow writes:
> Casts are instructions to the type checker only, they aren't "safe" and
> should probably be avoided in general. In this case, when we perform
> type checking on a nested structure, the type of each field does not
> "stick".
>
> (See PEP 647 for an example of "type narrowing"
On Thu, Mar 25, 2021 at 10:57:12AM +0100, Eric Auger wrote:
> Add new tests checking the good behavior of the SMMUv3 protecting
> 2 virtio pci devices (block and net). We check the guest boots and
> we are able to install a package. Different guest configs are tested:
> standard, passthrough an str
On 3/24/21 8:49 PM, Taylor Simpson wrote:
When exiting a TB, generate all the code before returning from
hexagon_tr_translate_packet so that nothing needs to be done in
hexagon_tr_tb_stop.
Address feedback from Richard Henderson
Signed-off-by: Taylor Simpson
---
target/hexagon/translate.c |
On 3/24/21 8:49 PM, Taylor Simpson wrote:
Multiple writes to the same preg are and'ed together. Rather than
generating a runtime check, we can determine at TCG generation time
if the predicate has previously been written in the packet.
Test added to tests/tcg/hexagon/misc.c
Address feedback fr
On 3/24/21 8:50 PM, Taylor Simpson wrote:
Address feedback from Richard Henderson
Signed-off-by: Taylor Simpson
---
target/hexagon/cpu_bits.h | 2 +-
target/hexagon/decode.c| 80 +++---
target/hexagon/insn.h | 21 ++--
target/hexago
On 3/24/21 8:50 PM, Taylor Simpson wrote:
Remove unused carry_from_add64 function
Change type of softfloat_roundingmodes
Address feedback from Richard Henderson
Signed-off-by: Taylor Simpson
---
target/hexagon/arch.c | 15 +--
target/hexagon/arch.h | 1 -
target/hexagon/mac
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