The HACE (Hash and Crypto Engine) is a device that offloads MD5, SHA1,
SHA2, RSA and other cryptographic algorithms.
This initial model implements a subset of the device's functionality;
currently only direct access (non-scatter gather) hashing.
Signed-off-by: Joel Stanley
---
v3:
- rebase on u
v4: Rebase on Philippe's memory region cleanup series [1]
Address feedback from Cédric
Rework qtest to run on ast2400, ast2500 and ast2600
v3: Rework qtest to not use libqtest-single.h, rebase to avoid LPC
conflicts.
v2: Address review from Andrew and Philippe. Adds a qtest.
[1] https://lo
This adds a test for the Aspeed Hash and Crypto (HACE) engine. It tests
the currently implemented behavior of the hash functionality.
The tests are similar, but are cut/pasted instead of broken out into a
common function so the assert machinery produces useful output when a
test fails.
Signed-off
Add the hash and crypto engine model to the Aspeed socs.
Reviewed-by: Andrew Jeffery
Signed-off-by: Joel Stanley
---
v3: Rebase on upstream
v4: Update integration for soc-specific hace objects
---
docs/system/arm/aspeed.rst | 2 +-
include/hw/arm/aspeed_soc.h | 3 +++
hw/arm/aspeed_ast2600.c
On 3/24/21 8:09 AM, Joel Stanley wrote:
> This adds a test for the Aspeed Hash and Crypto (HACE) engine. It tests
> the currently implemented behavior of the hash functionality.
>
> The tests are similar, but are cut/pasted instead of broken out into a
> common function so the assert machinery pro
On 11/12/2020 18.11, Markus Armbruster wrote:
qobject_to_json() and qobject_to_json_pretty() build a GString, then
covert it to QString. Just one of the callers actually needs a
QString: qemu_rbd_parse_filename(). A few others need a string they
can modify: qmp_send_response(), qga's send_respo
On Tue, Mar 23, 2021 at 04:10:27PM +, Catangiu, Adrian Costin wrote:
> Hi Greg,
>
> After your previous reply on this thread we started considering to provide
> this interface and framework/functionality through a userspace service
> instead of a kernel interface.
> The latest iteration on t
On 3/24/21 8:09 AM, Joel Stanley wrote:
> Add the hash and crypto engine model to the Aspeed socs.
>
> Reviewed-by: Andrew Jeffery
> Signed-off-by: Joel Stanley
Reviewed-by: Cédric Le Goater
> ---
> v3: Rebase on upstream
> v4: Update integration for soc-specific hace objects
> ---
> docs/s
On 3/24/21 8:09 AM, Joel Stanley wrote:
> The HACE (Hash and Crypto Engine) is a device that offloads MD5, SHA1,
> SHA2, RSA and other cryptographic algorithms.
>
> This initial model implements a subset of the device's functionality;
> currently only direct access (non-scatter gather) hashing.
>
Patchew URL: https://patchew.org/QEMU/20210324070955.125941-1-j...@jms.id.au/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20210324070955.125941-1-j...@jms.id.au
Subject: [PATCH v4 0/3] hw/misc: Model ASPEED hash and
Hello,
This is an initial implementation of a generic vhost-user backend for
the I2C bus. This is based of the virtio specifications (already merged)
for the I2C bus.
The kernel virtio I2C driver is still under review, here is the latest
version (v10):
https://lore.kernel.org/lkml/226a8d5663b
This allows is to instantiate a vhost-user-i2c device as part of a PCI
bus. It is mostly boilerplate which looks pretty similar to the
vhost-user-fs-pci device.
Signed-off-by: Viresh Kumar
---
hw/virtio/meson.build | 1 +
hw/virtio/vhost-user-i2c-pci.c | 79
This adds the vhost-user backend driver to support virtio based I2C
devices.
vhost-user-i2c --help
Signed-off-by: Viresh Kumar
---
hw/virtio/vhost-user-i2c.c | 2 +-
tools/meson.build| 8 +
tools/vhost-user-i2c/50-qemu-i2c.json.in | 5 +
tools/vhost-u
This patch adds entry for virtio-i2c related files in MAINTAINERS.
Signed-off-by: Viresh Kumar
---
MAINTAINERS | 9 +
1 file changed, 9 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 9147e9a429a0..3a80352fc85b 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1967,6 +1967,15 @@
This creates the QEMU side of the vhost-user-i2c device which connects
to the remote daemon. It is based of vhost-user-fs code.
Signed-off-by: Viresh Kumar
---
hw/virtio/Kconfig | 5 +
hw/virtio/meson.build | 1 +
hw/virtio/vhost-user-i2c.c
24.03.2021 00:22, Paolo Bonzini wrote:
On 23/03/21 20:17, Vladimir Sementsov-Ogievskiy wrote:
+ unittest.main(argv=argv,
+ testRunner=ReproducibleTestRunner,
+ verbosity=2 if debug else 1,
+ warnings=None if sys.warnoptions else 'ignore')
24.03.2021 00:20, Paolo Bonzini wrote:
On 23/03/21 20:12, Vladimir Sementsov-Ogievskiy wrote:
Move the trailing empty line to print_env(), since it always looks better
and one caller was not adding it.
Seems you've moved this fix from one unrelated commit to another.. And it
touches two ext
Basic usage and example invocation.
Signed-off-by: Viresh Kumar
---
docs/tools/index.rst | 1 +
docs/tools/vhost-user-i2c.rst | 75 +++
2 files changed, 76 insertions(+)
create mode 100644 docs/tools/vhost-user-i2c.rst
diff --git a/docs/tools/index.rst
On Wednesday, 17 March, 2021, 10:26:36 pm IST, Cheolwoo Myung
wrote:
> Hello PJP, Mauro
>
> Of course. you can post the details with our reproducers.
> I'm glad it helped you.
>
> Thank you.
> - Cheolwoo Myung
>
2021년 3월 17일 (수) 오후 10:30, P J P 님이 작성:
>
>On Monday, 15 March, 2021, 07:54:30 p
Patchew URL:
https://patchew.org/QEMU/cover.1616570702.git.viresh.ku...@linaro.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: cover.1616570702.git.viresh.ku...@linaro.org
Subject: [PATCH 0/5] virtio: Implement gen
On 23.03.2021 21:35, Peter Xu wrote:
On Tue, Mar 23, 2021 at 08:21:43PM +0300, Andrey Gruzdev wrote:
For the long term I think we'd better have a helper:
qemu_put_qio_channel_buffer(QEMUFile *file, QIOChannelBuffer *bioc)
So as to hide this flush operation, which is tricky. We'll hav
On Wed, Mar 24, 2021 at 03:30:57PM +1100, Alexey Kardashevskiy wrote:
>
>
> On 22/03/2021 16:44, David Gibson wrote:
> > On Thu, Feb 25, 2021 at 02:23:35PM +1100, Alexey Kardashevskiy wrote:
> > > There is no H_REGISTER_PROCESS_TABLE, it is H_REGISTER_PROC_TBL handler
> > > for which is still cal
Since commit fa4518741e (target-i386: Rename struct XMMReg to ZMMReg),
CPUX86State.xmm_regs[] has already been extended to 512bit to support
AVX512.
Also, other qemu level supports for AVX512 registers are there for
years.
But in x86_cpu_dump_state(), still only dump XMM registers no matter
YMM/ZMM
On Wed, 24 Mar 2021 00:35:05 +0100
Philippe Mathieu-Daudé wrote:
> On 3/24/21 12:00 AM, Greg Kurz wrote:
> > Cc'ing David
> >
> > On Tue, 23 Mar 2021 17:48:36 +0100
> > Thomas Huth wrote:
> >
> >>
> >> In case anyone is interested in fixing those, there are two regressions
> >> with
> >> qem
Thomas Huth writes:
> On 11/12/2020 18.11, Markus Armbruster wrote:
>> qobject_to_json() and qobject_to_json_pretty() build a GString, then
>> covert it to QString. Just one of the callers actually needs a
>> QString: qemu_rbd_parse_filename(). A few others need a string they
>> can modify: qmp
Can you confirm that this is fixed in the v2 of the above patchset?
https://lists.gnu.org/archive/html/qemu-devel/2021-03/msg06550.html
ATB,
Mark.
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/190
On 24.03.2021 01:21, Peter Xu wrote:
On Fri, Mar 19, 2021 at 05:52:46PM +0300, Andrey Gruzdev wrote:
Changes v0->v1:
* Using qemu_real_host_page_size instead of TARGET_PAGE_SIZE for host
page size in ram_block_populate_pages()
* More elegant implementation of ram_block_populate_pages()
On 3/23/21 11:50 PM, Alex Bennée wrote:
>
> Claudio Fontana writes:
>
>> After this patch it is possible to build only kvm:
>>
>> ./configure --disable-tcg --enable-kvm
It's possible to build, but tests will fail until all the test-related patches
are applied.
>
> FWIW at this point we get
Hi
On Wed, Mar 24, 2021 at 2:23 AM Cleber Rosa wrote:
> For users of the LinuxTest class, let's set up the VM with the port
> redirection for SSH, instead of requiring each test to set the same
> arguments.
>
> Signed-off-by: Cleber Rosa
> ---
> tests/acceptance/avocado_qemu/__init__.py | 4 ++
On Wed, Mar 24, 2021 at 2:21 AM Cleber Rosa wrote:
> This makes the username/password used for authentication configurable,
> because some guest operating systems may have restrictions on accounts
> to be used for logins, and it just makes it better documented.
>
> Signed-off-by: Cleber Rosa
>
On Wed, Mar 24, 2021 at 2:34 AM Cleber Rosa wrote:
> The LinuxTest specifically targets users that need to interact with Linux
> guests. So, it makes sense to give a connection by default, and avoid
> requiring it as boiler-plate code.
>
> Signed-off-by: Cleber Rosa
>
Reviewed-by: Marc-André L
On Wed, Mar 24, 2021 at 2:32 AM Cleber Rosa wrote:
> The LinuxTest class' launch_and_wait() method now behaves the same way
> as this test's custom launch_vm(), so let's just use the upper layer
> (common) method.
>
> Signed-off-by: Cleber Rosa
>
Reviewed-by: Marc-André Lureau
> ---
> test
Public bug reported:
When i do memory SRAR test for VM, I meet the following issue:
My VM has 16 vCPU, I will inject one UE error to memory which is accessed by
VM, Then host MCE is raised and SIGBUS is send to VM, and qemu take control.
Qemu will check the broadcast attribute by following
cpu
Output of default values in device help is broken:
$ ./qemu-system-x86_64 -S -display none -monitor stdio
QEMU 5.2.50 monitor - type 'help' for more information
(qemu) device_add pvpanic,help
pvpanic options:
events= - (default: (null))
ioport=- (defau
There is an typo in iotest 051, correct it.
Signed-off-by: Tao Xu
---
tests/qemu-iotests/051| 2 +-
tests/qemu-iotests/051.pc.out | 4 ++--
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/tests/qemu-iotests/051 b/tests/qemu-iotests/051
index f92161d8ef..1595babe82 100755
-
Hi Cleber,
On 3/23/21 11:15 PM, Cleber Rosa wrote:
> If the vmlinuz variable is set to anything that evaluates to True,
> then the respective arguments should be set. If the variable contains
> an empty string, than it will evaluate to False, and the extra
s/than/then
> arguments will not be set.
Hi Cleber,
On 3/23/21 11:15 PM, Cleber Rosa wrote:
> The tag is useful to select tests that depend/use a particular
> feature.
>
> Signed-off-by: Cleber Rosa
> Reviewed-by: Wainer dos Santos Moschetta
> Reviewed-by: Willian Rampazzo
> ---
> tests/acceptance/virtiofs_submounts.py | 1 +
> 1 fi
On Wed, Mar 24, 2021 at 12:41 PM Markus Armbruster
wrote:
> Output of default values in device help is broken:
>
> $ ./qemu-system-x86_64 -S -display none -monitor stdio
> QEMU 5.2.50 monitor - type 'help' for more information
> (qemu) device_add pvpanic,help
> pvpanic options:
>
Hi Cleber,
On 3/23/21 11:15 PM, Cleber Rosa wrote:
> Slightly different versions for the same utility code are currently
> present on different locations. This unifies them all, giving
> preference to the version from virtiofs_submounts.py, because of the
> last tweaks added to it.
>
> While at
On 24/03/2021 09.41, Markus Armbruster wrote:
Output of default values in device help is broken:
$ ./qemu-system-x86_64 -S -display none -monitor stdio
QEMU 5.2.50 monitor - type 'help' for more information
(qemu) device_add pvpanic,help
pvpanic options:
events=
On 24/03/2021 08.21, Cédric Le Goater wrote:
On 3/24/21 8:09 AM, Joel Stanley wrote:
This adds a test for the Aspeed Hash and Crypto (HACE) engine. It tests
the currently implemented behavior of the hash functionality.
The tests are similar, but are cut/pasted instead of broken out into a
commo
Hi Cleber,
On 3/23/21 11:15 PM, Cleber Rosa wrote:
> Both the virtiofs submounts and the linux ssh mips malta tests
> contains useful methods related to ssh that deserve to be made
> available to other tests. Let's move them to the base LinuxTest
nit: strictly speaking they are moved to another c
Hi Cleber,
On 3/23/21 11:15 PM, Cleber Rosa wrote:
> For users of the LinuxTest class, let's set up the VM with the port
> redirection for SSH, instead of requiring each test to set the same
also sets the network device to virtio-net. This may be worth mentioning
here in the commit msg.
> argument
On 24/03/21 00:35, Philippe Mathieu-Daudé wrote:
Hmmm does this assert() matches your comment?
-- >8 --
diff --git a/hw/core/qdev.c b/hw/core/qdev.c
index cefc5eaa0a9..41cbee77d14 100644
--- a/hw/core/qdev.c
+++ b/hw/core/qdev.c
@@ -1130,6 +1130,8 @@ Object *qdev_get_machine(void)
{
stat
On 24.03.21 09:51, Andreas Krebbel wrote:
The sigreturn SVC is put onto the stack by the emulation code. Hence
the address of it should not be subject to guest_base transformation
when fetching it.
The fix applies h2g to the address when writing it into the return
address register to nullify th
On 3/23/21 11:15 PM, Cleber Rosa wrote:
> This makes the username/password used for authentication configurable,
> because some guest operating systems may have restrictions on accounts
> to be used for logins, and it just makes it better documented.
>
> Signed-off-by: Cleber Rosa
Reviewed-by:
Hi Cleber,
On 3/23/21 11:15 PM, Cleber Rosa wrote:
> The LinuxTest specifically targets users that need to interact with Linux
> guests. So, it makes sense to give a connection by default, and avoid
> requiring it as boiler-plate code.
>
> Signed-off-by: Cleber Rosa
> ---
> tests/acceptance/av
Hi,
On 3/23/21 11:15 PM, Cleber Rosa wrote:
> The LinuxTest class' launch_and_wait() method now behaves the same way
> as this test's custom launch_vm(), so let's just use the upper layer
> (common) method.
>
> Signed-off-by: Cleber Rosa
Reviewed-by: Eric Auger
Eric
> ---
> tests/acceptance/v
Hi,
On 3/23/21 11:15 PM, Cleber Rosa wrote:
> Signed-off-by: Cleber Rosa
> Reviewed-by: Marc-André Lureau
> Reviewed-by: Willian Rampazzo
Reviewed-by: Eric Auger
Eric
> ---
> docs/devel/testing.rst | 25 +
> 1 file changed, 25 insertions(+)
>
> diff --git a/docs/deve
Hi Cleber,
On 3/23/21 11:15 PM, Cleber Rosa wrote:
> Even though there are qtest based tests for hotplugging CPUs (from
> which this test took some inspiration from), this one adds checks
> from a Linux guest point of view.
>
> It should also serve as an example for tests that follow a similar
>
v2:
* split the initial patch into two (Raphael)
* rename init to realized (Raphael)
* remove unrelated comment (Raphael)
When the vhost-user-blk device lose the connection to the daemon during
the initialization phase it kills qemu because of the assert in the code.
The series fixes the bug
Commit 4bcad76f4c39 ("vhost-user-blk: delay vhost_user_blk_disconnect")
introduced postponing vhost_dev cleanup aiming to eliminate qemu aborts
because of connection problems with vhost-blk daemon.
However, it introdues a new problem. Now, any communication errors
during execution of vhost_dev_ini
It is useful to use different connect/disconnect event handlers
on device initialization and operation as seen from the further
commit fixing a bug on device initialization.
The patch refactor the code to make use of them: we don't rely any
more on the VM state for choosing how to cleanup the devi
On 3/24/21 8:09 AM, Joel Stanley wrote:
> The HACE (Hash and Crypto Engine) is a device that offloads MD5, SHA1,
> SHA2, RSA and other cryptographic algorithms.
>
> This initial model implements a subset of the device's functionality;
> currently only direct access (non-scatter gather) hashing.
>
On Mon, Mar 22, 2021 at 11:27:17AM +0100, Gerd Hoffmann wrote:
> Hi,
>
> > > +if (vd->msgsize != msg->size + sizeof(*msg)) {
> > > +/* FIXME: handle parse messages splitted into multiple chunks */
> > > +fprintf(stderr, "%s: size mismatch: chunk %d, msg %d (+%zd)\n",
> > > +
On 3/24/21 8:09 AM, Joel Stanley wrote:
> Add the hash and crypto engine model to the Aspeed socs.
>
> Reviewed-by: Andrew Jeffery
> Signed-off-by: Joel Stanley
> ---
> v3: Rebase on upstream
> v4: Update integration for soc-specific hace objects
> ---
> docs/system/arm/aspeed.rst | 2 +-
> i
Hello,
Thank you all for your comments. Both patches (PJP/comment#8 -
Mark/comment#9) seem to properly fix the UAF reported by Alexander in
comment #6. However, I'm still able to reproduce the heap-bof from the
above hw-esp-oob-issues.zip:
./x86_64-softmmu/qemu-system-x86_64 -m 512 \
-drive file=
On 24/03/2021 00.35, Philippe Mathieu-Daudé wrote:
[...]
Hmmm does this assert() matches your comment?
-- >8 --
diff --git a/hw/core/qdev.c b/hw/core/qdev.c
index cefc5eaa0a9..41cbee77d14 100644
--- a/hw/core/qdev.c
+++ b/hw/core/qdev.c
@@ -1130,6 +1130,8 @@ Object *qdev_get_machine(void)
{
I can confirm this is fixed now, thank you Mark.
Patchset v2:
https://lists.gnu.org/archive/html/qemu-devel/2021-03/msg06550.html
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1910723
Title:
NULL
Hi,
> > +if (gd->cbowner[s]) {
> > +/* ignore notifications about our own grabs */
> > +return;
> > +}
> > +
> > +
> > +switch (event->owner_change.reason) {
> > +case GDK_SETTING_ACTION_NEW:
> > +info = qemu_clipboard_info_new(&gd->cbpeer, s);
> > +
Hi
On Wed, Mar 24, 2021 at 2:16 PM Gerd Hoffmann wrote:
> Hi,
>
> > > +if (gd->cbowner[s]) {
> > > +/* ignore notifications about our own grabs */
> > > +return;
> > > +}
> > > +
> > > +
> > > +switch (event->owner_change.reason) {
> > > +case GDK_SETTING_ACTION
Le 24/03/2021 à 10:17, David Hildenbrand a écrit :
> On 24.03.21 09:51, Andreas Krebbel wrote:
>> The sigreturn SVC is put onto the stack by the emulation code. Hence
>> the address of it should not be subject to guest_base transformation
>> when fetching it.
>>
>> The fix applies h2g to the addre
On Wed, Mar 24, 2021 at 1:47 PM Gerd Hoffmann wrote:
> On Mon, Mar 22, 2021 at 11:27:17AM +0100, Gerd Hoffmann wrote:
> > Hi,
> >
> > > > +if (vd->msgsize != msg->size + sizeof(*msg)) {
> > > > +/* FIXME: handle parse messages splitted into multiple
> chunks */
> > > > +fpri
On 24/03/2021 11.10, Thomas Huth wrote:
On 24/03/2021 00.35, Philippe Mathieu-Daudé wrote:
[...]
Hmmm does this assert() matches your comment?
-- >8 --
diff --git a/hw/core/qdev.c b/hw/core/qdev.c
index cefc5eaa0a9..41cbee77d14 100644
--- a/hw/core/qdev.c
+++ b/hw/core/qdev.c
@@ -1130,6 +1130,8
Public bug reported:
Working with Zephyr RTOS, running a multi core sample on mps2_an521 works fine.
Both cpus start.
Trying to debug with options -s -S the second core fails to boot.
Posted with explanation also at:
https://github.com/zephyrproject-rtos/zephyr/issues/33635
** Affects: qemu
Hi Cleber,
On 3/23/21 11:15 PM, Cleber Rosa wrote:
> For users of the LinuxTest class, let's set up the VM with the port
> redirection for SSH, instead of requiring each test to set the same
> arguments.
>
> Signed-off-by: Cleber Rosa
> ---
> tests/acceptance/avocado_qemu/__init__.py | 4 +++-
>
* Zhang Chen (chen.zh...@intel.com) wrote:
> Add hmp_colo_passthrough_add and hmp_colo_passthrough_del make user
> can maintain COLO network passthrough list in human monitor.
>
> Signed-off-by: Zhang Chen
> ---
> hmp-commands.hx | 26 ++
> include/monitor/hmp.h |
** Description changed:
Working with Zephyr RTOS, running a multi core sample on mps2_an521 works
fine. Both cpus start.
Trying to debug with options -s -S the second core fails to boot.
Posted with explanation also at:
https://github.com/zephyrproject-rtos/zephyr/issues/33635
+
+ only af
* Zhang Chen (chen.zh...@intel.com) wrote:
> Make other modules can reuse COLO code.
>
> Signed-off-by: Zhang Chen
> ---
> net/colo-compare.c | 106 -
> net/colo-compare.h | 106 +
> 2 files changed, 106 inse
Update .gitignore to ignore .swp and .patch files.
Signed-off-by: Viresh Kumar
---
.gitignore | 2 ++
1 file changed, 2 insertions(+)
diff --git a/.gitignore b/.gitignore
index 75a4be07240f..eb2553026c5e 100644
--- a/.gitignore
+++ b/.gitignore
@@ -13,3 +13,5 @@ GTAGS
*~
*.ast_raw
*.depend_r
On 24-03-21, 00:42, no-re...@patchew.org wrote:
> Patchew URL:
> https://patchew.org/QEMU/cover.1616570702.git.viresh.ku...@linaro.org/
>
> === TEST SCRIPT BEGIN ===
> #!/bin/bash
> git rev-parse base > /dev/null || exit 0
> git config --local diff.renamelimit 0
> git config --local diff.renames
On Wed, 24 Mar 2021, David Gibson wrote:
On Tue, Mar 23, 2021 at 02:31:07PM +0100, BALATON Zoltan wrote:
On Tue, 23 Mar 2021, David Gibson wrote:
On Wed, Mar 17, 2021 at 02:17:51AM +0100, BALATON Zoltan wrote:
[snip]
+static void setup_mem_windows(MV64361State *s, uint32_t val)
+{
+MV6436
Hi Cédric,
I'm trying to understand the comment you added in commit
3495b6b6101 ("ppc/pnv: add a ISA bus"):
/* let isa_bus_new() create its own bridge on SysBus otherwise
* devices specified on the command line won't find the bus and
* will fail to create.
*/
isa_bus = isa_bus_new(NULL, &
On Tue, 23 Mar 2021 at 15:39, Gerd Hoffmann wrote:
>
> The following changes since commit c95bd5ff1660883d15ad6e0005e4c8571604f51a:
>
> Merge remote-tracking branch 'remotes/philmd/tags/mips-fixes-20210322' into=
> staging (2021-03-22 14:26:13 +)
>
> are available in the Git repository at:
On Wed, 24 Mar 2021, David Gibson wrote:
On Tue, Mar 23, 2021 at 02:01:27PM +0100, BALATON Zoltan wrote:
On Tue, 23 Mar 2021, David Gibson wrote:
On Wed, Mar 17, 2021 at 02:17:51AM +0100, BALATON Zoltan wrote:
Add new machine called pegasos2 emulating the Genesi/bPlan Pegasos II,
a PowerPC boa
On Tue, 23 Mar 2021 19:09:15 +
Daniel P. Berrangé wrote:
> On Tue, Mar 23, 2021 at 06:52:19PM +0100, Lukas Straub wrote:
> > Hello Everyone,
> > These patches remove yank's dependency on qiochannel and always link it in.
> > Please Review.
>
> It would be useful if the cover letter or comm
On Wed, Mar 24, 2021 at 12:22:42PM +0100, Lukas Straub wrote:
> On Tue, 23 Mar 2021 19:09:15 +
> Daniel P. Berrangé wrote:
>
> > On Tue, Mar 23, 2021 at 06:52:19PM +0100, Lukas Straub wrote:
> > > Hello Everyone,
> > > These patches remove yank's dependency on qiochannel and always link it
>
On 3/24/21 12:13 PM, Philippe Mathieu-Daudé wrote:
> Hi Cédric,
>
> I'm trying to understand the comment you added in commit
> 3495b6b6101 ("ppc/pnv: add a ISA bus"):
>
> /* let isa_bus_new() create its own bridge on SysBus otherwise
> * devices specified on the command line won't find the bus
Claudio Fontana writes:
> On 3/23/21 11:50 PM, Alex Bennée wrote:
>>
>> Claudio Fontana writes:
>>
>>> After this patch it is possible to build only kvm:
>>>
>>> ./configure --disable-tcg --enable-kvm
>
>
> It's possible to build, but tests will fail until all the test-related
> patches are
Alex Bennée writes:
> Claudio Fontana writes:
>
>> On 3/23/21 11:50 PM, Alex Bennée wrote:
> Moving up the build chain to the revert I now get:
>
> ./qemu-system-aarch64 -M virt,gic=host -cpu host -accel kvm -m 2048
> -net none -nographic -kernel
> ~/lsrc/linux.git/builds/arm64.virt/arch/ar
On Wed, 24 Mar 2021 11:36:13 +
Daniel P. Berrangé wrote:
> On Wed, Mar 24, 2021 at 12:22:42PM +0100, Lukas Straub wrote:
> > On Tue, 23 Mar 2021 19:09:15 +
> > Daniel P. Berrangé wrote:
> >
> > > On Tue, Mar 23, 2021 at 06:52:19PM +0100, Lukas Straub wrote:
> > > > Hello Everyone,
>
On Thu 18 Mar 2021 03:25:07 PM CET, Vladimir Sementsov-Ogievskiy
wrote:
>> static int bdrv_reopen_prepare(BDRVReopenState *reopen_state,
>> BlockReopenQueue *queue,
>> - Transaction *set_backings_tran, Error
>> **errp);
>> +
This suggests that the rcu_read in iotlb_to_section is not
playing well with one of the g_renew calls in softmmu/physmem.c.
Not sure which, since the sanitizer dump above doesn't trace
back beyond glib itself.
--
You received this bug notification because you are a member of qemu-
devel-ml, whic
On Wed, 24 Mar 2021 10:59:50 +0800
Aili Yao wrote:
> On Wed, 24 Feb 2021 10:39:21 +0800
> Aili Yao wrote:
>
> > On Tue, 23 Feb 2021 16:12:43 +
> > "Luck, Tony" wrote:
> >
> > > > What I think is qemu has not an easy to get the MCE signature from host
> > > > or currently no methods for
On Wed, 24 Feb 2021 10:39:21 +0800
Aili Yao wrote:
> On Tue, 23 Feb 2021 16:12:43 +
> "Luck, Tony" wrote:
>
> > > What I think is qemu has not an easy to get the MCE signature from host
> > > or currently no methods for this
> > > So qemu treat all AR will be No RIPV, Do more is better tha
On 3/24/21 8:39 AM, David Gibson wrote:
On Tue, Mar 23, 2021 at 09:47:55AM -0400, Shivaprasad G Bhat wrote:
The patch adds the 'sync-dax' property to the nvdimm device.
When the sync-dax is 'off', the device tree property
"hcall-flush-required" is added to the nvdimm node which makes the
guest
On 3/24/21 11:28 AM, Laurent Vivier wrote:
> Le 24/03/2021 à 10:17, David Hildenbrand a écrit :
>> On 24.03.21 09:51, Andreas Krebbel wrote:
>>> The sigreturn SVC is put onto the stack by the emulation code. Hence
>>> the address of it should not be subject to guest_base transformation
>>> when fe
Hi:
When i do memory SRAR test for VM, I meet the following issue:
My VM has 16 vCPU, I will inject one UE error to memory which is accessed by VM,
Then host MCE is raised and SIGBUS is send to VM, and qemu take control.
Qemu will check the broadcast attribute by following
cpu_x86_support_mca_br
On 3/24/21 8:37 AM, David Gibson wrote:
On Tue, Mar 23, 2021 at 09:47:38AM -0400, Shivaprasad G Bhat wrote:
The patch adds support for the SCM flush hcall for the nvdimm devices.
To be available for exploitation by guest through the next patch.
The hcall expects the semantics such that the flus
The sigreturn SVC is put onto the stack by the emulation code. Hence
the address of it should not be subject to guest_base transformation
when fetching it.
The fix applies h2g to the address when writing it into the return
address register to nullify the transformation applied to it later.
Note:
On Tue, Mar 23, 2021 at 01:57:05PM +, Stefan Hajnoczi wrote:
> On Fri, Mar 19, 2021 at 03:25:21PM +0200, Mahmoud Mandour wrote:
> > @@ -629,9 +628,6 @@ int fuse_reply_ioctl_retry(fuse_req_t req, const struct
> > iovec *in_iov,
> >
> > res = send_reply_iov(req, 0, iov, count);
> > out:
Hi,
> I fail to see how that works, imagine the other end is the same code (qemu
> in the guest), it will take clipboard ownership and it is in a endless
> loop, isn't it?
Notifications on guest-triggered clipboard updates will not be sent back
to the guest, exactly to avoid that kind of loop.
On Wed, Mar 24, 2021 at 7:12 AM Mahmoud Mandour wrote:
>
> On Tue, Mar 23, 2021 at 4:15 PM Stefan Hajnoczi wrote:
>>
>> On Fri, Mar 19, 2021 at 03:25:27PM +0200, Mahmoud Mandour wrote:
>> > @@ -588,7 +587,7 @@ out:
>> > }
>> >
>> > pthread_mutex_destroy(&req->ch.lock);
>> > -free(fb
Le 24/03/2021 à 12:26, Andreas Krebbel a écrit :
> On 3/24/21 11:28 AM, Laurent Vivier wrote:
>> Le 24/03/2021 à 10:17, David Hildenbrand a écrit :
>>> On 24.03.21 09:51, Andreas Krebbel wrote:
The sigreturn SVC is put onto the stack by the emulation code. Hence
the address of it should
From: Xingang Wang
The idmap of smmuv3 and root complex covers the whole RID space for now,
this patch add explicit idmap info according to root bus number range.
This add smmuv3 idmap for certain bus which has enabled the iommu property.
Signed-off-by: Xingang Wang
Signed-off-by: Jiahui Cen
-
From: Xingang Wang
This helps to find max bus number of a root bus.
Signed-off-by: Xingang Wang
Signed-off-by: Jiahui Cen
---
hw/pci/pci.c | 34 ++
include/hw/pci/pci.h | 1 +
2 files changed, 35 insertions(+)
diff --git a/hw/pci/pci.c b/hw/pci/pci.c
From: Xingang Wang
This add iommu option for pci root bus, including primary bus
and pxb root bus. The option is valid only if there is a virtual
iommu device.
Signed-off-by: Xingang Wang
Signed-off-by: Jiahui Cen
---
hw/arm/virt.c | 25 +
hw/i386
From: Xingang Wang
When building amd IVRS table, only devices attached to root bus with
IOMMU flag should be scanned.
Signed-off-by: Xingang Wang
Signed-off-by: Jiahui Cen
---
hw/i386/acpi-build.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/i386/acpi-build.c b/hw/i3
From: Xingang Wang
The pci host iommu property is useful to check whether
the iommu is enabled on the pci root bus.
Signed-off-by: Xingang Wang
Signed-off-by: Jiahui Cen
---
hw/pci/pci.c | 18 +-
hw/pci/pci_host.c | 2 ++
include/hw/pci/pci.h | 1 +
From: Xingang Wang
In DMAR table, the drhd is set to cover all pci devices when intel_iommu
is on. This patch add explicit scope data, including only the pci devices
that go through iommu.
Signed-off-by: Xingang Wang
Signed-off-by: Jiahui Cen
---
hw/i386/acpi-build.c | 68
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