On 3/9/21 2:41 PM, Claudio Fontana wrote:
> On 2/21/21 11:26 PM, Philippe Mathieu-Daudé wrote:
>> IDAU is specific to M-profile. KVM only supports A-profile.
>> Restrict this interface to TCG, as it is pointless (and
>> confusing) on a KVM-only build.
>>
>> Reviewed-by: Richard Henderson
>> Review
Query the SYS_HEAPINFO semicall and do some basic verification of the
information via libc calls.
Signed-off-by: Alex Bennée
---
.../multiarch/arm-compat-semi/semihosting.c | 35 ++-
1 file changed, 34 insertions(+), 1 deletion(-)
diff --git a/tests/tcg/multiarch/arm-compat-se
As per the spec:
the PARAMETER REGISTER contains the address of a pointer to a
four-field data block.
So we need to follow the pointer and place the results of SYS_HEAPINFO
there.
Bug: https://bugs.launchpad.net/bugs/1915925
Cc: Bug 1915925 <1915...@bugs.launchpad.net>
Cc: Keith Packard
Sig
>From the semihosting point of view what we want to know is the current
mode of the processor. Unify this into a single helper and allow us to
use the same GET/SET_ARG helpers for the rest of the code.
Note: we aren't currently testing riscv32 due to missing toolchain for
check-tcg tests.
Signed-
On 09/03/21 15:14, Philippe Mathieu-Daudé wrote:
SENSE_CODE(LUN_COMM_FAILURE) has an ABORTED COMMAND sense key,
so it results in a retry in Linux. To ensure that EREMOTEIO
is forwarded to the guest, use a HARDWARE ERROR sense key
instead. Note that the code before commit d7a84021d was incorrect
On Mon, Feb 15, 2021 at 11:37 AM vincent Dupaquis
wrote:
>
> Hello,
>
> I am using qemu-system-arm with a netduino2 target, supposingly
> integrating a STM32F2xx chip.
>
> I tested using the STM HAL in order to make a simple program run,
> and I just failed to have it running correctly
On 3/8/21 4:11 AM, Mark Cave-Ayland wrote:
Move the feature comment from after the feature name to the preceding line to
allow for longer feature names and descriptions without hitting the 80
character line limit.
Signed-off-by: Mark Cave-Ayland
---
Reviewed-by: Richard Henderson
r~
On 3/8/21 3:57 AM, Philippe Mathieu-Daudé wrote:
On 3/8/21 11:48 AM, Philippe Mathieu-Daudé wrote:
On 2/15/21 5:26 PM, Richard Henderson wrote:
On 2/14/21 9:58 AM, Philippe Mathieu-Daudé wrote:
+if (a->rt == 0) {
+tcg_gen_movi_i64(cpu_gpr[a->rd], 0);
+tcg_gen_movi_i64(cpu_g
On 3/8/21 4:11 AM, Mark Cave-Ayland wrote:
According to the M68040UM Appendix D the requirement for data accesses to be
word aligned is only for the 68000, 68008 and 68010 CPUs. Later CPUs from the
68020 onwards will allow unaligned data accesses but at the cost of being less
efficient.
Add a ne
Here a new version of the series that enables kvm-only builds.
The goal here is to enable the KVM-only build.
The split of additional kvm code to kvm/ is planned for the next series,
along with the splitting of the accelerator-specific extensions to the
cpu class, once all tests are ok.
The rebas
Signed-off-by: Claudio Fontana
Reviewed-by: Richard Henderson
---
target/arm/{ => tcg}/translate-a64.h | 0
target/arm/{ => tcg}/translate.h | 0
target/arm/{ => tcg}/a32-uncond.decode| 0
target/arm/{ => tcg}/a32.decode | 0
target/arm/{ => tcg}/m-nocp.decode
Signed-off-by: Claudio Fontana
Reviewed-by: Richard Henderson
---
target/arm/tcg/meson.build | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/target/arm/tcg/meson.build b/target/arm/tcg/meson.build
index 0bd4e9d954..3b4146d079 100644
--- a/target/arm/tcg/meson.build
+++
cpu-vfp.c: vfp_get_fpsr and vfp_set_fpsr are needed also for KVM,
so create a new cpu-vfp.c
tcg/cpu-vfp.c: vfp_get_fpscr_from_host and vv are TCG-only, so we
move the implementation to tcg/cpu-vfp.c
kvm/helper-stubs.c: vfp_get_fpscr_from_host and vv stubs for KVM.
Signe
Signed-off-by: Claudio Fontana
---
target/arm/tcg/meson.build| 3 +++
target/arm/tcg/sysemu/meson.build | 3 +++
target/arm/tcg/user/meson.build | 3 +++
3 files changed, 9 insertions(+)
create mode 100644 target/arm/tcg/sysemu/meson.build
create mode 100644 target/arm/tcg/user/meson.
Signed-off-by: Claudio Fontana
Reviewed-by: Richard Henderson
[claudio: moved vec_internal.h and op_addsub.h to tcg/ too]
Signed-off-by: Claudio Fontana
---
meson.build | 1 +
target/arm/{ => tcg}/op_addsub.h | 0
target/arm/tcg/trace.h | 1 +
tar
this function is used for kvm too, add it to the
cpu-common module.
Signed-off-by: Claudio Fontana
---
target/arm/cpu-common.c | 11 +++
target/arm/tcg/helper.c | 11 ---
2 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/target/arm/cpu-common.c b/target/arm/cpu-com
Signed-off-by: Claudio Fontana
---
target/arm/cpu-mmu.h| 3 +-
target/arm/cpu-mmu-sysemu.c | 149
2 files changed, 101 insertions(+), 51 deletions(-)
diff --git a/target/arm/cpu-mmu.h b/target/arm/cpu-mmu.h
index fdedc8fb92..01b060613a 100644
--- a/
We do not move psci.c to tcg/ because we expect other
hypervisors to use it (waiting for HVF enablement).
Signed-off-by: Claudio Fontana
Cc: Alexander Graf
---
target/arm/meson.build | 4
1 file changed, 4 insertions(+)
diff --git a/target/arm/meson.build b/target/arm/meson.build
index 01
it is required by arch-dump.c and cpu.c, so apparently
we need this for KVM too
Signed-off-by: Claudio Fontana
---
target/arm/cpu-common.c | 43 +
target/arm/tcg/helper.c | 33 ---
2 files changed, 43 insertions(+), 33 deletions
move work is needed later on to split things into
tcg-specific portions and kvm-specific portions of this
Signed-off-by: Claudio Fontana
---
target/arm/internals.h | 8 ++-
target/arm/cpu-sysemu.c | 105
target/arm/cpu.c| 83 --
Signed-off-by: Claudio Fontana
---
target/arm/cpregs.h | 54 ++---
target/arm/cpregs.c | 60 ++
target/arm/tcg/cpregs.c | 253 ++--
3 files changed, 241 insertions(+), 126 deletions(-)
diff --git a/target/arm/cpregs.h b/target/arm/cpregs.
Signed-off-by: Claudio Fontana
---
target/arm/cpu-common.c | 41 +
target/arm/tcg/helper.c | 29 -
target/arm/meson.build | 1 +
3 files changed, 42 insertions(+), 29 deletions(-)
create mode 100644 target/arm/cpu-common.c
di
at least the armv7m one should go away with proper
configuration changes (only enabling possible boards for KVM).
Signed-off-by: Claudio Fontana
---
target/arm/kvm/helper-stubs.c | 27 +++
target/arm/kvm/meson.build| 3 +++
target/arm/meson.build| 1 +
3 fil
of note, cpreg lists were previously initialized by TCG first,
and then thrown away and replaced with the data coming from KVM.
Now we just initialize once, either for TCG or for KVM.
Signed-off-by: Claudio Fontana
---
target/arm/cpu.c | 32 ++--
target/arm/kvm.c
this should go away once the configuration and hw/arm is clean
Signed-off-by: Claudio Fontana
---
hw/arm/boot.c | 5 -
target/arm/arm-powerctl.c | 8 +---
target/arm/kvm/helper-stubs.c | 6 ++
3 files changed, 15 insertions(+), 4 deletions(-)
diff --git a/hw/arm/
After this patch it is possible to build only kvm:
./configure --disable-tcg --enable-kvm
Signed-off-by: Claudio Fontana
---
target/arm/cpu-sysemu.c | 12 +++-
1 file changed, 7 insertions(+), 5 deletions(-)
diff --git a/target/arm/cpu-sysemu.c b/target/arm/cpu-sysemu.c
index eb928832a
we need as a result to move switch_mode too,
so we put an implementation into cpu_user and cpu_sysemu.
Signed-off-by: Claudio Fontana
---
target/arm/cpu.h| 2 +
target/arm/cpu-common.c | 192 +++
target/arm/cpu-sysemu.c | 30 ++
target/arm/cpu-user.
just like we have cpu64.c for the 64bit cpu models,
spawn a cpu32.c from cpu.c.
cpu.c will continue to contain the common parts.
Note that we need to build cpu32 also for TARGET_AARCH64,
because qemu-system-aarch64 is supposed to be able to run
non-aarch64 cpus too.
Signed-off-by: Claudio Fontan
Signed-off-by: Claudio Fontana
---
target/arm/cpu-mmu.c| 95 +
target/arm/tcg/helper.c | 95 -
2 files changed, 95 insertions(+), 95 deletions(-)
diff --git a/target/arm/cpu-mmu.c b/target/arm/cpu-mmu.c
index f46
From: Claudio Fontana
and adapt the code including the header references,
and trace-events / trace.h
Signed-off-by: Claudio Fontana
---
meson.build | 2 +-
target/arm/cpu.h | 2 +-
target/arm/{ => kvm}/kvm-consts.h | 0
target/arm/{ => kvm}/kvm_arm.h
Signed-off-by: Claudio Fontana
Reviewed-by: Richard Henderson
---
target/arm/cpu-common.c | 42 +
target/arm/tcg/helper.c | 41
2 files changed, 42 insertions(+), 41 deletions(-)
diff --git a/target/arm/cpu-common.
Signed-off-by: Claudio Fontana
---
target/arm/cpu-sysemu.c | 17 +++--
1 file changed, 11 insertions(+), 6 deletions(-)
diff --git a/target/arm/cpu-sysemu.c b/target/arm/cpu-sysemu.c
index 126263dbf4..eb928832a9 100644
--- a/target/arm/cpu-sysemu.c
+++ b/target/arm/cpu-sysemu.c
@@ -3
on ARM we currently list and build all machines, even when
building KVM-only, without TCG.
Until we fix this (and we only list and build machines that are
compatible with KVM), only test specifically using the "virt"
machine in this case.
Signed-off-by: Claudio Fontana
Cc: Philippe Mathieu-Daudé
we need this for KVM too.
Signed-off-by: Claudio Fontana
---
target/arm/cpu-sysemu.c | 60
target/arm/cpu-user.c | 5
target/arm/tcg/helper.c | 61 -
3 files changed, 65 insertions(+), 61 deletions(-)
diff
From: Claudio Fontana
cpu.c,
cpu32.c,
cpu64.c,
tcg/sysemu/tcg-cpu.c,
all need a good cleanup when it comes to included header files.
Signed-off-by: Claudio Fontana
---
target/arm/cpu.c| 8 ++--
target/arm/cpu32.c | 14 --
target/arm/cpu64.c
and arm_phys_excp_target_el since it is tied up inside the
same #ifdef block.
aarch64_sync_32_to_64 and aarch64_sync_64_to_32 are
mixed in with the TCG helpers, but they shouldn't, as they
are needed for KVM too.
kvm_arch_get_registers()
{
if (!is_a64(env)) {
aarch64_sync_64_to_32(env
The ISD MemoryRegion is implemented for 32-bit accesses.
Simplify it by setting the MemoryRegionOps::impl min/max
access size fields.
Since the region is registered with a size of 0x1000 bytes,
we can remove the hwaddr mask.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/mips/gt64xxx_pci.c | 10 +
to avoid confusion, move the TCG-only 32bit cpu models definitions
inside tcg/tcg-cpu-models.c
The 64bit cpu models (a53/a57/a72/max) remain in cpu64.c .
Signed-off-by: Claudio Fontana
---
target/arm/cpu.h | 1 -
target/arm/internals.h| 5
sve_tests_sve_max_vq_8,
sve_tests_sve_off,
test_query_cpu_model_expansion
all require TCG to run. Skip them for KVM-only builds.
Signed-off-by: Claudio Fontana
---
tests/qtest/arm-cpu-features.c | 16 +++-
1 file changed, 15 insertions(+), 1 deletion(-)
diff --git a/tests/qtest/arm
From: Claudio Fontana
The QEMU PSCI implementation is not used for KVM,
we do not need the kvm constants header.
Signed-off-by: Claudio Fontana
---
target/arm/arm-powerctl.h | 2 --
target/arm/psci.c | 1 -
2 files changed, 3 deletions(-)
diff --git a/target/arm/arm-powerctl.h b/targe
We want to trace all register accesses. First rename the current
gt64120_read / gt64120_write events with '_intreg' suffix, as they
are restricted to interrupt registers.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/mips/gt64xxx_pci.c | 16
hw/mips/trace-events | 4 ++--
2 fil
this change breaks all tests, need to revert for now.
Author: Philippe Mathieu-Daudé
Date: Sun Feb 21 23:26:15 2021 +0100
target/arm: Restrict v8M IDAU to TCG
Signed-off-by: Claudio Fontana
---
target/arm/cpu.c| 7 +++
target/arm/tcg/tcg-cpu-models.c | 8
2 file
test is TCG-only.
Signed-off-by: Claudio Fontana
Cc: Philippe Mathieu-Daudé
---
tests/qtest/bios-tables-test.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c
index e020c83d2a..bd7b85909c 100644
--- a/tests/qtest/bios-ta
There might be more than just KVM and TCG in the future,
so where appropriate, replace broad "else" statements
with the appropriate if (accel_enabled()) check.
Also invert some checks for !kvm_enabled() or !tcg_enabled()
where it seems appropriate to do so.
Note that to make qtest happy we need t
Hi,
On 2021/3/9 5:12, Peter Xu wrote:
On Mon, Mar 08, 2021 at 06:34:58PM +0800, Kunkun Jiang wrote:
Hi,
On 2021/3/5 22:22, Peter Xu wrote:
Kunkun,
On Fri, Mar 05, 2021 at 03:50:34PM +0800, Kunkun Jiang wrote:
When the host page is a huge page and something is sent in the
current iteration,
Skip the test_device_intro_concrete for now for ARM KVM-only build,
as on ARM we currently build devices for ARM that are not
compatible with a KVM-only build.
We can remove this workaround when we fix this in KConfig etc,
and we only list and build machines that are compatible with KVM
for KVM-on
on ARM we currently list and build all machines, even when
building KVM-only, without TCG.
Until we fix this (and we only list and build machines that are
compatible with KVM), only test specifically using the "virt"
machine in this case.
Signed-off-by: Claudio Fontana
Cc: Philippe Mathieu-Daudé
Trivial fixes extracted from another series which became too big,
so I prefer to send them in a previous step.
(This is a resend for Zoltan).
Philippe Mathieu-Daudé (6):
hw/mips/gt64xxx: Initialize ISD I/O memory region in DeviceRealize()
hw/mips/gt64xxx: Simplify ISD MemoryRegion read/write
Fix the following typos:
- GT_PCI1_CFGDATA is not a timer register but a PCI one,
- zero-padding flag is out of the format
Fixes: 641ca2bfcd5 ("hw/mips/gt64xxx_pci: Use qemu_log_mask() instead of debug
printf()")
Signed-off-by: Philippe Mathieu-Daudé
---
hw/mips/gt64xxx_pci.c | 20 ++---
The ISD I/O region belongs to the TYPE_GT64120_PCI_HOST_BRIDGE,
so initialize it before it is realized, not after.
Rename the region as 'gt64120-isd' so it is clearer to realize
it belongs to the GT64120 in the memory tree view.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/mips/gt64xxx_pci.c | 1
On 3/9/21 6:18 AM, Kevin Wolf wrote:
> bdrv_close_all() asserts that no jobs are running any more, so we need
> to cancel all jobs first to avoid failing the assertion.
>
> Fixes: b55a3c8860b763b62b2cc2f4a6f55379977bbde5
> Reported-by: Nini Gu
> Signed-off-by: Kevin Wolf
> ---
> storage-daemon/
Trace all accesses to Internal Space Decode (ISD) registers.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/mips/gt64xxx_pci.c | 2 ++
hw/mips/trace-events | 2 ++
2 files changed, 4 insertions(+)
diff --git a/hw/mips/gt64xxx_pci.c b/hw/mips/gt64xxx_pci.c
index 9a12d00d1e1..43349d6837d 100644
--
Per the comment in the Malta board, the [0x.-0x2000.]
range is decoded by the GT64120, so move the "empty_slot" there.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/mips/gt64xxx_pci.c | 8
hw/mips/malta.c | 7 ---
2 files changed, 8 insertions(+), 7 deletions(-)
di
Given that the block size is read from the header of the VDI file, a
wide variety of sizes might be seen. Rather than re-using a block
sized memory region when writing the VDI header, allocate an
appropriately sized buffer.
Signed-off-by: David Edmondson
---
block/vdi.c | 10 ++
1 file c
First part (TCG, testing postponed) of RFC v1:
https://www.mail-archive.com/qemu-devel@nongnu.org/msg782449.html
3 patches can still be improved for performance, but the improvement
is not yet addressed in this series. Other patches are good enough
for review.
https://gitlab.com/philmd/qemu/-/com
We will use gen_rdhwr() outside of translate.c, make it public.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20210214175912.732946-28-f4...@amsat.org>
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/translate.h | 2 ++
target/mips/translate.c | 2 +-
Hi,
On 2/27/21 9:33 AM, Wang Xingang wrote:
> From: Xingang Wang
>
> These patches add support for configure iommu on/off for pci root bus,
> including primary bus and pxb root bus. At present, All root bus will go
> through iommu when iommu is configured, which is not flexible.
>
> So this add
When taking the slow path for mutex acquisition, set the coroutine
value in the CoWaitRecord in push_waiter(), rather than both there and
in the caller.
Reviewed-by: Paolo Bonzini
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: David Edmondson
---
util/qemu-coroutine-lock.c | 1 -
1 file ch
On Mon, Mar 1, 2021 at 2:34 PM Alexander Bulekov wrote:
>
> This patch switches to use qemu_receive_packet() which can detect
> reentrancy and return early.
>
> Signed-off-by: Alexander Bulekov
Reviewed-by: Alistair Francis
Alistair
> ---
> hw/net/cadence_gem.c | 2 +-
> 1 file changed, 1 in
Move the existing PCPYH opcode (Parallel Copy Halfword) to decodetree.
Remove unnecessary code / comments.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20210214175912.732946-12-f4...@amsat.org>
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/tx79.deco
If a new bitmap entry is allocated, requiring the entire block to be
written, avoiding leaking the buffer allocated for the block should
the write fail.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: David Edmondson
---
block/vdi.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/block/v
Given that we know whether the queued coroutines are reader hopefuls
or writer hopefuls, avoid marking all of the queued coroutines as
runnable when unlocking, choosing instead to wake a single queued
writer or all queued readers.
Suggested-by: Paolo Bonzini
Signed-off-by: David Edmondson
---
u
When trying to remove the -usbdevice option, there were complaints that
"-usbdevice braille" is still a very useful shortcut for some people.
Thus we never remove this option. Since it's not such a big burden to
keep it around, and it's also convenient in the sense that you don't
have to worry to e
Introduce the parallel logic opcodes:
- PAND (Parallel AND)
- POR (Parallel OR)
- PXOR (Parallel XOR)
- PNOR (Parallel NOR)
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20210214175912.732946-16-f4...@amsat.org>
Signed-off-by: Philippe Mathieu-Daudé
---
Stressing the VDI code with qemu-img:
qemu-img convert -p -W -m 16 -O vdi input.qcow2 output.vdi
leads to a hang relatively quickly on a machine with sufficient
CPUs. A similar test targetting either raw or qcow2 formats, or
avoiding out-of-order writes, completes fine.
At the point of the han
Test that downgrading an rwlock does not result in a failure to
schedule coroutines queued on the rwlock.
The diagram associated with test_co_rwlock_downgrade() describes the
intended behaviour, but what is observed currently corresponds to:
| c1 | c2 | c3 | c4 |
|--
On Tue, Mar 9, 2021 at 2:27 AM Alexander Wagner
wrote:
>
>
> On 08.03.21 14:47, Alistair Francis wrote:
> >> hw/char/ibex_uart.c | 20 +++-
> >> include/hw/char/ibex_uart.h | 4
> >> 2 files changed, 19 insertions(+), 5 deletions(-)
> >>
> >> diff --git a/hw/char/
Introduce the 'Parallel Subtract' opcodes:
- PSUBB (Parallel Subtract Byte)
- PSUBH (Parallel Subtract Halfword)
- PSUBW (Parallel Subtract Word)
Signed-off-by: Philippe Mathieu-Daudé
---
v2: Uses tcg_gen_vec_sub{8,16,32}_i64 from tcg/tcg-op-gvec.h (rth)
---
target/mips/tx79.decode | 6
On 09/03/21 15:29, Thomas Huth wrote:
When trying to remove the -usbdevice option, there were complaints that
"-usbdevice braille" is still a very useful shortcut for some people.
Thus we never remove this option. Since it's not such a big burden to
keep it around, and it's also convenient in the
On 3/8/21 2:16 PM, Philippe Mathieu-Daudé wrote:
> Use gen_load_gpr[_hi]() instead of open coding it.
>
> Patch generated using the following spatch script:
>
> @gen_load_gpr@
> identifier reg_idx;
> expression tcg_reg;
> @@
> -if (reg_idx == 0) {
> -tcg_gen_movi_tl(tcg_reg, 0);
>
Introduce the 'Parallel Compare for Greater Than' opcodes:
- PCGTB (Parallel Compare for Greater Than Byte)
- PCGTH (Parallel Compare for Greater Than Halfword)
- PCGTW (Parallel Compare for Greater Than Word)
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20210214175912.732946-21-f4...@a
> On 15 Feb 2021, at 17:09, vincent Dupaquis
> wrote:
>
> ... stuck on the starting HAL_init() call.
HAL requires, amongst other things, the clock registers, since it sets the PLLs
for the desired frequencies.
xPack QEMU Arm [1] implements these registers, and is able to properly run the
On 09/03/2021 15.05, Keqian Zhu wrote:
On 2021/3/9 21:48, Thomas Huth wrote:
On 17/12/2020 02.49, Keqian Zhu wrote:
The parameters start and size are transfered from QEMU memory
emulation layer. It can promise that they are TARGET_PAGE_SIZE
aligned. However, KVM needs they are qemu_real_page_
On 3/9/21 3:18 PM, Philippe Mathieu-Daudé wrote:
> On 3/9/21 2:41 PM, Claudio Fontana wrote:
>> On 2/21/21 11:26 PM, Philippe Mathieu-Daudé wrote:
>>> IDAU is specific to M-profile. KVM only supports A-profile.
>>> Restrict this interface to TCG, as it is pointless (and
>>> confusing) on a KVM-only
Introduce the PEXEH (Parallel Exchange Even Halfword) and PEXEW
(Parallel Exchange Even Word) opcodes.
Signed-off-by: Philippe Mathieu-Daudé
---
v2: unoptimized, see:
https://www.mail-archive.com/qemu-devel@nongnu.org/msg782831.html
---
target/mips/tx79.decode | 2 ++
target/mips/tx79_tran
On Mar 09 10:08, Peter Maydell wrote:
> On Mon, 8 Mar 2021 at 20:14, Aaron Lindsay
> wrote:
> >
> > This allows plugins to query for full virtual-to-physical address
> > translation for a given `qemu_plugin_hwaddr` and stops exposing the
> > offset within the device itself. As this change breaks
Introduce decodetree structure to decode the tx79 opcodes.
Start it by moving the existing MFHI1 and MFLO1 opcodes.
Remove unnecessary comments.
As the TX79 share opcodes with the TX19/TX39/TX49 CPUs,
we introduce the decode_ext_txx9() dispatcher where we
will add the other decoders later.
Signed
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20210214175912.732946-10-f4...@amsat.org>
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/tx79.decode | 3 +++
target/mips/translate.c | 25 -
target/mips/tx79_translate.c
Introduce the LQ opcode (Load Quadword) and remove unreachable code.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20210214175912.732946-26-f4...@amsat.org>
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/tx79.decode | 8
target/mips/tra
A feature of the current rwlock is that if multiple coroutines hold a
reader lock, all must be runnable. The unlock implementation relies on
this, choosing to wake a single coroutine when the final read lock
holder exits the critical section, assuming that it will wake a
coroutine attempting to acq
Move PCPYLD (Parallel Copy Lower Doubleword) and PCPYUD
(Parallel Copy Upper Doubleword) to decodetree. Remove
unnecessary code / comments.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20210214175912.732946-13-f4...@amsat.org>
Signed-off-by: Philippe Mathieu-
Simplify the PCPYH (Parallel Copy Halfword) instruction by using
multiple calls to deposit_i64() which can be optimized by some
TCG backends.
Suggested-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20210214175912.732946-11-f4...@amsat.or
We have almost 400 lines of code full of /* TODO */ comments
which end calling gen_reserved_instruction().
As we are not going to implement them, and all the caller's
switch() default cases already call gen_reserved_instruction(),
we can remove this altogether.
Signed-off-by: Philippe Mathieu-Dau
This comment describing the tx79 opcodes is helpful. As we
will implement these instructions in tx79_translate.c, move
the comment there.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20210214175912.732946-15-f4...@amsat.org>
Signed-off-by: Philippe Mathieu-Da
Introduce the PEXTUW opcode (Parallel Extend Upper from Word).
Signed-off-by: Philippe Mathieu-Daudé
---
v2: Introduce gen_pextw (rth)
---
target/mips/tx79.decode | 4
target/mips/tx79_translate.c | 30 ++
2 files changed, 34 insertions(+)
diff --git a/tar
On 3/8/21 4:11 PM, Rebecca Cran wrote:
ARMv8.4 adds the mandatory FEAT_TLBIRANGE. It provides TLBI
maintenance instructions that apply to a range of input addresses.
Signed-off-by: Rebecca Cran
I realized this only partially addresses the feedback from v1.
Specifically, it still doesn't take
Introduce the 'Parallel Compare for Equal' opcodes:
- PCEQB (Parallel Compare for Equal Byte)
- PCEQH (Parallel Compare for Equal Halfword)
- PCEQW (Parallel Compare for Equal Word)
Signed-off-by: Philippe Mathieu-Daudé
---
v2:
unoptimized, see:
https://www.mail-archive.com/qemu-devel@nongnu.
Introduce the 'Parallel Extend Lower' opcodes:
- PEXTLB (Parallel Extend Upper from Byte)
- PEXTLH (Parallel Extend Upper from Halfword)
- PEXTLW (Parallel Extend Upper from Word)
Signed-off-by: Philippe Mathieu-Daudé
---
v2: Uses gen_pextw, still unoptimized, see:
https://www.mail-archive.co
* Thomas Huth (th...@redhat.com) wrote:
> On 09/03/2021 15.05, Keqian Zhu wrote:
> >
> >
> > On 2021/3/9 21:48, Thomas Huth wrote:
> > > On 17/12/2020 02.49, Keqian Zhu wrote:
> > > > The parameters start and size are transfered from QEMU memory
> > > > emulation layer. It can promise that they a
Introduce the SQ opcode (Store Quadword).
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20210214175912.732946-27-f4...@amsat.org>
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/tx79.decode | 1 +
target/mips/tx79_translate.c | 27 +++
Introduce the PPACW opcode (Parallel Pack to Word).
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20210214175912.732946-22-f4...@amsat.org>
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/tx79.decode | 1 +
target/mips/tx79_translate.c | 30 +
Introduce the PROT3W opcode (Parallel Rotate 3 Words).
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20210214175912.732946-25-f4...@amsat.org>
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/tx79.decode | 1 +
target/mips/tx79_translate.c | 28 ++
Thanks for your bug report. I was just off work, will dig into it tomorrow.
thanks :）
Keqian
On 09/03/2021 15.05, Keqian Zhu wrote:
>
>
> On 2021/3/9 21:48, Thomas Huth wrote:
>> On 17/12/2020 02.49, Keqian Zhu wrote:
>>> The parameters start and size are transfered from QEMU memory
>>> emula
Introduce the PINTEH opcode (Parallel Interleave Even Halfword).
Signed-off-by: Philippe Mathieu-Daudé
---
v2:
Use trans_parallel_arith (rth)
---
target/mips/tx79.decode | 1 +
target/mips/tx79_translate.c | 22 ++
2 files changed, 23 insertions(+)
diff --git a/target/
Now that we have the minimum prerequisites to support the
R5900 CPU, we can reintroduce it.
While we are reverting commit 823f2897bdd ("Disable R5900
support"), we effectively cherry-pick commit ed4f49ba9bb
("target/mips: Define the R5900 CPU").
This reverts commit 823f2897bdd78185f3ba33292a25105
On Mon, Mar 08, 2021 at 07:26:36PM -0800, Joelle van Dyne wrote:
> iOS does not support ucontext natively for aarch64 and the sigaltstack is
> also unsupported (even worse, it fails silently, see:
> https://openradar.appspot.com/13002712 )
>
> As a workaround we include a library implementation of
On Mon, Mar 08, 2021 at 01:31:41PM +0100, Greg Kurz wrote:
> QEMU can stop a virtqueue by sending a VHOST_USER_GET_VRING_BASE request
> to virtiofsd. As with all other vhost-user protocol messages, the thread
> that runs the main event loop in virtiofsd takes the vu_dispatch lock in
> write mode. T
Now than SQ is properly implemented, we can move the RDHWR
kludge required to have usermode working with recent glibc.
Signed-off-by: Philippe Mathieu-Daudé
---
v2: { RDHWR_user } (rth)
---
target/mips/tx79.decode | 5 +++-
target/mips/translate.c | 56
On Mon, Mar 08, 2021 at 01:31:38PM +0100, Greg Kurz wrote:
> A deadlock condition potentially exists if a vhost-user process needs
> to request something to QEMU on the slave channel while processing a
> vhost-user message.
>
> This doesn't seem to affect any vhost-user implementation so far, but
On Mon, Mar 08, 2021 at 01:31:39PM +0100, Greg Kurz wrote:
> +g_autofree int *fd = NULL;
> +size_t fdsize = 0;
> +int i;
>
> /* Read header */
> iov.iov_base = &hdr;
> iov.iov_len = VHOST_USER_HDR_SIZE;
>
> do {
> -size = recvmsg(u->slave_fd, &msgh, 0);
>
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