On 3/1/21 7:13 PM, Stefan Hajnoczi wrote:
> On Mon, Mar 01, 2021 at 12:53:29PM +0100, Philippe Mathieu-Daudé wrote:
>> If the block drive is read-only we will model a "protected" flash
>> device. We can thus use memory_region_init_rom_device_from_file()
>> which mmap the backing file when creating
On 01.03.21 20:59, Vitaly Cheptsov wrote:
> After fixing the _UID value for the primary PCI root bridge in
> af1b80ae it was discovered that this change updates Windows
> configuration in an incompatible way causing network configuration
> failure unless DHCP is used. More details provided on the l
On 02/03/2021 05:54, Jason Wang wrote:
This patch switches to use qemu_receive_packet() which can detect
reentrancy and return early.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Jason Wang
---
hw/net/sungem.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/net
On 01.03.2021 20:16, Arnabjyoti Kalita wrote:
Hello all,
I am really thankful for the wonderful answers in my last post linked below-
https://lists.nongnu.org/archive/html/qemu-discuss/2021-02/msg00131.html
In continuation with the last post, I have a few more questions to ask -
My experiment
On 02/03/2021 14:35, David Gibson wrote:
On Wed, Feb 24, 2021 at 04:41:30PM +1100, Alexey Kardashevskiy wrote:
The PAPR platform which describes an OS environment that's presented by
a combination of a hypervisor and firmware. The features it specifies
require collaboration between the firmwa
Can you give the lspci messages? The below is my output. There is a RAM memory
device.
$ lspci
00:00.0 Host bridge: Intel Corporation 440FX - 82441FX PMC [Natoma] (rev 02)
00:01.0 ISA bridge: Intel Corporation 82371SB PIIX3 ISA [Natoma/Triton II]
00:01.1 IDE interface: Intel Corporation 82371SB
On 3/1/21 10:51 PM, Philippe Mathieu-Daudé wrote:
> Somehow similar to commit 78271684719 ("cpu: tcg_ops: move to
> tcg-cpu-ops.h, keep a pointer in CPUClass"):
>
> We cannot in principle make the SysEmu Operations field definitions
> conditional on CONFIG_SOFTMMU in code that is included by both
Probably I should describe here that after this patch,
configure --enable-tcg --disable-kvm
is now buildable.
Ciao,
Claudio
On 3/1/21 5:49 PM, Claudio Fontana wrote:
> Signed-off-by: Claudio Fontana
> ---
> target/arm/cpu-sysemu.c | 12 +++-
> 1 file changed, 7 insertions(+), 5 delet
On 2/25/21 8:47 PM, BALATON Zoltan wrote:
> Add emulation of VT8231 south bridge ISA part based on the similar
> VT82C686B but implemented in a separate subclass that holds the
> differences while reusing parts that can be shared.
>
> Signed-off-by: BALATON Zoltan
> ---
> hw/isa/vt82c686.c
On 2/25/21 8:47 PM, BALATON Zoltan wrote:
> The VT8231 south bridge is very similar to VT82C686B but there are
> some differences in register addresses and functionality, e.g. the
> VT8231 only has one serial port. This commit adds VT8231_SUPERIO
> subclass based on the abstract VIA_SUPERIO class t
On 3/2/21 4:36 AM, Richard Henderson wrote:
> On 3/1/21 8:49 AM, Claudio Fontana wrote:
>> @@ -1321,6 +1323,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error
>> **errp)
>> }
>> }
>>
>> +#ifdef CONFIG_TCG
>> {
>> uint64_t scale;
>>
>> @@ -1346,7 +1349,
On 2/25/21 8:47 PM, BALATON Zoltan wrote:
> The Marvell Discovery II aka. MV64361 is a PowerPC system controller
> chip that is used on the pegasos2 PPC board. This adds emulation of it
> that models the device enough to boot guests on this board. The
> mv643xx.h header with register definitions is
Hi ChangLimin,
Thanks for your reply. I checked again to find the device... I thought the
name was ivshmem.
I don't find any driver code for IVSHMEM in the linux and qemu repo. Can
you give me some help?
00:10.0 RAM memory: Red Hat, Inc. Inter-VM shared memory (rev 01)
Subsystem: Red Hat, Inc. QE
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