[PATCH v3 44/70] tcg/tci: Split out tcg_out_op_p

Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.c.inc | 18 -- 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 1e3f2c4049..cb0cbbb8da 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.i

[PATCH v3 52/70] tcg/tci: Split out tcg_out_op_rrrr

Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.c.inc | 21 +++-- 1 file changed, 15 insertions(+), 6 deletions(-) diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index f7595fbd65..c2bbd85130 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.

[PATCH v3 43/70] tcg/tci: Split out tcg_out_op_l

Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.c.inc | 14 +++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 707f801099..1e3f2c4049 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @

[PATCH v3 37/70] tcg: Build ffi data structures for helpers

We will shortly use libffi for tci, as that is the only portable way of calling arbitrary functions. Signed-off-by: Richard Henderson --- meson.build| 9 +- include/exec/helper-ffi.h | 115 + include/exec/helper-tcg.h

[PATCH v3 47/70] tcg/tci: Split out tcg_out_op_rrrc

Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.c.inc | 21 +++-- 1 file changed, 15 insertions(+), 6 deletions(-) diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 546424c2bd..5848779208 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.

[PATCH v3 57/70] tcg/tci: Split out tcg_out_op_r[iI]

Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.c.inc | 50 1 file changed, 35 insertions(+), 15 deletions(-) diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index e4a5872b2a..c2d2bd24d7 100644 --- a/tcg/tci/tcg-target.c.inc +++ b

[PATCH v3 56/70] tcg/tci: Split out tcg_out_op_np

Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.c.inc | 18 +- 1 file changed, 13 insertions(+), 5 deletions(-) diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index eeafec6d44..e4a5872b2a 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.i

[PATCH v3 38/70] tcg/tci: Use ffi for calls

This requires adjusting where arguments are stored. Place them on the stack at left-aligned positions. Adjust the stack frame to be at entirely positive offsets. Signed-off-by: Richard Henderson --- include/tcg/tcg.h| 1 + tcg/tci/tcg-target.h | 2 +- tcg/tcg.c|

[PATCH v3 50/70] tcg/tci: Split out tcg_out_op_rrcl

Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.c.inc | 21 +++-- 1 file changed, 15 insertions(+), 6 deletions(-) diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 6c743a8fbd..8cc63124d4 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.

[PATCH v3 61/70] tcg/tci: Change encoding to uint32_t units

This removes all of the problems with unaligned accesses to the bytecode stream. With an 8-bit opcode at the bottom, we have 24 bits remaining, which are generally split into 6 4-bit slots. This fits well with the maximum length opcodes, e.g. INDEX_op_add2_i386, which have 6 register operands. W

[PATCH v3 58/70] tcg/tci: Reserve r13 for a temporary

We're about to adjust the offset range on host memory ops, and the format of branches. Both will require a temporary. Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.h | 1 + tcg/tci/tcg-target.c.inc | 1 + 2 files changed, 2 insertions(+) diff --git a/tcg/tci/tcg-target.h b/tcg/tc

[PATCH v3 41/70] tcg/tci: Push opcode emit into each case

We're about to split out bytecode output into helpers, but we can't do that one at a time if tcg_out_op_t is being done outside of the switch. Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.c.inc | 35 --- 1 file changed, 32 insertions(+), 3 deletions(-)

[PATCH v3 53/70] tcg/tci: Split out tcg_out_op_rrrrcl

Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.c.inc | 27 +++ 1 file changed, 19 insertions(+), 8 deletions(-) diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index c2bbd85130..fb4aacaca3 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-t

[PATCH v3 66/70] tcg/tci: Implement clz, ctz, ctpop

Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.h | 12 +-- tcg/tci.c| 44 tcg/tci/tcg-target.c.inc | 9 3 files changed, 59 insertions(+), 6 deletions(-) diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target

[PATCH v3 59/70] tcg/tci: Emit setcond before brcond

The encoding planned for tci does not have enough room for brcond2, with 4 registers and a condition as input as well as the label. Resolve the condition into TCG_REG_TMP, and relax brcond to one register plus a label, considering the condition to always be reg != 0. Signed-off-by: Richard Hender

[PATCH v3 46/70] tcg/tci: Split out tcg_out_op_rrr

Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.c.inc | 19 ++- 1 file changed, 14 insertions(+), 5 deletions(-) diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 272e3ca70b..546424c2bd 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.

[PATCH v3 54/70] tcg/tci: Split out tcg_out_op_{rrm,rrrm,rrrrm}

Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.c.inc | 70 ++-- 1 file changed, 53 insertions(+), 17 deletions(-) diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index fb4aacaca3..f93772f01f 100644 --- a/tcg/tci/tcg-target.c.inc +++ b

[PATCH v3 67/70] tcg/tci: Implement mulu2, muls2

We already had mulu2_i32 for a 32-bit host; expand this to 64-bit hosts as well. The muls2_i32 and the 64-bit opcodes are new. Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.h | 8 tcg/tci.c| 35 +-- tcg/tci/tcg-target.c.inc

[PATCH v3 60/70] tcg/tci: Remove tci_write_reg

Inline it into its one caller, tci_write_reg64. Drop the asserts that are redundant with tcg_read_r. Signed-off-by: Richard Henderson --- tcg/tci.c | 13 ++--- 1 file changed, 2 insertions(+), 11 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index e7268b13e1..4f81cbb904 100644 --- a/t

[PATCH v3 45/70] tcg/tci: Split out tcg_out_op_rr

At the same time, validate the type argument in tcg_out_mov. Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.c.inc | 36 +++- 1 file changed, 23 insertions(+), 13 deletions(-) diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index cb0cbbb8

[PATCH v3 64/70] tcg/tci: Implement andc, orc, eqv, nand, nor

These were already present in tcg-target.c.inc, but not in the interpreter. Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.h | 20 ++-- tcg/tci.c| 40 2 files changed, 50 insertions(+), 10 deletions(-) diff --git a/tc

[PATCH v3 68/70] tcg/tci: Implement add2, sub2

We already had the 32-bit versions for a 32-bit host; expand this to 64-bit hosts as well. The 64-bit opcodes are new. Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.h | 8 tcg/tci.c| 40 ++-- tcg/tci/tcg-target.c.inc |

[PATCH v3 48/70] tcg/tci: Split out tcg_out_op_rrrrrc

Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.c.inc | 30 +- 1 file changed, 21 insertions(+), 9 deletions(-) diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 5848779208..8eda159dde 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tc

[PATCH v2 13/15] tcg/arm: Implement TCG_TARGET_HAS_shv_vec

The three vector shift by vector operations are all implemented via expansion. Therefore do not actually set TCG_TARGET_HAS_shv_vec, as none of shlv_vec, shrv_vec, sarv_vec may actually appear in the instruction stream, and therefore also do not appear in tcg_target_op_def. Signed-off-by: Richard

[PATCH v3 65/70] tcg/tci: Implement extract, sextract

Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.h | 8 tcg/tci.c| 42 tcg/tci/tcg-target.c.inc | 32 ++ 3 files changed, 78 insertions(+), 4 deletions(-) diff --git a/tcg/tci/tcg-target.h b

[PATCH v3 69/70] tests/tcg: Increase timeout for TCI

The longest test at the moment seems to be a (slower) aarch64 host, for which test-mmap takes 64 seconds. Signed-off-by: Richard Henderson --- configure | 3 +++ tests/tcg/Makefile.target | 6 -- 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/configure b/confi

[PATCH v3 49/70] tcg/tci: Split out tcg_out_op_rrrbb

Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.c.inc | 23 --- 1 file changed, 16 insertions(+), 7 deletions(-) diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 8eda159dde..6c743a8fbd 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-targe

[Bug 1914696] Re: aarch64: migration failed: Segmentation fault (core dumped)

https://patchew.org/QEMU/20210203161340.55210-1-aa...@os.amperecomputing.com/ works for me. -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to the bug report. https://bugs.launchpad.net/bugs/1914696 Title: aarch64: migration failed: Segment

[PATCH v2 01/15] tcg: Change parameters for tcg_target_const_match

Change the return value to bool, because that's what is should have been from the start. Pass the ct mask instead of the whole TCGArgConstraint, as that's the only part that's relevant. Change the value argument to int64_t. We will need the extra width for 32-bit hosts wanting to match vector co

[PATCH v3 70/70] gitlab: Enable cross-i386 builds of TCI

We're currently only testing TCI with a 64-bit host -- also test with a 32-bit host. Enable a selection of softmmu and user-only targets, 32-bit LE, 64-bit LE, 32-bit BE, as there are ifdefs for each. Signed-off-by: Richard Henderson --- .gitlab-ci.d/crossbuilds.yml| 17

[PATCH v2 07/16] tcg/s390x: Implement tcg_out_dup*_vec

Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target.c.inc | 122 - 1 file changed, 119 insertions(+), 3 deletions(-) diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index fdf7475b2d..01118d9993 100644 --- a/tcg/s390x/tcg-target.c.inc

[PATCH v3 51/70] tcg/tci: Split out tcg_out_op_rrrrrr

Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.c.inc | 27 +++ 1 file changed, 19 insertions(+), 8 deletions(-) diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 8cc63124d4..f7595fbd65 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-t

[PATCH v2 03/15] tcg/arm: Implement tcg_out_ld/st for vector types

Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.c.inc | 70 1 file changed, 64 insertions(+), 6 deletions(-) diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index 9bb354abce..ca9a71ca64 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/

[PATCH v2 09/15] tcg/arm: Implement TCG_TARGET_HAS_mul_vec

Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.h | 2 +- tcg/arm/tcg-target.c.inc | 6 ++ 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h index cfbadad72c..94d768f249 100644 --- a/tcg/arm/tcg-target.h +++ b/tcg/arm/tcg-tar

[PATCH v3 55/70] tcg/tci: Split out tcg_out_op_v

Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.c.inc | 14 ++ 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index f93772f01f..eeafec6d44 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @

[PATCH v2 06/16] tcg/s390x: Implement tcg_out_mov for vector types

Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target.c.inc | 72 +++--- 1 file changed, 68 insertions(+), 4 deletions(-) diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index df10ee0feb..fdf7475b2d 100644 --- a/tcg/s390x/tcg-target.c.inc

[PATCH v2 04/15] tcg/arm: Implement tcg_out_mov for vector types

Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.c.inc | 50 +++- 1 file changed, 44 insertions(+), 6 deletions(-) diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index ca9a71ca64..20088ac61a 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/

[PATCH v2 14/15] tcg/arm: Implement TCG_TARGET_HAS_roti_vec

Implement via expansion, so don't actually set TCG_TARGET_HAS_roti_vec. For NEON, this is shift-right followed by shift-left-and-insert. Signed-off-by: Richard Henderson --- tcg/arm/tcg-target-con-set.h | 1 + tcg/arm/tcg-target.opc.h | 1 + tcg/arm/tcg-target.c.inc | 15 ++

[PATCH v3 62/70] tcg/tci: Implement goto_ptr

This operation is critical to staying within the interpretation loop longer, which avoids the overhead of setup and teardown for many TBs. The check in tcg_prologue_init is disabled because TCI does want to use NULL to indicate exit, as opposed to branching to a real epilogue. Signed-off-by: Rich

[PATCH v2 15/16] tcg/s390x: Implement TCG_TARGET_HAS_bitsel_vec

Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target-con-set.h | 1 + tcg/s390x/tcg-target.h | 2 +- tcg/s390x/tcg-target.c.inc | 20 3 files changed, 22 insertions(+), 1 deletion(-) diff --git a/tcg/s390x/tcg-target-con-set.h b/tcg/s390x/tcg-target-con-se

[PATCH v2 03/16] tcg/s390x: Merge TCG_AREG0 and TCG_REG_CALL_STACK into TCGReg

They are rightly values in the same enumeration. Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: David Hildenbrand Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target.h | 28 +++- 1 file changed, 7 insertions(+), 21 deletions(-) diff --git a/tcg/s390x/tcg-target

[PATCH v2 11/15] tcg/arm: Implement TCG_TARGET_HAS_minmax_vec

This is minimum and maximu, signed and unsigned. Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.h | 2 +- tcg/arm/tcg-target.c.inc | 24 2 files changed, 25 insertions(+), 1 deletion(-) diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h index 71621f2

[PATCH v3 63/70] tcg/tci: Implement movcond

When this opcode is not available in the backend, tcg middle-end will expand this as a series of 5 opcodes. So implementing this saves bytecode space. Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.h | 4 ++-- tcg/tci.c| 16 +++- tcg/tci/tcg-target.c.in

[PATCH v2 05/16] tcg/s390x: Implement tcg_out_ld/st for vector types

Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target.c.inc | 117 + 1 file changed, 105 insertions(+), 12 deletions(-) diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index 4656efea83..df10ee0feb 100644 --- a/tcg/s390x/tcg-target.c.in

[PATCH v2 08/16] tcg/s390x: Implement minimal vector operations

Implementing add, sub, and, or, xor as the minimal set. This allows us to actually enable vectors in query_s390_facilities. Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target.c.inc | 154 - 1 file changed, 150 insertions(+), 4 deletions(-) diff --git a

[PATCH v2 00/15] tcg/arm: host neon support

Generate NEON instructions for tcg vector operations. Changes for v2: * Rebase on master, now that all prereq are upstream. r~ Richard Henderson (15): tcg: Change parameters for tcg_target_const_match tcg/arm: Add host vector framework tcg/arm: Implement tcg_out_ld/st for vector types

[RFC PATCH 4/5] Add migration support for KVM guest with MTE

To make it easier to keep the page tags sync with the page data, tags for one page are appended to the data during ram save iteration. This patch only add the pre-copy migration support. Post-copy and compress as well as zero page saving are not supported yet. Signed-off-by: Haibo Xu --- includ

[PATCH v2 00/16] tcg/s390x: host vector support

Changes for v2: * Rebase on master, now that all prereq are upstream. r~ Richard Henderson (16): tcg/s390x: Rename from tcg/s390 tcg/s390x: Change FACILITY representation tcg/s390x: Merge TCG_AREG0 and TCG_REG_CALL_STACK into TCGReg tcg/s390x: Add host vector framework tcg/s390x: Im

[PATCH v2 12/16] tcg/s390x: Implement TCG_TARGET_HAS_minmax_vec

Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target.h | 2 +- tcg/s390x/tcg-target.c.inc | 25 + 2 files changed, 26 insertions(+), 1 deletion(-) diff --git a/tcg/s390x/tcg-target.h b/tcg/s390x/tcg-target.h index 3026a4d8c4..efa32f348c 100644 --- a/tcg/s390x/tc

[PATCH v2 02/15] tcg/arm: Add host vector framework

Add registers and function stubs. The functionality is disabled via use_neon_instructions defined to 0. We must still include results for the mandatory opcodes in tcg_target_op_def, as all opcodes are checked during tcg init. Signed-off-by: Richard Henderson --- tcg/arm/tcg-target-con-set.h |

[PATCH v2 16/16] tcg/s390x: Implement TCG_TARGET_HAS_cmpsel_vec

This is via expansion; don't actually set TCG_TARGET_HAS_cmpsel_vec. Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target.c.inc | 24 +++- 1 file changed, 23 insertions(+), 1 deletion(-) diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index 3c86b233

[PATCH v2 13/16] tcg: Expand usadd/ussub with umin/umax

For usadd, we only have to consider overflow. Since ~B + B == -1, the maximum value for A that saturates is ~B. For ussub, we only have to consider underflow. The minimum value that saturates to 0 from A - B is B. Signed-off-by: Richard Henderson --- tcg/tcg-op-vec.c | 37

[PATCH v2 05/15] tcg/arm: Implement tcg_out_dup*_vec

Most of dupi is copied from tcg/aarch64, which has the same encoding for AdvSimdExpandImm. Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.c.inc | 283 +-- 1 file changed, 275 insertions(+), 8 deletions(-) diff --git a/tcg/arm/tcg-target.c.inc b/tcg/a

Re: [PATCH] vhost: Unbreak SMMU and virtio-iommu on dev-iotlb support

On 2021/2/5 下午11:31, Peter Xu wrote: On Fri, Feb 05, 2021 at 09:33:29AM +0100, Auger Eric wrote: Hi, On 2/5/21 4:16 AM, Jason Wang wrote: On 2021/2/5 上午3:12, Peter Xu wrote: Previous work on dev-iotlb message broke vhost on either SMMU Have a quick git grep and it looks to me v3 support A

[RFC PATCH 0/5] target/arm: Add MTE support to KVM guest

This series add support for MTE(Memory Tagging Extension)[1] in KVM guest. It's based on Steven Price's kernel KVM patches V7[2], and has been tested to ensure that test case[3] can be passed in a KVM guest. Basic pre-copy migration test also passed between two MTE enabled kvm guest. This is a RF

[PATCH v2 06/15] tcg/arm: Implement minimal vector operations

Implementing dup2, add, sub, and, or, xor as the minimal set. This allows us to actually enable neon in the header file. Signed-off-by: Richard Henderson --- tcg/arm/tcg-target-con-set.h | 3 + tcg/arm/tcg-target-con-str.h | 2 + tcg/arm/tcg-target.h | 6 +- tcg/arm/tcg-target.c.in

[RFC PATCH 1/5] Update Linux headers with new MTE support

Signed-off-by: Haibo Xu --- linux-headers/linux/kvm.h | 15 +++ 1 file changed, 15 insertions(+) diff --git a/linux-headers/linux/kvm.h b/linux-headers/linux/kvm.h index 020b62a619..6a291a9a35 100644 --- a/linux-headers/linux/kvm.h +++ b/linux-headers/linux/kvm.h @@ -1056,6 +1056,7 @

[PATCH v2 07/15] tcg/arm: Implement andc, orc, abs, neg, not vector operations

These logical and arithmetic operations are optional, but are trivial to accomplish with the existing infrastructure. Signed-off-by: Richard Henderson --- tcg/arm/tcg-target-con-set.h | 1 + tcg/arm/tcg-target.h | 10 +- tcg/arm/tcg-target.c.inc | 38

Re: [PATCH v3 00/70] TCI fixes and cleanups

Patchew URL: https://patchew.org/QEMU/20210208023752.270606-1-richard.hender...@linaro.org/ Hi, This series seems to have some coding style problems. See output below for more information: Type: series Message-id: 20210208023752.270606-1-richard.hender...@linaro.org Subject: [PATCH v3 00/70]

[RFC PATCH 3/5] Add APIs to get/set MTE tags

MTE spec provide instructions to retrieve the memory tags: (1) LDG, at 16 bytes granularity, and available in both user and kernel space; (2) LDGM, at 256 bytes granularity in maximum, and only available in kernel space To improve the performance, KVM has exposed the LDGM capability to use

[PATCH v2 08/15] tcg/arm: Implement TCG_TARGET_HAS_shi_vec

This consists of the three immediate shifts: shli, shri, sari. Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.h | 2 +- tcg/arm/tcg-target.c.inc | 27 +++ 2 files changed, 28 insertions(+), 1 deletion(-) diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-targe

[RFC PATCH 2/5] Add basic MTE support to KVM guest

Enable the virt machine feature "mte" to work with KVM guest. This feature is still hiden from the user in this patch, and will be available in a later patch. Signed-off-by: Haibo Xu --- hw/arm/virt.c | 22 +++--- target/arm/cpu.c | 2 +- target/arm/kvm.c | 9 +

[PATCH v2 10/15] tcg/arm: Implement TCG_TARGET_HAS_sat_vec

This is saturating add and subtract, signed and unsigned. Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.h | 2 +- tcg/arm/tcg-target.c.inc | 24 2 files changed, 25 insertions(+), 1 deletion(-) diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h inde

[PATCH v2 12/15] tcg/arm: Implement TCG_TARGET_HAS_bitsel_vec

NEON has 3 instructions implementing this 4 argument operation, with each insn overlapping a different logical input onto the destination register. Signed-off-by: Richard Henderson --- tcg/arm/tcg-target-con-set.h | 1 + tcg/arm/tcg-target.h | 2 +- tcg/arm/tcg-target.c.inc | 22 ++

[PATCH v2 15/15] tcg/arm: Implement TCG_TARGET_HAS_rotv_vec

Implement via expansion, so don't actually set TCG_TARGET_HAS_rotv_vec. Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.c.inc | 35 ++- 1 file changed, 34 insertions(+), 1 deletion(-) diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index

[PATCH v2 01/16] tcg/s390x: Rename from tcg/s390

This emphasizes that we don't support s390, only 64-bit s390x hosts. Reviewed-by: Thomas Huth Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- meson.build | 2 -- tcg/{s390 => s390x}/tcg-target-con-set.h | 0 tcg/{s390 => s390x}/tcg-target-c

[PATCH v2 02/16] tcg/s390x: Change FACILITY representation

We will shortly need to be able to check facilities beyond the first 64. Instead of explicitly masking against s390_facilities, create a HAVE_FACILITY macro that indexes an array. Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: David Hildenbrand Signed-off-by: Richard Henderson --- v2: Change

[PATCH v2 04/16] tcg/s390x: Add host vector framework

Add registers and function stubs. The functionality is disabled via squashing s390_facilities[2] to 0. We must still include results for the mandatory opcodes in tcg_target_op_def, as all opcodes are checked during tcg init. Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target-con-set.h |

[PATCH v2 09/16] tcg/s390x: Implement andc, orc, abs, neg, not vector operations

These logical and arithmetic operations are optional but trivial. Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target-con-set.h | 1 + tcg/s390x/tcg-target.h | 10 +- tcg/s390x/tcg-target.c.inc | 34 +- 3 files changed, 39 insertions(+),

Re: [PATCH 3/3] virtio-net: graceful fallback to vhost=off for tap netdev

On 2021/2/5 上午4:29, Yuri Benditovich wrote: Currently virtio-net silently clears features if they are not supported by respective vhost. This may create migration problems in future if vhost features on the source and destination are different. Implement graceful fallback to no-vhost mode when

[PATCH v2 10/16] tcg/s390x: Implement TCG_TARGET_HAS_mul_vec

Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target.h | 2 +- tcg/s390x/tcg-target.c.inc | 7 +++ 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/tcg/s390x/tcg-target.h b/tcg/s390x/tcg-target.h index dd11972ed2..13b9918276 100644 --- a/tcg/s390x/tcg-target.h +++ b/tcg/

[PATCH v2 11/16] tcg/s390x: Implement vector shift operations

Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target-con-set.h | 1 + tcg/s390x/tcg-target.h | 12 ++--- tcg/s390x/tcg-target.c.inc | 93 +- 3 files changed, 99 insertions(+), 7 deletions(-) diff --git a/tcg/s390x/tcg-target-con-set.h b/tcg/s390x

[PATCH v2 14/16] tcg/s390x: Implement TCG_TARGET_HAS_sat_vec

The unsigned saturations are handled via generic code using min/max. The signed saturations are expanded using double-sized arithmetic and a saturating pack. Since all operations are done via expansion, do not actually set TCG_TARGET_HAS_sat_vec. Signed-off-by: Richard Henderson --- tcg/s390x/

Re: [PATCH 3/3] virtio-net: graceful fallback to vhost=off for tap netdev

On 2021/2/5 下午9:38, Michael S. Tsirkin wrote: On Thu, Feb 04, 2021 at 10:29:15PM +0200, Yuri Benditovich wrote: Currently virtio-net silently clears features if they are not supported by respective vhost. This may create migration problems in future if vhost features on the source and destinat

[RFC PATCH 5/5] Enable the MTE support for KVM guest

Signed-off-by: Haibo Xu --- hw/arm/virt.c | 22 +++--- 1 file changed, 19 insertions(+), 3 deletions(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 623d5e9397..c2358cf4c5 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -79,6 +79,7 @@ #include "hw/virtio/virtio-iommu.h" #

Re: [PATCH 0/3] hw/sd: sd: erase operation fixes

On Thu, Jan 28, 2021 at 2:43 PM Bin Meng wrote: > > From: Bin Meng > > This includes several fixes related to erase operation of a SD card. > > Based-on: > http://patchwork.ozlabs.org/project/qemu-devel/list/?series=226785 > > > Bin Meng (3): > hw/sd: sd: Fix address check in sd_erase() > hw/

[PATCH v2 1/2] hw/ssi: xilinx_spips: Clean up coding convention issues

From: Xuzhou Cheng There are some coding convention warnings in xilinx_spips.c, as reported by: $ ./scripts/checkpatch.pl hw/ssi/xilinx_spips.c Let's clean them up. Signed-off-by: Xuzhou Cheng Signed-off-by: Bin Meng Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Peter Maydell --- (no

[PATCH v2 0/2] ZynqMP QSPI supports SPI transfer using DMA mode, but currently this

From: Bin Meng is unimplemented. When QSPI is programmed to use DMA mode, QEMU will crash. This is observed when testing VxWorks 7. Add a basic implementation of QSPI DMA functionality. Changes in v2: - Remove unconnected TYPE_STREAM_SINK link property - Add a TYPE_MEMORY_REGION link property,

[PATCH v2 2/2] hw/ssi: xilinx_spips: Implement basic QSPI DMA support

From: Xuzhou Cheng ZynqMP QSPI supports SPI transfer using DMA mode, but currently this is unimplemented. When QSPI is programmed to use DMA mode, QEMU will crash. This is observed when testing VxWorks 7. Add a basic implementation of QSPI DMA functionality. Signed-off-by: Xuzhou Cheng Signed-

Re: [PULL v3 11/27] multi-process: setup PCI host bridge for remote device

On 06/02/2021 18.57, Philippe Mathieu-Daudé wrote: On 2/5/21 5:44 PM, Stefan Hajnoczi wrote: From: Jagannathan Raman PCI host bridge is setup for the remote device process. It is implemented using remote-pcihost object. It is an extension of the PCI host bridge setup by QEMU. Remote-pcihost co

[PATCH v8 02/35] Hexagon (target/hexagon) README

Gives an introduction and overview to the Hexagon target Signed-off-by: Taylor Simpson --- target/hexagon/README | 235 ++ 1 file changed, 235 insertions(+) create mode 100644 target/hexagon/README diff --git a/target/hexagon/README b/target/hexa

[PATCH v8 12/35] Hexagon (target/hexagon) instruction attributes

Signed-off-by: Taylor Simpson Reviewed-by: Philippe Mathieu-Daudé --- target/hexagon/attribs.h | 35 +++ target/hexagon/attribs_def.h.inc | 97 2 files changed, 132 insertions(+) create mode 100644 target/hexagon/attribs.h create mod

[PATCH v8 11/35] Hexagon (target/hexagon) register fields

Declare bitfields within registers such as user status register (USR) Signed-off-by: Taylor Simpson --- target/hexagon/reg_fields.h | 36 target/hexagon/reg_fields_def.h.inc | 41 + target/hexagon/reg_fields.c |

[PATCH v8 04/35] Hexagon (target/hexagon) scalar core definition

Add target state header, target definitions and initialization routines Signed-off-by: Taylor Simpson --- target/hexagon/cpu-param.h | 29 + target/hexagon/cpu.h | 159 +++ target/hexagon/cpu_bits.h | 58 + target/hexagon/internal.h | 35 + target/h

[PATCH v8 13/35] Hexagon (target/hexagon) instruction/packet decode

Take the words from instruction memory and build a packet_t for TCG code generation The following operations are performed Convert the .new encoded offset to the register number of the producer Reorder the packet so .new producer is before consumer Apply constant extenders Separate

[PATCH v8 03/35] Hexagon (include/elf.h) ELF machine definition

Define EM_HEXAGON 164 Signed-off-by: Taylor Simpson Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- include/elf.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/elf.h b/include/elf.h index 7a418ee..f4fa3c1 100644 --- a/incl

[PATCH v8 01/35] Hexagon Update MAINTAINERS file

Add Taylor Simpson as the Hexagon target maintainer Signed-off-by: Taylor Simpson Reviewed-by: Richard Henderson --- MAINTAINERS | 9 + 1 file changed, 9 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 8d8b0bf..4130008 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -188,6 +18

[PATCH v8 14/35] Hexagon (target/hexagon) instruction printing

Signed-off-by: Taylor Simpson Reviewed-by: Philippe Mathieu-Daudé --- target/hexagon/printinsn.h | 27 + target/hexagon/printinsn.c | 146 + 2 files changed, 173 insertions(+) create mode 100644 target/hexagon/printinsn.h create mode 100644

[PATCH v8 19/35] Hexagon (target/hexagon) generator phase 1 - C preprocessor for semantics

Run the C preprocessor across the instruction definition files and macro definition file to expand macros and prepare the semantics_generated.pyinc file. The resulting file contains one entry with the semantics for each instruction and one line with the instruction attributes associated with each

[PATCH v8 00/35] Hexagon patch series

This series adds support for the Hexagon processor with Linux user support See patch 02 Hexagon README for detailed information. This series assumes int128_or() is implemented. https://lists.nongnu.org/archive/html/qemu-devel/2020-10/msg06004.html The series is also available at https://github.c

[PATCH v8 07/35] Hexagon (target/hexagon) scalar core helpers

The majority of helpers are generated. Define the helper functions needed then include the generated file Signed-off-by: Taylor Simpson --- target/hexagon/helper.h| 88 target/hexagon/op_helper.c | 1064 2 files changed, 1152 insertions(+)

[PATCH v8 05/35] Hexagon (disas) disassembler

Add hexagon to disas/meson.build Add disas/hexagon.c Add hexagon to include/disas/dis-asm.h Signed-off-by: Taylor Simpson Tested-by: Philippe Mathieu-Daudé Reviewed-by: Philippe Mathieu-Daudé --- include/disas/dis-asm.h | 1 + disas/hexagon.c | 65 +

[PATCH v8 06/35] Hexagon (target/hexagon) register names

Signed-off-by: Taylor Simpson Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé --- target/hexagon/hex_regs.h | 83 +++ 1 file changed, 83 insertions(+) create mode 100644 target/hexagon/hex_regs.h diff --git a/target/hexagon/hex_re

[PATCH v8 17/35] Hexagon (target/hexagon/fma_emu.[ch]) utility functions

Signed-off-by: Taylor Simpson --- target/hexagon/fma_emu.h | 36 +++ target/hexagon/fma_emu.c | 702 +++ 2 files changed, 738 insertions(+) create mode 100644 target/hexagon/fma_emu.h create mode 100644 target/hexagon/fma_emu.c diff --git a/target/h

[PATCH v8 16/35] Hexagon (target/hexagon/conv_emu.[ch]) utility functions

Signed-off-by: Taylor Simpson --- target/hexagon/conv_emu.h | 31 target/hexagon/conv_emu.c | 177 ++ 2 files changed, 208 insertions(+) create mode 100644 target/hexagon/conv_emu.h create mode 100644 target/hexagon/conv_emu.c diff --git a/

[PATCH v8 15/35] Hexagon (target/hexagon/arch.[ch]) utility functions

Signed-off-by: Taylor Simpson --- target/hexagon/arch.h | 34 ++ target/hexagon/arch.c | 300 ++ 2 files changed, 334 insertions(+) create mode 100644 target/hexagon/arch.h create mode 100644 target/hexagon/arch.c diff --git a/target/hexagon

[PATCH v8 33/35] Hexagon (tests/tcg/hexagon) TCG tests - floating point

Signed-off-by: Taylor Simpson --- tests/tcg/hexagon/fpstuff.c | 370 ++ tests/tcg/hexagon/Makefile.target | 1 + 2 files changed, 371 insertions(+) create mode 100644 tests/tcg/hexagon/fpstuff.c diff --git a/tests/tcg/hexagon/fpstuff.c b/tests/tcg/hex

[PATCH v8 10/35] Hexagon (target/hexagon) instruction and packet types

The insn_t and packet_t are the interface between instruction decoding and TCG code generation Signed-off-by: Taylor Simpson --- target/hexagon/insn.h | 74 +++ 1 file changed, 74 insertions(+) create mode 100644 target/hexagon/insn.h diff --git

[PATCH v8 32/35] Hexagon (tests/tcg/hexagon) TCG tests - atomics/load/store/misc

Signed-off-by: Taylor Simpson --- tests/tcg/hexagon/atomics.c | 139 ++ tests/tcg/hexagon/dual_stores.c | 60 ++ tests/tcg/hexagon/mem_noshuf.c| 328 tests/tcg/hexagon/misc.c | 380 ++ tests

[PATCH v8 09/35] Hexagon (target/hexagon) architecture types

Define types used in files imported from the Hexagon architecture library Signed-off-by: Taylor Simpson --- target/hexagon/hex_arch_types.h | 38 ++ 1 file changed, 38 insertions(+) create mode 100644 target/hexagon/hex_arch_types.h diff --git a/target/hexag

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