We only tested it on x86-64 and aarch64, but we couldn't repro on arm.
It is possible that this affects other platforms as well, but note that
this is specifically mentioned in the qemu wiki as one of the cases that
should be covered when porting mttcg to a new platform:
https://wiki.qemu.org/Featu
Per the ARM Generic Interrupt Controller Architecture specification
(document "ARM IHI 0048B.b (ID072613)"), the SGIINTID field is 4 bit,
not 10:
- 4.3 Distributor register descriptions
- 4.3.15 Software Generated Interrupt Register, GICD_SG
- Table 4-21 GICD_SGIR bit assignments
The
On 1/31/21 11:34 AM, Philippe Mathieu-Daudé wrote:
> Per the ARM Generic Interrupt Controller Architecture specification
> (document "ARM IHI 0048B.b (ID072613)"), the SGIINTID field is 4 bit,
> not 10:
>
> - 4.3 Distributor register descriptions
> - 4.3.15 Software Generated Interrupt Registe
Commit 299e6f19b3e ("vhost-net: revamp configure logic") added
the --enable-vhost-kernel option.
Disable it in the build-disable job.
Signed-off-by: Philippe Mathieu-Daudé
---
.gitlab-ci.yml | 1 +
1 file changed, 1 insertion(+)
diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
index 7c0db64710b..e8
** Changed in: qemu
Status: New => Confirmed
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https://bugs.launchpad.net/bugs/1913916
Title:
aarch64-virt: heap-buffer-overflow in address_space_lookup_region
Status in QEMU:
** Changed in: qemu
Status: New => Confirmed
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https://bugs.launchpad.net/bugs/1913917
Title:
aarch64-virt: heap-use-after-free in gic_dist_writeb
Status in QEMU:
Confirmed
B
Trivial bugfixes and cleanup patches noticed while rebasing
my "Support disabling TCG on ARM (part 2)" series.
Since v1:
- added patches to remove 64-bit specific features on 32-bit build.
Philippe Mathieu-Daudé (7):
hw/arm/stm32f405_soc: Add missing dependency on OR_IRQ
hw/arm/exynos4210: Ad
The STM32F405 SoC uses an OR gate on its ADC IRQs.
Fixes: 529fc5fd3e1 ("hw/arm: Add the STM32F4xx SoC")
Signed-off-by: Philippe Mathieu-Daudé
---
Cc: alist...@alistair23.me
---
hw/arm/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index 13cc42dcc84..a
The ZynqMP ZCU102 board only use the Cortex-A53 CPU, which
is only available in the 64-bit build. It is pointless to
have this board present in the 32-bit build where this CPU
is not available.
Signed-off-by: Philippe Mathieu-Daudé
---
Cc: Alistair Francis
Cc: "Edgar E. Iglesias"
---
hw/arm/me
The Exynos4210 SoC uses an OR gate on the PL330 IRQ lines.
Fixes: dab15fbe2ab ("hw/arm/exynos4210: Fix DMA initialization")
Signed-off-by: Philippe Mathieu-Daudé
---
Cc: Igor Mitsyanko
---
hw/arm/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index a
The SBSA-ref board only use CPUs available in the 64-bit build,
it is pointless to have it available in the 32-bit build.
Signed-off-by: Philippe Mathieu-Daudé
---
Cc: Radoslaw Biernacki
Cc: Leif Lindholm
---
hw/arm/meson.build | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
The Versal SoC instantiates the TYPE_XLNX_ZDMA object in
versal_create_admas(). Introduce the XLNX_ZDMA configuration
and select it to fix:
$ qemu-system-aarch64 -M xlnx-versal-virt ...
qemu-system-aarch64: missing object type 'xlnx.zdma'
Signed-off-by: Philippe Mathieu-Daudé
---
Cc: Alistai
Most of ARM machines display their CPU when QEMU list the available
machines (-M help). Some machines do not. Fix to unify the help
output.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/arm/digic_boards.c | 2 +-
hw/arm/microbit.c | 2 +-
hw/arm/netduino2.c | 2 +-
hw/arm/netduinoplus2.
Similarly to commit 210f47840dd, remove 64-bit CPUs (which have
never been available on 32-bit build, see commit d14d42f19bf),
to fix:
$ make check-qtest-arm
...
Running test qtest-arm/device-introspect-test
missing object type 'cortex-a53-arm-cpu'
Broken pipe
../tests/qtest/libqtest.c
Fix for this 13+ years old issue:
https://lists.gnu.org/archive/html/qemu-devel/2021-01/msg07969.html
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https://bugs.launchpad.net/bugs/1913917
Title:
aarch64-virt: heap-use-after-free
Fix for this 13+ years old issue:
https://lists.gnu.org/archive/html/qemu-devel/2021-01/msg07969.html
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https://bugs.launchpad.net/bugs/1913916
Title:
aarch64-virt: heap-buffer-overflow
Hi,
This series add a Kconfig file to each target, allowing
to select target-specific features there, instead of from
the hardware Kconfig.
This simplifies managing multi-arch features such semihosting.
Series organization:
1/ Some targets use the architecture symbol to select boards and
periph
We want to be able to use the 'SH4' config for architecture
specific features. As CONFIG_SH4 is only used to select
peripherals, rename it CONFIG_SH4_PERIPHERALS.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/block/meson.build | 2 +-
hw/char/meson.build | 2 +-
hw/intc/meson.build | 2 +-
hw/s
ARM_COMPATIBLE_SEMIHOSTING is an architecture feature, move its
declaration to each target/ARCH/.
Note, we do not modify the linux-user targets, as user-mode builds
don't use Kconfig.
Signed-off-by: Philippe Mathieu-Daudé
---
default-configs/devices/arm-softmmu.mak | 1 -
default-configs/de
We want to be able to use the 'LM32' config for architecture
specific features. As CONFIG_LM32 is only used to select
peripherals, rename it CONFIG_LM32_PERIPHERALS.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/char/meson.build | 4 ++--
hw/intc/meson.build | 2 +-
hw/lm32/Kconfig | 4 ++-
Add a target-specific Kconfig.
Target foo now has CONFIG_FOO defined.
Two architecture have a particularity, ARM and MIPS:
their 64-bit version include the 32-bit subset.
Signed-off-by: Philippe Mathieu-Daudé
---
I suppose X86_64 should also select I386?
No clue about PPC/RISCV.
---
meson.buil
We want to be able to use the 'LM32' config for architecture
specific features. Introduce CONFIG_LM32_EVR to select the
lm32-evr / lm32-uclinux boards.
Signed-off-by: Philippe Mathieu-Daudé
---
default-configs/devices/lm32-softmmu.mak | 2 +-
hw/lm32/Kconfig | 6 +-
SEMIHOSTING is an architecture feature, move its declaration to
each target/ARCH/.
Signed-off-by: Philippe Mathieu-Daudé
---
default-configs/devices/lm32-softmmu.mak| 2 --
default-configs/devices/m68k-softmmu.mak| 2 --
default-configs/devices/mips-softmmu-common.mak | 3 ---
de
SEV is an architecture feature, move its declaration to target/i386/.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/i386/Kconfig | 4
target/i386/Kconfig | 4
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/i386/Kconfig b/hw/i386/Kconfig
index 7f91f30877f..3d67c172
V7M is an architecture feature, move its declaration to target/arm/.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/arm/Kconfig | 4
target/arm/Kconfig | 4
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index 09298881f2f..f3ecb73a3d8 1
The Milkymist board requires more than the PTIMER. Directly
select the LM32_PERIPHERALS. This fixes:
/usr/bin/ld:
libqemu-lm32-softmmu.fa.p/target_lm32_gdbstub.c.o: in function
`lm32_cpu_gdb_read_register':
target/lm32/gdbstub.c:46: undefined reference to `lm32_pic_get_im'
target/lm32/gdb
Commit 56b5170c87e ("semihosting: Move ARM semihosting code to
shared directories") selected ARM_COMPATIBLE_SEMIHOSTING which
already selects SEMIHOSTING. No need to select it again.
Signed-off-by: Philippe Mathieu-Daudé
---
default-configs/devices/arm-softmmu.mak | 1 -
default-configs/devi
Hi,
After reading related source code and discussions in the mailing list,
I understand that:
1. tb_page_add() calls tlb_protect_code() to clear the code page by
setting TLB_NOTDIRTY in .addr_write field of corresponding CPUTLBEntry
*of all vCPUs*.
2. Updating and accessing (even from TCG-gener
вс, 31 янв. 2021 г., 12:13 Philippe Mathieu-Daudé :
> Add a target-specific Kconfig.
>
> Target foo now has CONFIG_FOO defined.
>
> Two architecture have a particularity, ARM and MIPS:
> their 64-bit version include the 32-bit subset.
>
> Signed-off-by: Philippe Mathieu-Daudé
>
For SPARC part:
A
Cover from Samuel Ortiz from (part 1) [1]:
This patchset allows for building and running ARM targets with TCG
disabled. [...]
The rationale behind this work comes from the NEMU project where
we're trying to only support x86 and ARM 64-bit architectures,
without including the TCG code ba
KVM requires the target cpu to be at least ARMv8 architecture
(support on ARMv7 has been dropped in commit 82bf7ae84ce:
"target/arm: Remove KVM support for 32-bit Arm hosts").
Only enable the following ARMv5 CPUs when TCG is available:
- ARM926
- ARM946
- ARM1026
- XScale (PXA250/255/260/
Modules are registered early with type_register_static().
We would like to call tcg_enabled() when registering QOM types,
but tcg_enabled() returns tcg_allowed which is a runtime property
initialized later (See commit 2f181fbd5a9 which introduced the
MachineInitPhase in "hw/qdev-core.h" representi
Fixes when building with --disable-tcg on ARM:
In file included from target/arm/helper.c:16:
include/exec/helper-proto.h:42:10: fatal error: tcg-runtime.h: No such file
or directory
42 | #include "tcg-runtime.h"
| ^~~
Signed-off-by: Philippe Mathieu-Daudé
-
KVM requires the target cpu to be at least ARMv8 architecture
(support on ARMv7 has been dropped in commit 82bf7ae84ce:
"target/arm: Remove KVM support for 32-bit Arm hosts").
Beside, KVM only supports A-profile, thus won't be able to run
R-profile cpus.
Only enable the following ARMv7 R-Profile
KVM requires the target cpu to be at least ARMv8 architecture
(support on ARMv7 has been dropped in commit 82bf7ae84ce:
"target/arm: Remove KVM support for 32-bit Arm hosts").
Beside, KVM only supports A-profile, thus won't be able to run
M-profile cpus.
Only enable the following ARMv7 M-Profile
KVM requires the target cpu to be at least ARMv8 architecture
(support on ARMv7 has been dropped in commit 82bf7ae84ce:
"target/arm: Remove KVM support for 32-bit Arm hosts").
Only enable the following ARMv4 CPUs when TCG is available:
- StrongARM (SA1100/1110)
- OMAP1510 (TI925T)
The follow
From: Thomas Huth
We've already got the CONFIG_ARM_V7M switch, but it currently can
not be disabled yet. The m_helper.c code should not be compiled
into the binary if the switch is not enabled. We also have to
provide some stubs in a separate file to make sure that we still
can link the other cod
From: Philippe Mathieu-Daudé
Reorder the rules to make this file easier to modify.
No logical change introduced in this commit.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
target/arm/meson.build | 19 ---
1 file changed, 12 insertions(+), 7 deletio
KVM requires the target cpu to be at least ARMv8 architecture
(support on ARMv7 has been dropped in commit 82bf7ae84ce:
"target/arm: Remove KVM support for 32-bit Arm hosts").
Only enable the following ARMv6 CPUs when TCG is available:
- ARM1136
- ARM1176
- ARM11MPCore
- Cortex-M0
The fo
On Sun, Jan 31, 2021 at 12:51 PM Philippe Mathieu-Daudé wrote:
>
> From: Philippe Mathieu-Daudé
>
> Add a job to build QEMU on Aarch64 with TCG disabled, so
> this configuration won't bitrot over time.
>
> We explicitly modify default-configs/aarch64-softmmu.mak to
> only select the 'virt' and 'S
From: Samuel Ortiz
We can now safely turn all TCG dependent build off when CONFIG_TCG is
off. This allows building ARM binaries with --disable-tcg.
Signed-off-by: Samuel Ortiz
[PMD: Heavily rebased during more than 2 years then finally rewritten]
Reviewed-by: Richard Henderson
Signed-off-by: P
From: Philippe Mathieu-Daudé
Add a job to build QEMU on Aarch64 with TCG disabled, so
this configuration won't bitrot over time.
We explicitly modify default-configs/aarch64-softmmu.mak to
only select the 'virt' and 'SBSA-REF' machines.
Signed-off-by: Philippe Mathieu-Daudé
---
Job ran for 7 m
+-- On Sun, 31 Jan 2021, Philippe Mathieu-Daudé wrote --+
| On 1/31/21 11:34 AM, Philippe Mathieu-Daudé wrote:
| > Per the ARM Generic Interrupt Controller Architecture specification
| > (document "ARM IHI 0048B.b (ID072613)"), the SGIINTID field is 4 bit,
| > not 10:
| >
| > - Table 4-21 GICD
On 1/31/21 11:59 AM, Philippe Mathieu-Daudé wrote:
> The SBSA-ref board only use CPUs available in the 64-bit build,
> it is pointless to have it available in the 32-bit build.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> Cc: Radoslaw Biernacki
> Cc: Leif Lindholm
> ---
> hw/arm/meson.bui
On 1/31/21 11:59 AM, Philippe Mathieu-Daudé wrote:
> The ZynqMP ZCU102 board only use the Cortex-A53 CPU, which
> is only available in the 64-bit build. It is pointless to
> have this board present in the 32-bit build where this CPU
> is not available.
>
> Signed-off-by: Philippe Mathieu-Daudé
>
On 1/31/21 12:13 PM, Philippe Mathieu-Daudé wrote:
> Add a target-specific Kconfig.
>
> Target foo now has CONFIG_FOO defined.
>
> Two architecture have a particularity, ARM and MIPS:
> their 64-bit version include the 32-bit subset.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
...
> diff -
On 1/31/21 12:50 PM, Philippe Mathieu-Daudé wrote:
> KVM requires the target cpu to be at least ARMv8 architecture
> (support on ARMv7 has been dropped in commit 82bf7ae84ce:
> "target/arm: Remove KVM support for 32-bit Arm hosts").
>
> Beside, KVM only supports A-profile, thus won't be able to ru
On Sun, 31 Jan 2021, Philippe Mathieu-Daudé wrote:
We want to be able to use the 'SH4' config for architecture
specific features. As CONFIG_SH4 is only used to select
peripherals, rename it CONFIG_SH4_PERIPHERALS.
PERIPHERALS is a bit long and hard to write correctly. How about
CONFIG_SH4_DEVI
Forwarding to qemu-security@ to see if this issue is worth a CVE.
On 1/31/21 12:57 PM, P J P wrote:
> +-- On Sun, 31 Jan 2021, Philippe Mathieu-Daudé wrote --+
> | On 1/31/21 11:34 AM, Philippe Mathieu-Daudé wrote:
> | > Per the ARM Generic Interrupt Controller Architecture specification
> | > (do
On 1/29/21 8:59 PM, Paolo Bonzini wrote:
> On 29/01/21 20:44, Philippe Mathieu-Daudé wrote:
>> hw/ide/ioport.c has a strong dependency on hw/isa/isa-bus.c:
>>
>> /usr/bin/ld: libcommon.fa.p/hw_ide_ioport.c.o: in function
>> `ide_init_ioport':
>> /usr/bin/ld: hw/ide/ioport.c:61: undefined refe
Gentoo also noticed the bug: https://bugs.gentoo.org/766743
Jannik Glückert proposed a fix:
```
--- a/pc-bios/descriptors/meson.build
+++ b/pc-bios/descriptors/meson.build
@@ -8,7 +8,7 @@ foreach f: [
]
configure_file(input: files(f),
output: f,
- configurati
Sort the Xen buildsys glue a bit.
v2: Considered Paolo's comments from v1
Supersedes: <20210129194415.3925153-1-f4...@amsat.org>
Philippe Mathieu-Daudé (4):
meson: Do not build Xen x86_64-softmmu on Aarch64
hw/i386/xen: Introduce XEN_FV Kconfig
hw/xen/Kconfig: Introduce XEN_PV config
hw/
On 1/31/21 12:50 PM, Philippe Mathieu-Daudé wrote:
> Modules are registered early with type_register_static().
>
> We would like to call tcg_enabled() when registering QOM types,
Hi Philippe,
could this not be controlled by meson at this stage?
On X86, I register the tcg-specific types in tcg/*
Introduce XEN_FV to differency the machine from the accelerator.
Suggested-by: Paolo Bonzini
Signed-off-by: Philippe Mathieu-Daudé
---
hw/i386/Kconfig | 2 ++
hw/i386/xen/Kconfig | 5 +
hw/i386/xen/meson.build | 2 +-
3 files changed, 8 insertions(+), 1 deletion(-)
create mode
The Xen on ARM documentation only mentions the i386-softmmu
target. As the x86_64-softmmu doesn't seem used, remove it
to avoid wasting cpu cycles building it.
Signed-off-by: Philippe Mathieu-Daudé
---
meson.build | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/meson.bui
9pfs is not an accelerator feature but a machine one,
move the selection on the machine Kconfig (in hw/).
Signed-off-by: Philippe Mathieu-Daudé
---
accel/Kconfig | 1 -
hw/i386/xen/Kconfig | 1 +
hw/xen/Kconfig | 1 +
3 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/accel
On 1/31/21 12:50 PM, Philippe Mathieu-Daudé wrote:
> Fixes when building with --disable-tcg on ARM:
>
> In file included from target/arm/helper.c:16:
> include/exec/helper-proto.h:42:10: fatal error: tcg-runtime.h: No such file
> or directory
> 42 | #include "tcg-runtime.h"
> |
xenpv machine requires USB, IDE_PIIX and PCI:
/usr/bin/ld:
libcommon.fa.p/hw_xen_xen-legacy-backend.c.o: in function
`xen_be_register_common':
hw/xen/xen-legacy-backend.c:757: undefined reference to `xen_usb_ops'
libqemu-i386-softmmu.fa.p/hw_i386_xen_xen_platform.c.o: in function
`unplug
On 1/31/21 12:50 PM, Philippe Mathieu-Daudé wrote:
> KVM requires the target cpu to be at least ARMv8 architecture
> (support on ARMv7 has been dropped in commit 82bf7ae84ce:
> "target/arm: Remove KVM support for 32-bit Arm hosts").
>
> Only enable the following ARMv4 CPUs when TCG is available:
>
On 1/31/21 12:50 PM, Philippe Mathieu-Daudé wrote:
> KVM requires the target cpu to be at least ARMv8 architecture
> (support on ARMv7 has been dropped in commit 82bf7ae84ce:
> "target/arm: Remove KVM support for 32-bit Arm hosts").
>
> Only enable the following ARMv5 CPUs when TCG is available:
>
On 1/31/21 12:50 PM, Philippe Mathieu-Daudé wrote:
> KVM requires the target cpu to be at least ARMv8 architecture
> (support on ARMv7 has been dropped in commit 82bf7ae84ce:
> "target/arm: Remove KVM support for 32-bit Arm hosts").
>
> Only enable the following ARMv6 CPUs when TCG is available:
>
On 1/31/21 12:50 PM, Philippe Mathieu-Daudé wrote:
> KVM requires the target cpu to be at least ARMv8 architecture
> (support on ARMv7 has been dropped in commit 82bf7ae84ce:
> "target/arm: Remove KVM support for 32-bit Arm hosts").
>
> Beside, KVM only supports A-profile, thus won't be able to ru
On 1/31/21 12:50 PM, Philippe Mathieu-Daudé wrote:
> KVM requires the target cpu to be at least ARMv8 architecture
> (support on ARMv7 has been dropped in commit 82bf7ae84ce:
> "target/arm: Remove KVM support for 32-bit Arm hosts").
>
> Beside, KVM only supports A-profile, thus won't be able to ru
Before the change /usr/share/qemu/firmware/50-edk2-x86_64-secure.json
contained the relative path:
"filename": "share/qemu/edk2-x86_64-secure-code.fd",
"filename": "share/qemu/edk2-i386-vars.fd",
After then change the paths are absolute:
"filename": "/usr/share/
On 1/31/21 12:50 PM, Philippe Mathieu-Daudé wrote:
> Cover from Samuel Ortiz from (part 1) [1]:
>
> This patchset allows for building and running ARM targets with TCG
> disabled. [...]
>
> The rationale behind this work comes from the NEMU project where
> we're trying to only support x86
On 31/01/2021 14:18, Philippe Mathieu-Daudé wrote:
> The Xen on ARM documentation only mentions the i386-softmmu
> target. As the x86_64-softmmu doesn't seem used, remove it
> to avoid wasting cpu cycles building it.
>
> Signed-off-by: Philippe Mathieu-Daudé
As far as I understand, it only gets u
On 1/31/21 3:34 PM, Sergei Trofimovich wrote:
> Before the change /usr/share/qemu/firmware/50-edk2-x86_64-secure.json
> contained the relative path:
> "filename": "share/qemu/edk2-x86_64-secure-code.fd",
> "filename": "share/qemu/edk2-i386-vars.fd",
>
> After then change th
Peter mentioned [*] KVM only support ARMv8 targets. Restrict the
non-ARMv8 machines to TCG.
While this is still not enough to boot a raspi3 image using KVM:
$ qemu-system-aarch64 -M raspi3b -enable-kvm ...
qemu-system-aarch64: ../../softmmu/physmem.c:745: cpu_address_space_init: A=
ssertion `
Move the abstract TYPE_BCM283X and TYPE_RASPI_MACHINE declarations
earlier to make the next commit easier to review.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/arm/bcm2836.c | 32 +---
hw/arm/raspi.c | 18 ++
2 files changed, 27 insertions(+), 23 d
KVM requires the target cpu to be at least ARMv8 architecture
(support on ARMv7 has been dropped in commit 82bf7ae84ce:
"target/arm: Remove KVM support for 32-bit Arm hosts").
>From the various SoC used by the Raspberry Pi machines, only
the BCM2837 is an ARMv8 (Cortex-A53).
Restrict the BCM2835
On 1/31/21 3:40 PM, Claudio Fontana wrote:
> On 1/31/21 12:50 PM, Philippe Mathieu-Daudé wrote:
>> Cover from Samuel Ortiz from (part 1) [1]:
>>
>> This patchset allows for building and running ARM targets with TCG
>> disabled. [...]
>>
>> The rationale behind this work comes from the NEMU pr
On 1/31/21 3:18 PM, Claudio Fontana wrote:
> On 1/31/21 12:50 PM, Philippe Mathieu-Daudé wrote:
>> Modules are registered early with type_register_static().
>>
>> We would like to call tcg_enabled() when registering QOM types,
>
>
> Hi Philippe,
>
> could this not be controlled by meson at this
On 1/31/21 1:31 PM, Philippe Mathieu-Daudé wrote:
> On 1/31/21 11:59 AM, Philippe Mathieu-Daudé wrote:
>> The ZynqMP ZCU102 board only use the Cortex-A53 CPU, which
>> is only available in the 64-bit build. It is pointless to
>> have this board present in the 32-bit build where this CPU
>> is not a
On 1/31/21 1:31 PM, Philippe Mathieu-Daudé wrote:
> On 1/31/21 11:59 AM, Philippe Mathieu-Daudé wrote:
>> The SBSA-ref board only use CPUs available in the 64-bit build,
>> it is pointless to have it available in the 32-bit build.
>>
>> Signed-off-by: Philippe Mathieu-Daudé
>> ---
>> Cc: Radoslaw
On 1/31/21 1:36 PM, Philippe Mathieu-Daudé wrote:
> On 1/31/21 12:13 PM, Philippe Mathieu-Daudé wrote:
>> Add a target-specific Kconfig.
>>
>> Target foo now has CONFIG_FOO defined.
>>
>> Two architecture have a particularity, ARM and MIPS:
>> their 64-bit version include the 32-bit subset.
>>
>> S
On 1/30/21 7:54 PM, Peter Maydell wrote:
> On Sat, 30 Jan 2021 at 18:36, Philippe Mathieu-Daudé wrote:
>>
>> Hi Peter,
>>
>> On 1/30/21 4:37 PM, Peter Maydell wrote:
>>> On Sat, 30 Jan 2021 at 01:52, Philippe Mathieu-Daudé
>>> wrote:
KVM requires a cpu based on (at least) the ARMv7 arc
Hi Zenghui,
On 1/30/21 5:32 AM, Zenghui Yu wrote:
> When handling guest range-based IOTLB invalidation, we should decode the TG
> field into the corresponding translation granule size so that we can pass
> the correct invalidation range to backend. Set @granule to (tg * 2 + 10) to
> properly emula
On 1/31/21 4:22 PM, Jannik Glückert wrote:
>> Jannik, can you send a Signed-off-by line so we can accept
>> your patch? See:
>> https://wiki.qemu.org/Contribute/SubmitAPatch#Patch_emails_must_include_a_Signed-off-by:_line
>
> Sure! I hope this is right, I'm not exactly experienced with mailing
> l
KVM requires the target cpu to be at least ARMv8 architecture.
Restrict the last ARMv7 CPUs (A-profile) to TCG.
(This is where I realize no need to split the v7 A/R/M profiles
anymore... I could have use a single ARM_V7, although it is useful
to have the M-profile separated).
Based-on: <20210131
Machines can be automatically selected using the Kconfig
'default y' syntax. This change allow deselecting these
machines without having to modify default-configs/ files.
Signed-off-by: Philippe Mathieu-Daudé
---
default-configs/devices/aarch64-softmmu.mak | 3 ---
default-configs/devices/arm-so
KVM requires the target cpu to be at least ARMv8 architecture
(support on ARMv7 has been dropped in commit 82bf7ae84ce:
"target/arm: Remove KVM support for 32-bit Arm hosts").
The following machines are no more built when TCG is disabled:
- cubieboard cubietech cubieboard (Cortex-A8)
KVM requires the target cpu to be at least ARMv8 architecture
(support on ARMv7 has been dropped in commit 82bf7ae84ce:
"target/arm: Remove KVM support for 32-bit Arm hosts").
A KVM-only build won't be able to run TCG cpus, move the
v7A CPU definitions to cpu_tcg.c.
Reported-by: Peter Maydell
Si
IDAU is specific to M-profile. KVM only supports A-profile.
Restrict this interface to TCG, as it is pointless (and
confusing) on a KVM-only build.
Signed-off-by: Philippe Mathieu-Daudé
---
target/arm/cpu.c | 7 ---
target/arm/cpu_tcg.c | 8
2 files changed, 8 insertions(+), 7 d
We will move this code in the next commit. Clean it up
first to avoid checkpatch.pl errors.
Signed-off-by: Philippe Mathieu-Daudé
---
target/arm/cpu.c | 12
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index d0853fae5ae..2d8312267
#ifdef DEBUG
-alsa_dump_info(req, obt, obtfmt, pdo);
+alsa_dump_info(req, obt, obtfmt, apdo);
#endif
"if (DEBUG) { }" is a nice way to have this checked by the
compiler. With "#define DEBUG 0" the compiler will optimize away
the dead code, so it isn't much different to #ifdef'ed
> Jannik, can you send a Signed-off-by line so we can accept
> your patch? See:
> https://wiki.qemu.org/Contribute/SubmitAPatch#Patch_emails_must_include_a_Signed-off-by:_line
Sure! I hope this is right, I'm not exactly experienced with mailing
list development.
Signed-off-by: Jannik Glückert
>
Hi,
-hw->samples = obt.samples;
+hw->samples = (spdo->has_buffer_count ? spdo->buffer_count : 4) *
+obt.samples;
+# @buffer-count: number of buffers (default 4)
Any specific reason for this default?
In my testing I've needed much higher values.
8 still got me crackling sound
Commit 4e66c9ef64 "tracetool: add input filename and line number to
Event" forgot to add a line number and a filename argument at one
build method call site.
Traceback (most recent call last):
File "./scripts/simpletrace.py", line 261, in
run(Formatter())
File "./scripts/simpletrace.py",
Hi,
I started setting up some developer documentation for 9pfs:
https://wiki.qemu.org/Documentation/9p
Still quite a bunch that should be added (e.g. there should be a section about
threads and coroutines), but at least it's a start ...
Best regards,
Christian Schoenebeck
On 1/31/21 5:44 PM, Philippe Mathieu-Daudé wrote:
> KVM requires the target cpu to be at least ARMv8 architecture
> (support on ARMv7 has been dropped in commit 82bf7ae84ce:
> "target/arm: Remove KVM support for 32-bit Arm hosts").
>
> The following machines are no more built when TCG is disabled:
Trivial bugfixes and cleanup patches noticed while rebasing
my "Support disabling TCG on ARM (part 2)" series.
Since v2:
- removed incorrect patches added in v2 =)
- more fixes for Versal board (CAN, RTC)
Since v1:
- added patches to remove 64-bit specific features on 32-bit build.
Philippe Math
The Exynos4210 SoC uses an OR gate on the PL330 IRQ lines.
Fixes: dab15fbe2ab ("hw/arm/exynos4210: Fix DMA initialization")
Signed-off-by: Philippe Mathieu-Daudé
---
Cc: Igor Mitsyanko
---
hw/arm/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index a
The STM32F405 SoC uses an OR gate on its ADC IRQs.
Fixes: 529fc5fd3e1 ("hw/arm: Add the STM32F4xx SoC")
Signed-off-by: Philippe Mathieu-Daudé
---
Cc: alist...@alistair23.me
---
hw/arm/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index 13cc42dcc84..a
The Versal SoC instantiates the TYPE_XLNX_ZDMA object in
versal_create_admas(). Introduce the XLNX_ZDMA configuration
and select it to fix:
$ qemu-system-aarch64 -M xlnx-versal-virt ...
qemu-system-aarch64: missing object type 'xlnx.zdma'
Signed-off-by: Philippe Mathieu-Daudé
---
Cc: Alistai
Add a dependency XLNX_ZYNQMP -> PTIMER to fix:
/usr/bin/ld:
libcommon.fa.p/hw_net_can_xlnx-zynqmp-can.c.o: in function
`xlnx_zynqmp_can_realize':
hw/net/can/xlnx-zynqmp-can.c:1082: undefined reference to `ptimer_init'
hw/net/can/xlnx-zynqmp-can.c:1085: undefined reference to
`ptimer_tran
The Versal SoC instantiates the TYPE_XLNX_ZYNQMP_RTC object in
versal_create_rtc()(). Select CONFIG_XLNX_ZYNQMP to fix:
$ make check-qtest-aarch64
...
Running test qtest-aarch64/qom-test
qemu-system-aarch64: missing object type 'xlnx-zynmp.rtc'
Broken pipe
Signed-off-by: Philippe Mathie
Most of ARM machines display their CPU when QEMU list the available
machines (-M help). Some machines do not. Fix to unify the help
output.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/arm/digic_boards.c | 2 +-
hw/arm/microbit.c | 2 +-
hw/arm/netduino2.c | 2 +-
hw/arm/netduinoplus2.
On 1/31/21 3:45 PM, andrew.cooper3--- via wrote:
> On 31/01/2021 14:18, Philippe Mathieu-Daudé wrote:
>> The Xen on ARM documentation only mentions the i386-softmmu
>> target. As the x86_64-softmmu doesn't seem used, remove it
>> to avoid wasting cpu cycles building it.
>>
>> Signed-off-by: Philipp
I have identified the core issue:
Synchronous exceptions/traps in linux-user/i386/cpu_loop.c are handled as a
return value from cpu_exec().
cpu_exec() resets exception_index to -1 in cpu_handle_exception()
This means that queue_signal() (called from gen_signal() in the cpu
loop) does not store
On 1/31/21 6:34 PM, Volker Rümelin wrote:
> Commit 4e66c9ef64 "tracetool: add input filename and line number to
> Event" forgot to add a line number and a filename argument at one
> build method call site.
>
> Traceback (most recent call last):
> File "./scripts/simpletrace.py", line 261, in
>
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