Re: [PATCH] fuzz: fix wrong index in clear_bits

On 28/01/21 04:59, Qiuhao Li wrote: Signed-off-by: Qiuhao Li --- scripts/oss-fuzz/minimize_qtest_trace.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/scripts/oss-fuzz/minimize_qtest_trace.py b/scripts/oss-fuzz/minimize_qtest_trace.py index 4cba96dee2..20825768c2 10075

[PATCH 01/23] configure: Fix --enable-tcg-interpreter

The configure option was backward, and we failed to pass the value on to meson. Fixes: 23a77b2d18b Signed-off-by: Richard Henderson --- configure | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/configure b/configure index dcc5ea7d63..ad35e26168 100755 --- a/configure +++

[PATCH 00/23] TCI fixes and cleanups

The first patch I believe is queued by Paolo, but is not yet upstream; copied here for convenience. Then, fill in all of the TODO blanks in TCI. The tci_write_reg* functions are redundant with tcg_write_reg. Just pass in the properly truncated result to begin. In the cases of the loads, we've au

[PATCH 03/23] exec: Make tci_tb_ptr thread-local

Each thread must have its own pc, even under TCI. Signed-off-by: Richard Henderson --- include/exec/exec-all.h | 2 +- tcg/tcg-common.c| 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 125000bcf7..f933c74c44 100

[PATCH 07/23] tcg/tci: Inline tci_write_reg8 into its callers

Signed-off-by: Richard Henderson --- tcg/tci.c | 9 ++--- 1 file changed, 2 insertions(+), 7 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index 438d712ea8..7797558b2a 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -115,11 +115,6 @@ tci_write_reg(tcg_target_ulong *regs, TCGReg index, tcg_targe

[PATCH 05/23] tcg/tci: Implement INDEX_op_ld8s_i64

From: Stefan Weil That TCG opcode is used by debian-buster (arm64) running ffmpeg: qemu-aarch64 /usr/bin/ffmpeg -i theora.mkv theora.webm Reported-by: Alex Bennée Signed-off-by: Stefan Weil Message-Id: <20210128020425.2055454-1...@weilnetz.de> Signed-off-by: Richard Henderson --- tcg/tc

[PATCH 04/23] tcg/tci: Implement INDEX_op_ld16s_i32

From: Stefan Weil That TCG opcode is used by debian-buster (arm64) running ffmpeg: qemu-aarch64 /usr/bin/ffmpeg -i theora.mkv theora.webm Reported-by: Alex Bennée Signed-off-by: Stefan Weil Message-Id: <20210128024814.2056958-1...@weilnetz.de> Signed-off-by: Richard Henderson --- tcg/tc

[PATCH 16/23] tcg/tci: Merge INDEX_op_st8_{i32,i64}

Signed-off-by: Richard Henderson --- tcg/tci.c | 7 +-- 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index 233fc0604e..0978a5c554 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -606,6 +606,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,

[PATCH 02/23] tcg: Manage splitwx in tc_ptr_to_region_tree by hand

The use in tcg_tb_lookup is given a random pc that comes from the pc of a signal handler. Do not assert that the pointer is already within the code gen buffer at all, much less the writable mirror of it. Fixes: db0c51a3803 Signed-off-by: Richard Henderson --- For TCI, this indicates a bug in ha

[PATCH 11/23] tcg/tci: Merge INDEX_op_ld8u_{i32,i64}

Signed-off-by: Richard Henderson --- tcg/tci.c | 7 +-- 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index 864771d91b..019035d52f 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -571,6 +571,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,

[PATCH 19/23] tcg/tci: Merge INDEX_op_{st_i32,st32_i64}

Signed-off-by: Richard Henderson --- tcg/tci.c | 7 +-- 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index c4c303f874..66b90f8489 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -620,6 +620,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,

[PATCH 09/23] tcg/tci: Inline tci_write_reg32 into all callers

For a 64-bit TCI, the upper bits of a 32-bit operation are undefined (much like a native ppc64 32-bit operation). It simplifies everything if we don't force-extend the result. Signed-off-by: Richard Henderson --- tcg/tci.c | 66 +-- 1 file cha

[PATCH 06/23] tcg/tci: Inline tci_write_reg32s into the only caller

Signed-off-by: Richard Henderson --- tcg/tci.c | 10 +- 1 file changed, 1 insertion(+), 9 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index 0e1b8e8383..438d712ea8 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -115,14 +115,6 @@ tci_write_reg(tcg_target_ulong *regs, TCGReg index, tcg_targ

[PATCH 13/23] tcg/tci: Merge INDEX_op_ld16u_{i32,i64}

Eliminating a TODO for ld16u_i32. Signed-off-by: Richard Henderson --- tcg/tci.c | 12 +--- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index 7d11982eb2..d197803dca 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -585,7 +585,11 @@ uintptr_t QEMU_DISABLE_

[PATCH 08/23] tcg/tci: Inline tci_write_reg16 into the only caller

Signed-off-by: Richard Henderson --- tcg/tci.c | 8 +--- 1 file changed, 1 insertion(+), 7 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index 7797558b2a..0b27f26cfb 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -115,12 +115,6 @@ tci_write_reg(tcg_target_ulong *regs, TCGReg index, tcg_target_

[PATCH 21/23] tcg/tci: Remove dead code for TCG_TARGET_HAS_div2_*

We do not simultaneously support div and div2 -- it's one or the other. TCI is already using div, so remove div2. Signed-off-by: Richard Henderson --- tcg/tci.c| 12 tcg/tci/tcg-target.c.inc | 16 2 files changed, 28 deletions(-) diff --git a/tcg/t

[PATCH 22/23] tcg/tci: Implement 64-bit division

Trivially implemented like other arithmetic. Tested via check-tcg and the ppc64 target. Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.h | 4 ++-- tcg/tci.c| 28 ++-- tcg/tci/tcg-target.c.inc | 12 3 files changed, 28 insertions(

[PATCH 10/23] tcg/tci: Inline tci_write_reg64 into 64-bit callers

Note that we had two functions of the same name: a 32-bit version which took two register numbers and a 64-bit version which was a no-op wrapper for tcg_write_reg. After this, we are left with only the 32-bit version. Signed-off-by: Richard Henderson --- tcg/tci.c | 60 +

[PATCH 23/23] tcg/tci: Remove TODO as unused

Signed-off-by: Richard Henderson --- tcg/tci.c | 8 1 file changed, 8 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index 0065c854a4..efc0ca20a6 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -33,14 +33,6 @@ #include "tcg/tcg-op.h" #include "qemu/compiler.h" -/* Marker for missing code

[PATCH 12/23] tcg/tci: Merge INDEX_op_ld8s_{i32,i64}

Eliminating a TODO for ld8s_i32. Signed-off-by: Richard Henderson --- tcg/tci.c | 12 +--- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index 019035d52f..7d11982eb2 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -578,7 +578,11 @@ uintptr_t QEMU_DISABLE_C

Re: [PATCH] hw/arm/smmuv3: Fix addr_mask for range-based invalidation

Hi Zenghui, On 12/25/20 10:50 AM, Zenghui Yu wrote: > When performing range-based IOTLB invalidation, we should decode the TG > field into the corresponding translation granule size so that we can pass > the correct invalidation range to backend. Set @granule to (tg * 2 + 10) to > properly emulate

[PATCH 14/23] tcg/tci: Merge INDEX_op_ld16s_{i32,i64}

Eliminating a TODO for ld16s_i64. Signed-off-by: Richard Henderson --- tcg/tci.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index d197803dca..95625701bb 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -592,6 +592,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qem

Re: [PATCH] target/i386: Fix decoding of certain BMI instructions

On 27/01/21 23:54, David Greenaway wrote: On 14 Jan 2021, David Greenaway wrote: This patch fixes a translation bug for a subset of x86 BMI instructions such as the following: [...] Gentle ping. The patch is up at: https://patchwork.kernel.org/project/qemu-devel/patch/20210114063958.1508050

[PATCH 15/23] tcg/tci: Merge INDEX_op_{ld_i32,ld32u_i64}

Signed-off-by: Richard Henderson --- tcg/tci.c | 7 +-- 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index 95625701bb..233fc0604e 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -599,6 +599,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,

[PATCH 17/23] tcg/tci: Merge INDEX_op_st16_{i32,i64}

Signed-off-by: Richard Henderson --- tcg/tci.c | 7 +-- 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index 0978a5c554..67875636a5 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -613,6 +613,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,

[PATCH 18/23] tcg/tci: Move stack bounds check to compile-time

The existing check was incomplete: (1) Only applied to two of the 7 stores, and not to the loads at all. (2) Only checked the upper, but not the lower bound of the stack. Doing this at compile time means that we don't need to do it at runtime as well. Signed-off-by: Richard Henderson --- tcg/tc

[PATCH 20/23] tcg/tci: Use g_assert_not_reached

Three TODO instances are never happen cases. Other uses of tcg_abort are also indicating unreachable cases. Signed-off-by: Richard Henderson --- tcg/tci.c | 15 +++ 1 file changed, 7 insertions(+), 8 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index 66b90f8489..2ce67a8fd3 100644

Re: qemu user mode fails to run programs with large VM / built with address sanitizer (was: Re: [PATCH v4 4/4] meson: Warn when TCI is selected but TCG backend is available)

On 1/27/21 8:51 PM, Stefan Weil wrote: > The problem occurred with a locally built tesseract, but I now found that it > is > more general. > > Any program which was compiled with address sanitizer uses huge virtual memory > (TB) right at the start. QEMU user mode tries to allocate that memory unt

Re: [PATCH v3 18/21] linux-user/aarch64: Signal SEGV_MTEAERR for async tag check error

On 1/22/21 3:59 AM, Peter Maydell wrote: > On Fri, 15 Jan 2021 at 22:47, Richard Henderson > wrote: >> >> Signed-off-by: Richard Henderson > > So when does the real kernel report async MTE exceptions to userspace? > The commit message would be a good place to briefly describe the > kernel's stra

[PATCH v14 00/22] i386 cleanup PART 2

A gentle ping on this series, and while we are at it, rebased again due to conflicting changes. v13 -> v14: rebased on latest master. v12 -> v13: rebased on latest master. v11 -> v12: reordered patches and improved tcg_ops * reordered all TcgCpuOperations stuff so it is at the beginning * adde

[PATCH v14 02/22] target/riscv: remove CONFIG_TCG, as it is always TCG

for now only TCG is allowed as an accelerator for riscv, so remove the CONFIG_TCG use. Signed-off-by: Claudio Fontana Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 567f6790

[PATCH v14 04/22] cpu: Move synchronize_from_tb() to tcg_ops

From: Eduardo Habkost Signed-off-by: Eduardo Habkost [claudio: wrapped in CONFIG_TCG] Signed-off-by: Claudio Fontana --- include/hw/core/cpu.h | 20 +++- accel/tcg/cpu-exec.c | 4 ++-- target/arm/cpu.c | 4 +++- target/avr/cpu.c | 2 +- target/hpp

[PATCH v14 05/22] cpu: Move cpu_exec_* to tcg_ops

From: Eduardo Habkost Signed-off-by: Eduardo Habkost [claudio: wrapped in CONFIG_TCG] Signed-off-by: Claudio Fontana Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alex Bennée Reviewed-by: Richard Henderson --- include/hw/core/cpu.h | 12 ++-- accel/tcg/cpu-exec.c

[PATCH v14 03/22] accel/tcg: split TCG-only code from cpu_exec_realizefn

move away TCG-only code, make it compile only on TCG. Signed-off-by: Claudio Fontana Reviewed-by: Alex Bennée Reviewed-by: Richard Henderson [claudio: moved the prototypes from hw/core/cpu.h to exec/cpu-all.h] --- include/exec/cpu-all.h | 11 +-- include/hw/core/cpu.h | 2 ++ accel/tcg/

[PATCH v14 07/22] cpu: Move debug_excp_handler to tcg_ops

From: Eduardo Habkost Signed-off-by: Eduardo Habkost Signed-off-by: Claudio Fontana Reviewed-by: Alex Bennée Reviewed-by: Richard Henderson --- include/hw/core/cpu.h | 4 ++-- accel/tcg/cpu-exec.c | 4 ++-- target/arm/cpu.c | 2 +- target/i386/tcg/tcg-cpu.c | 2 +- target/l

[PATCH v14 13/22] cpu: move adjust_watchpoint_address to tcg_ops

commit 40612000599e ("arm: Correctly handle watchpoints for BE32 CPUs") introduced this ARM-specific, TCG-specific hack to adjust the address, before checking it with cpu_check_watchpoint. Make adjust_watchpoint_address optional and move it to tcg_ops. Signed-off-by: Claudio Fontana --- includ

[PATCH v14 10/22] cpu: move cc->transaction_failed to tcg_ops

Signed-off-by: Claudio Fontana Reviewed-by: Alex Bennée Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson [claudio: replaced !CONFIG_USER_ONLY with CONFIG_SOFTMMU in cpu.h] this is working around a dangerous issue of different parts of the code seeing the struct TcgCpuOperati

[PATCH v14 18/22] accel: introduce AccelCPUClass extending CPUClass

add a new optional interface to CPUClass, which allows accelerators to extend the CPUClass with additional accelerator-specific initializations. Add the field before tcg_ops, and mark tcg_ops as needing to be last in the struct until we rework this further in a later patch. Signed-off-by: Claudio

[PATCH v14 08/22] target/arm: do not use cc->do_interrupt for KVM directly

cc->do_interrupt is in theory a TCG callback used in accel/tcg only, to prepare the emulated architecture to take an interrupt as defined in the hardware specifications, but in reality the _do_interrupt style of functions in targets are also occasionally reused by KVM to prepare the architecture s

[PATCH v14 06/22] cpu: Move tlb_fill to tcg_ops

From: Eduardo Habkost Signed-off-by: Eduardo Habkost [claudio: wrapped in CONFIG_TCG] Signed-off-by: Claudio Fontana Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alex Bennée Reviewed-by: Richard Henderson --- include/hw/core/cpu.h | 21 - accel/tcg/cputlb.c

[PATCH v14 11/22] cpu: move do_unaligned_access to tcg_ops

make it consistently SOFTMMU-only. Signed-off-by: Claudio Fontana Reviewed-by: Alex Bennée Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- include/hw/core/cpu.h | 22 +- target/alpha/cpu.c | 2 +- target/arm/cpu.c

[PATCH v14 01/22] cpu: Introduce TCGCpuOperations struct

From: Eduardo Habkost The TCG-specific CPU methods will be moved to a separate struct, to make it easier to move accel-specific code outside generic CPU code in the future. Start by moving tcg_initialize(). The new CPUClass.tcg_opts field may eventually become a pointer, but keep it an embedded

[PATCH v14 12/22] physmem: make watchpoint checking code TCG-only

cpu_check_watchpoint, watchpoint_address_matches are TCG-only. Signed-off-by: Claudio Fontana --- softmmu/physmem.c | 141 +++--- 1 file changed, 72 insertions(+), 69 deletions(-) diff --git a/softmmu/physmem.c b/softmmu/physmem.c index cdcd197656..ef94e3

[PATCH v14 09/22] cpu: move cc->do_interrupt to tcg_ops

Signed-off-by: Claudio Fontana Reviewed-by: Alex Bennée Reviewed-by: Richard Henderson --- include/hw/core/cpu.h | 4 ++-- accel/tcg/cpu-exec.c| 4 ++-- target/alpha/cpu.c | 2 +- target/arm/cpu.c| 4 ++-- target/arm/cpu_tcg.c|

[PATCH v14 22/22] accel: introduce new accessor functions

avoid open coding the accesses to cpu->accel_cpu interfaces, and instead introduce: accel_cpu_instance_init, accel_cpu_realizefn to be used by the targets/ initfn code, and by cpu_exec_realizefn respectively. Add warnings about the use of target-specific headers. Signed-off-by: Claudio Fontana

Re: [PATCH v2 15/36] block: use topological sort for permission update

27.01.2021 21:38, Kevin Wolf wrote: Am 27.11.2020 um 15:45 hat Vladimir Sementsov-Ogievskiy geschrieben: Rewrite bdrv_check_perm(), bdrv_abort_perm_update() and bdrv_set_perm() to update nodes in topological sort order instead of simple DFS. With topologically sorted nodes, we update a node only

[PATCH v14 16/22] accel: extend AccelState and AccelClass to user-mode

Signed-off-by: Claudio Fontana Reviewed-by: Alex Bennée [claudio: rebased on Richard's splitwx work] Signed-off-by: Claudio Fontana --- include/hw/boards.h| 2 +- include/{sysemu => qemu}/accel.h | 14 + include/sysemu/hvf.h | 2 +- include/sysemu/kvm.

[PATCH v14 14/22] cpu: move debug_check_watchpoint to tcg_ops

commit 568496c0c0f1 ("cpu: Add callback to check architectural") and commit 3826121d9298 ("target-arm: Implement checking of fired") introduced an ARM-specific hack for cpu_check_watchpoint. Make debug_check_watchpoint optional, and move it to tcg_ops. Signed-off-by: Claudio Fontana --- include

Re: [PATCH] vhost-user: Check for iotlb callback in iotlb_miss

Hi Jason. On Thu, Jan 28, 2021 at 3:32 AM Jason Wang wrote: > > > On 2021/1/28 上午4:44, Eugenio Pérez wrote: > > Not registering this can lead to vhost_backend_handle_iotlb_msg and > > vhost_device_iotlb_miss if backend issue a miss after qemu vhost device > > stop. > > > > This causes a try to ac

[PATCH v14 21/22] hw/core/cpu: call qemu_init_vcpu in cpu_common_realizefn

move the call to qemu_init_vcpu inside cpu_common_realizefn, so it does not need to be done explicitly in each target cpu. Despite this, the way cpu realize is done continues to be not ideal; ideally the cpu_list_add would be done in common_cpu, and in this case we could avoid even more redundant

[PATCH v14 20/22] cpu: call AccelCPUClass::cpu_realizefn in cpu_exec_realizefn

move the call to accel_cpu->cpu_realizefn to the general cpu_exec_realizefn from target/i386, so it does not need to be called for every target explicitly as we enable more targets. Signed-off-by: Claudio Fontana --- cpu.c | 6 ++ target/i386/cpu.c | 20 +++- 2 f

[PATCH v14 15/22] cpu: tcg_ops: move to tcg-cpu-ops.h, keep a pointer in CPUClass

this improves over the workaround in commit ("cpu: move cc->transaction_failed to tcg_ops") by moving the tcg cpu operations into a separate file, which is only included by target-specific code. The context is that code in ss_common and ss_specific modules might see different data structure layou

[PATCH v14 17/22] accel: replace struct CpusAccel with AccelOpsClass

also centralize the registration of the cpus.c module accelerator operations in accel/accel-softmmu.c Consequently, rename all tcg-cpus.c, kvm-cpus.c etc to tcg-accel-ops.c, kvm-accel-ops.c etc, also matching the object type names. Signed-off-by: Claudio Fontana --- accel/accel-softmmu.h

Re: acceptance-system-fedora and acceptance-system-centos failing sporadically with timeout?

On 28/01/21 10:45, Claudio Fontana wrote: Hi, is it just me, or is the CI sometimes failing with timeout? One nice feature that cirrus and travis have is the ability to relaunch one specific test, do you know if there is some way to do it in gitlab too? I could not find it.. Fedora: https://

[PATCH v14 19/22] i386: split cpu accelerators from cpu.c, using AccelCPUClass

i386 is the first user of AccelCPUClass, allowing to split cpu.c into: cpu.ccpuid and common x86 cpu functionality host-cpu.c host x86 cpu functions and "host" cpu type kvm/kvm-cpu.cKVM x86 AccelCPUClass hvf/hvf-cpu.cHVF x86 AccelCPUClass tcg/tcg-cpu.cTCG x86 AccelCPU

acceptance-system-fedora and acceptance-system-centos failing sporadically with timeout?

Hi, is it just me, or is the CI sometimes failing with timeout? One nice feature that cirrus and travis have is the ability to relaunch one specific test, do you know if there is some way to do it in gitlab too? I could not find it.. Fedora: https://gitlab.com/hw-claudio/qemu/-/jobs/986936506

RE: [PATCH v20 01/20] multi-process: add the concept description to docs/devel/qemu-multiprocess

> > I understand that this framework is targetting KVM and mostly PCI > > devices but I was wondering if it could be of any use for full system > > emulation. Would it possible to use this framework to interconnect > > QEMU processes emulating different machines but sharing a common bus > ? Not su

Re: acceptance-system-fedora and acceptance-system-centos failing sporadically with timeout?

On 1/28/21 10:50 AM, Paolo Bonzini wrote: > On 28/01/21 10:45, Claudio Fontana wrote: >> Hi, >> >> is it just me, or is the CI sometimes failing with timeout? >> >> One nice feature that cirrus and travis have is the ability to relaunch one >> specific test, >> do you know if there is some way to

[Bug 1898011] Re: mmap MAP_NORESERVE of 2^42 bytes consumes 16Gb of actual RAM

The problem occurs for example with any program which was compiled with the address sanitizer. A simple hello program compiled with "gcc -fsanitize=address hello.c" is sufficient to show the problem. Just run it with "qemu-x86_64 a.out". It will be killed by the Linux kernel OOM handler even on a

Re: [PATCH 22/23] tcg/tci: Implement 64-bit division

Am 28.01.21 um 09:23 schrieb Richard Henderson: Trivially implemented like other arithmetic. Tested via check-tcg and the ppc64 target. Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.h | 4 ++-- tcg/tci.c| 28 ++-- tcg/tci/tcg-target.c.

Re: [PATCH 20/23] tcg/tci: Use g_assert_not_reached

Am 28.01.21 um 09:23 schrieb Richard Henderson: Three TODO instances are never happen cases. Other uses of tcg_abort are also indicating unreachable cases. Signed-off-by: Richard Henderson --- tcg/tci.c | 15 +++ 1 file changed, 7 insertions(+), 8 deletions(-) Reviewed-by: St

Re: [PATCH 5/7] ppc/pnv: Discard internal BMC initialization when BMC is external

On Thu, 28 Jan 2021 at 07:13, Cédric Le Goater wrote: > > On 1/28/21 1:48 AM, Joel Stanley wrote: > > On Tue, 26 Jan 2021 at 17:11, Cédric Le Goater wrote: > >> > >> The PowerNV machine can be run with an external IPMI BMC device > >> connected to a remote QEMU machine acting as BMC, using these

Re: [PATCH 2/5] libqos/qgraph_internal: add qos_printf() and qos_printf_literal()

On 27/01/2021 00.04, Christian Schoenebeck wrote: These two are macros wrapping regular printf() call. They are intended to be used instead of calling printf() directly in order to avoid breaking TAP output format. TAP output format is enabled by using --tap command line argument. Starting with

Re: acceptance-system-fedora and acceptance-system-centos failing sporadically with timeout?

On 28/01/2021 10.45, Claudio Fontana wrote: Hi, is it just me, or is the CI sometimes failing with timeout? One nice feature that cirrus and travis have is the ability to relaunch one specific test, do you know if there is some way to do it in gitlab too? I could not find it.. Fedora: https:

[Bug 1898011] Re: mmap MAP_NORESERVE of 2^42 bytes consumes 16Gb of actual RAM

** Tags added: linux-user mmap tcg -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1898011 Title: mmap MAP_NORESERVE of 2^42 bytes consumes 16Gb of actual RAM Status in QEMU: Confirmed Bug descri

Re: acceptance-system-fedora and acceptance-system-centos failing sporadically with timeout?

On 1/28/21 11:10 AM, Thomas Huth wrote: > On 28/01/2021 10.45, Claudio Fontana wrote: >> Hi, >> >> is it just me, or is the CI sometimes failing with timeout? >> >> One nice feature that cirrus and travis have is the ability to relaunch one >> specific test, >> do you know if there is some way to

RE: [PATCH v4] blockjob: Fix crash with IOthread when block commit after snapshot

Any comments? -Original Message- From: 08005...@163.com <08005...@163.com> Sent: 2021年1月28日 9:31 To: kw...@redhat.com; mre...@redhat.com; js...@redhat.com Cc: qemu-bl...@nongnu.org; qemu-devel@nongnu.org; 仇大玉 Subject: [PATCH v4] blockjob: Fix crash with IOthread when block commit after

Re: [RFC PATCH v2 24/32] hw/cxl/device: Add a memory device (8.2.8.5)

On Wed, 27 Jan 2021 13:26:45 -0800 Ben Widawsky wrote: > On 21-01-27 22:03:12, Igor Mammedov wrote: > > On Tue, 5 Jan 2021 08:53:15 -0800 > > Ben Widawsky wrote: > > > > > A CXL memory device (AKA Type 3) is a CXL component that contains some > > > combination of volatile and persistent memo

[Bug 1913505] Re: Windows XP slow on Apple M1

Is the install that slow on some other hardware (useful comparisons: x86 Mac; x86 Linux; AArch64 Linux) ? -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1913505 Title: Windows XP slow on Apple M1 S

Re: [PATCH v3 18/21] linux-user/aarch64: Signal SEGV_MTEAERR for async tag check error

On Thu, 28 Jan 2021 at 08:49, Richard Henderson wrote: > > On 1/22/21 3:59 AM, Peter Maydell wrote: > > Does it work if we just always queue the SEGV on exit from cpu_exec() > > and let the signal handling machinery prioritize if we also pend > > some other signal because this was an EXCP_UDEF or

Re: [PULL 0/9] Gitlab-CI and testing improvements

On Wed, 27 Jan 2021 at 09:54, Thomas Huth wrote: > > Hi Peter, > > the following changes since commit 9cd69f1a270235b652766f00b94114f48a2d603f: > > Merge remote-tracking branch > 'remotes/stefanberger/tags/pull-tpm-2021-01-25-1' into staging (2021-01-26 > 09:51:02 +) > > are available in

Re: [Bug 1913505] Re: Windows XP slow on Apple M1

On 28/01/2021 10:33, Peter Maydell wrote: Is the install that slow on some other hardware (useful comparisons: x86 Mac; x86 Linux; AArch64 Linux) ? Could it be related to excess TLB flushing? Possible related bug report here: https://bugs.launchpad.net/qemu/+bug/1883593. ATB, Mark.

Re: [RFC] Set addresses for memory devices [CXL]

On Wed, 27 Jan 2021 21:20:21 -0800 Dan Williams wrote: > On Wed, Jan 27, 2021 at 7:52 PM Ben Widawsky wrote: > > > > Hi list, Igor. > > > > I wanted to get some ideas on how to better handle this. Per the recent > > discussion [1], it's become clear that there needs to be more thought put > > i

Re: [PATCH 3/6] qapi: Simplify full_name_nth() in qobject-input-visitor

Am 28.01.2021 um 08:43 hat Markus Armbruster geschrieben: > Kevin Wolf writes: > > > Am 27.01.2021 um 14:56 hat Markus Armbruster geschrieben: > >> Kevin Wolf writes: > >> > >> > Instead of counting how many elements from the top of the stack we need > >> > to ignore until we find the thing we'

Re: [PATCH v4 00/12] Support disabling TCG on ARM (part 2)

Hi Alex, On 1/28/21 1:41 AM, Alex Bennée wrote: > Philippe Mathieu-Daudé writes: > >> Cover from Samuel Ortiz from (part 1) [1]: >> >> This patchset allows for building and running ARM targets with TCG >> disabled. [...] >> >> The rationale behind this work comes from the NEMU project wher

Re: [PATCH] ui: fix spice display regression

Hi On Wed, Jan 27, 2021 at 2:54 PM Paolo Bonzini wrote: > > On 27/01/21 11:18, Marc-André Lureau wrote: > > Hi > > > > On Wed, Jan 27, 2021 at 2:03 PM wrote: > >> > >> From: Marc-André Lureau > >> > >> Since commit b4e1a342112e50e05b609e857f38c1f2b7aafdc4 ("vl: remove > >> separate preconfig ma

[PATCH] spice: delay starting until display are initialized

From: Marc-André Lureau QEMU used to run qemu_spice.display_init() before vm_start(), and QXL/display interfaces where started then. Now, vm_start() happens before QXL/display interfaces are added and Spice server doesn't automatically start them in this case (fixed in spice git) Fixes Spice reg

Re: Fwd: VirtioSound device emulation implementation

Shreyansh Chouhan writes: > Thanks a lot Alex! > >> All QEMU devices have two parts, a frontend (which the guest sees) and a >> backend (which is how the data gets to somewhere in the host). Some of >> the command line options in QEMU elide the details for convenience (-nic >> and -drive are ex

Re: Fwd: VirtioSound device emulation implementation

On Thu, Jan 28, 2021 at 09:58:23AM +0530, Shreyansh Chouhan wrote: > Thanks a lot Alex! > > > All QEMU devices have two parts, a frontend (which the guest sees) and a > > backend (which is how the data gets to somewhere in the host). Some of > > the command line options in QEMU elide the details f

[PATCH v2 00/25] Convert CMSDK timer, watchdog, dualtimer to Clock framework

This patchset converts the CMSDK timer, watchdog and dualtimer devices to use the Clock framework instead of an integer property specifying a frequency in Hz. The series is quito a lot of patches but they should be mostly small and I hope easy to review. The motivation here is the upcoming Arm SSE

[PATCH v2 03/25] tests: Add a simple test of the CMSDK APB timer

Add a simple test of the CMSDK APB timer, since we're about to do some refactoring of how it is clocked. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Luc Michel Message-id: 20210121190622.22000-4-peter.mayd...@linaro.org --- v1->v2 changes: - phrase various clo

[PATCH v2 12/25] hw/arm/mps2: Inline CMSDK_APB_TIMER creation

The old-style convenience function cmsdk_apb_timer_create() for creating CMSDK_APB_TIMER objects is used in only two places in mps2.c. Most of the rest of the code in that file uses the new "initialize in place" coding style. We want to connect up a Clock object which should be done between the o

[PATCH v2 05/25] tests: Add a simple test of the CMSDK APB dual timer

Add a simple test of the CMSDK dual timer, since we're about to do some refactoring of how it is clocked. Signed-off-by: Peter Maydell Message-id: 20210121190622.22000-6-peter.mayd...@linaro.org --- v1->v2 changes: - phrase various clock_step() arguments as calculations based on tick counts a

[PATCH v2 08/25] hw/timer/cmsdk-apb-dualtimer: Add Clock input

As the first step in converting the CMSDK_APB_DUALTIMER device to the Clock framework, add a Clock input. For the moment we do nothing with this clock; we will change the behaviour from using the pclk-frq property to using the Clock once all the users of this device have been converted to wire up

[PATCH v2 02/25] clock: Add new clock_has_source() function

Add a function for checking whether a clock has a source. This is useful for devices which have input clocks that must be wired up by the board as it allows them to fail in realize rather than ploughing on with a zero-period clock. Signed-off-by: Peter Maydell Reviewed-by: Luc Michel Reviewed-b

[PATCH v2 11/25] hw/arm/armsse: Wire up clocks

Create two input clocks on the ARMSSE devices, one for the normal MAINCLK, and one for the 32KHz S32KCLK, and wire these up to the appropriate devices. The old property-based clock frequency setting will remain in place until conversion is complete. This is a migration compatibility break for mac

[PATCH v2 16/25] hw/arm/stellaris: Convert SSYS to QOM device

Convert the SSYS code in the Stellaris boards (which encapsulates the system registers) to a proper QOM device. This will provide us with somewhere to put the output Clock whose frequency depends on the setting of the PLL configuration registers. This is a migration compatibility break for lm3s81

[PATCH v2 09/25] hw/watchdog/cmsdk-apb-watchdog: Add Clock input

As the first step in converting the CMSDK_APB_TIMER device to the Clock framework, add a Clock input. For the moment we do nothing with this clock; we will change the behaviour from using the wdogclk-frq property to using the Clock once all the users of this device have been converted to wire up t

[PATCH v2 01/25] ptimer: Add new ptimer_set_period_from_clock() function

The ptimer API currently provides two methods for setting the period: ptimer_set_period(), which takes a period in nanoseconds, and ptimer_set_freq(), which takes a frequency in Hz. Neither of these lines up nicely with the Clock API, because although both the Clock and the ptimer track the freque

[PATCH v2 18/25] hw/timer/cmsdk-apb-timer: Convert to use Clock input

Switch the CMSDK APB timer device over to using its Clock input; the pclk-frq property is now ignored. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Luc Michel Message-id: 20210121190622.22000-19-peter.mayd...@linaro.org --- hw/timer/cmsdk-apb-timer.c | 18 +

[PATCH v2 04/25] tests: Add a simple test of the CMSDK APB watchdog

Add a simple test of the CMSDK watchdog, since we're about to do some refactoring of how it is clocked. Signed-off-by: Peter Maydell Reviewed-by: Luc Michel Message-id: 20210121190622.22000-5-peter.mayd...@linaro.org Reviewed-by: Philippe Mathieu-Daudé --- v1->v2 changes: - remove set-but-not-

[PATCH v2 14/25] hw/arm/mps2-tz: Create and connect ARMSSE Clocks

Create and connect the two clocks needed by the ARMSSE. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Luc Michel Message-id: 20210121190622.22000-15-peter.mayd...@linaro.org --- hw/arm/mps2-tz.c | 13 + 1 file changed, 13 insertions(+) diff --git a/

[PATCH v2 25/25] hw/arm/stellaris: Remove board-creation reset of STELLARIS_SYS

Now that the watchdog device uses its Clock input rather than being passed the value of system_clock_scale at creation time, we can remove the hack where we reset the STELLARIS_SYS at board creation time to force it to set system_clock_scale. Instead it will be reset at the usual point in startup

[PATCH v2 06/25] hw/timer/cmsdk-apb-timer: Rename CMSDKAPBTIMER struct to CMSDKAPBTimer

The state struct for the CMSDK APB timer device doesn't follow our usual naming convention of camelcase -- "CMSDK" and "APB" are both acronyms, but "TIMER" is not so should not be all-uppercase. Globally rename the struct to "CMSDKAPBTimer" (bringing it into line with CMSDKAPBWatchdog and CMSDKAPBD

[PATCH v2 15/25] hw/arm/musca: Create and connect ARMSSE Clocks

Create and connect the two clocks needed by the ARMSSE. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Luc Michel Message-id: 20210121190622.22000-16-peter.mayd...@linaro.org --- hw/arm/musca.c | 12 1 file changed, 12 insertions(+) diff --git a/hw/

[PATCH v2 20/25] hw/watchdog/cmsdk-apb-watchdog: Convert to use Clock input

Switch the CMSDK APB watchdog device over to using its Clock input; the wdogclk_frq property is now ignored. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Luc Michel Message-id: 20210121190622.22000-21-peter.mayd...@linaro.org --- hw/watchdog/cmsdk-apb-watchdog.

[PATCH v2 07/25] hw/timer/cmsdk-apb-timer: Add Clock input

As the first step in converting the CMSDK_APB_TIMER device to the Clock framework, add a Clock input. For the moment we do nothing with this clock; we will change the behaviour from using the pclk-frq property to using the Clock once all the users of this device have been converted to wire up the

[PATCH v2 10/25] hw/arm/armsse: Rename "MAINCLK" property to "MAINCLK_FRQ"

While we transition the ARMSSE code from integer properties specifying clock frequencies to Clock objects, we want to have the device provide both at once. We want the final name of the main input Clock to be "MAINCLK", following the hardware name. Unfortunately creating an input Clock with a name

[PATCH v2 21/25] tests/qtest/cmsdk-apb-watchdog-test: Test clock changes

Now that the CMSDK APB watchdog uses its Clock input, it will correctly respond when the system clock frequency is changed using the RCC register on in the Stellaris board system registers. Test that when the RCC register is written it causes the watchdog timer to change speed. Signed-off-by: Pet

[PATCH v2 13/25] hw/arm/mps2: Create and connect SYSCLK Clock

Create a fixed-frequency Clock object to be the SYSCLK, and wire it up to the devices that require it. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Luc Michel Message-id: 20210121190622.22000-14-peter.mayd...@linaro.org --- hw/arm/mps2.c | 9 + 1 file c

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