On 1/5/21 8:17 PM, Laurent Vivier wrote:
> The first patch fixes a problem I have introduced in vhost-vdpa
> traces by adding an unsupported format ("%llu").
>
> The second patch fixes a problem I've seen while I was checking
> the result of the first patch: %PRI formats are not decoded
> correctl
Hi,
if of interest to anyone...
we were able to successfully upgrade firmware of Intel XL710 on aarch64
platform.
Two major items were required:
- small qemu change:
https://lists.gnu.org/archive/html/qemu-devel/2021-01/msg00553.html
- hack in Linux kernel /dev/mem driver in mmap function to ca
Hi Laurent,
I know it must be more complex, but it worked for our case so I wanted
to share it anyway as we did not find support for this in latest git,
but forgot to check mailing list.
With this small patch + some others in Linux kernel we were able to
execute Intel XL710 network adapter N
Reviewed-by: Joelle van Dyne
On Tue, Jan 5, 2021 at 9:19 AM Richard Henderson
wrote:
>
> Plumb the value through to alloc_code_gen_buffer. This is not
> supported by any os or tcg backend, so for now enabling it will
> result in an error.
>
> Signed-off-by: Richard Henderson
> ---
> include/s
On Wed, Dec 30, 2020 at 12:26 AM Sylvain Pelissier
wrote:
>
> Target description is not currently implemented in RISC-V architecture. Thus
> GDB won't set it properly when attached. The patch implements the target
> description response.
>
> Signed-off-by: Sylvain Pelissier
Reviewed-by: Alista
On Mon, Jan 04, 2021 at 03:23:07PM +, Alex Bennée wrote:
>
> Roman Bolshakov writes:
>
> > Pages can't be both write and executable at the same time on Apple
> > Silicon. macOS provides public API to switch write protection [1] for
> > JIT applications, like TCG.
> >
> > 1.
> > https://deve
On Tue, Jan 05, 2021 at 11:56:14AM +0100, Halil Pasic wrote:
> On Mon, 4 Jan 2021 10:40:26 -0800
> Ram Pai wrote:
>
> > On Mon, Jan 04, 2021 at 01:46:29PM +0100, Halil Pasic wrote:
> > > On Sun, 3 Jan 2021 23:15:50 -0800
> > > Ram Pai wrote:
> > >
> > > > On Fri, Dec 18, 2020 at 12:41:11PM +0
On Mon, Jan 4, 2021 at 7:11 PM Bin Meng wrote:
>
> On Fri, Dec 18, 2020 at 5:48 AM Atish Patra wrote:
> >
> > Currently, we place the DTB at 2MB from 4GB or end of DRAM which ever is
> > lesser. However, Linux kernel can address only 1GB of memory for RV32.
> > Thus, it can not map anything beyon
On Wed, Dec 30, 2020 at 12:26 AM Sylvain Pelissier
wrote:
>
> Target description is not currently implemented in RISC-V architecture. Thus
> GDB won't set it properly when attached. The patch implements the target
> description response.
>
> Signed-off-by: Sylvain Pelissier
Hello,
This patch
On Mon, 4 Jan 2021 at 17:35, Richard Henderson
wrote:
>
> The following changes since commit 41192db338588051f21501abc13743e62b0a5605:
>
> Merge remote-tracking branch
> 'remotes/ehabkost-gl/tags/machine-next-pull-request' into staging (2021-01-01
> 22:57:15 +)
>
> are available in the Git
On Wed, Dec 16, 2020 at 2:25 AM Bin Meng wrote:
>
> Hi Alistair, Peter,
>
> On Wed, Dec 2, 2020 at 10:45 PM Bin Meng wrote:
> >
> > From: Bin Meng
> >
> > Avoid using a magic number (4) everywhere for the number of chip
> > selects supported.
> >
> > Signed-off-by: Bin Meng
> > Reviewed-by: Ali
On Tue, 5 Jan 2021 at 21:09, Alistair Francis wrote:
>
> On Wed, Dec 16, 2020 at 2:25 AM Bin Meng wrote:
> >
> > Hi Alistair, Peter,
> >
> > On Wed, Dec 2, 2020 at 10:45 PM Bin Meng wrote:
> > >
> > > From: Bin Meng
> > >
> > > Avoid using a magic number (4) everywhere for the number of chip
>
On Tue, Jan 5, 2021 at 1:08 PM Alistair Francis wrote:
>
> On Wed, Dec 16, 2020 at 2:25 AM Bin Meng wrote:
> >
> > Hi Alistair, Peter,
> >
> > On Wed, Dec 2, 2020 at 10:45 PM Bin Meng wrote:
> > >
> > > From: Bin Meng
> > >
> > > Avoid using a magic number (4) everywhere for the number of chip
On Mon, Jan 4, 2021 at 7:50 PM Bin Meng wrote:
>
> On Wed, Dec 23, 2020 at 10:00 AM Bin Meng wrote:
> >
> > From: Bin Meng
> >
> > When write is disabled, the write to flash should be avoided
> > in flash_write8().
> >
> > Fixes: 82a2499011a7 ("m25p80: Initial implementation of SPI flash device"
On Thu, Dec 31, 2020 at 3:32 AM Bin Meng wrote:
>
> From: Bin Meng
>
> This updates the flash information table to include various ISSI
> flashes that are supported by upstream U-Boot and Linux kernel.
>
> Signed-off-by: Bin Meng
Acked-by: Alistair Francis
Alistair
> ---
>
> hw/block/m25p80
On Mon, Jan 04, 2021 at 07:39:13PM +0100, Alexander Graf wrote:
>
> On 04.01.21 16:23, Alex Bennée wrote:
> > Roman Bolshakov writes:
> >
> > > Pages can't be both write and executable at the same time on Apple
> > > Silicon. macOS provides public API to switch write protection [1] for
> > > JIT
On Mon, Jan 04, 2021 at 08:28:08PM +, Alex Bennée wrote:
>
> Alexander Graf writes:
>
> > On 04.01.21 16:23, Alex Bennée wrote:
> >> Roman Bolshakov writes:
> >>
> >>> Pages can't be both write and executable at the same time on Apple
> >>> Silicon. macOS provides public API to switch write
On Mon, Jan 04, 2021 at 06:02:50PM -0800, Joelle van Dyne wrote:
> Tested-by: Joelle van Dyne
>
> It works for me. But one thing is that if you build it with the macOS
> 11.x SDK it won't run on < 11.x. This is why apple recommends
> something like:
>
> if (__builtin_available(macOS 11,
Ping?
On Wed, Dec 16, 2020 at 4:45 PM Hao Wu wrote:
> This patch series include a few more NPCM7XX devices including
>
> - Analog Digital Converter (ADC)
> - Pulse Width Modulation (PWM)
>
> We also modified the CLK module to generate clock values using qdev_clock.
> These clocks are used to det
On Fri, Dec 04, 2020 at 04:44:12PM +1100, David Gibson wrote:
> Some upcoming POWER machines have a system called PEF (Protected
> Execution Facility) which uses a small ultravisor to allow guests to
> run in a way that they can't be eavesdropped by the hypervisor. The
> effect is roughly similar
Roman Bolshakov writes:
> On Mon, Jan 04, 2021 at 03:23:07PM +, Alex Bennée wrote:
>>
>> Roman Bolshakov writes:
>>
>> > Pages can't be both write and executable at the same time on Apple
>> > Silicon. macOS provides public API to switch write protection [1] for
>> > JIT applications, li
On Tue, 2021-01-05 at 11:11 +0800, Bin Meng wrote:
> On Fri, Dec 18, 2020 at 5:48 AM Atish Patra
> wrote:
> >
> > Currently, we place the DTB at 2MB from 4GB or end of DRAM which
> > ever is
> > lesser. However, Linux kernel can address only 1GB of memory for
> > RV32.
> > Thus, it can not map an
Hi Atish,
On Wed, Jan 6, 2021 at 7:44 AM Atish Patra wrote:
>
> On Tue, 2021-01-05 at 11:11 +0800, Bin Meng wrote:
> > On Fri, Dec 18, 2020 at 5:48 AM Atish Patra
> > wrote:
> > >
> > > Currently, we place the DTB at 2MB from 4GB or end of DRAM which
> > > ever is
> > > lesser. However, Linux ke
On Wed, Jan 6, 2021 at 5:11 AM Peter Maydell wrote:
>
> On Tue, 5 Jan 2021 at 21:09, Alistair Francis wrote:
> >
> > On Wed, Dec 16, 2020 at 2:25 AM Bin Meng wrote:
> > >
> > > Hi Alistair, Peter,
> > >
> > > On Wed, Dec 2, 2020 at 10:45 PM Bin Meng wrote:
> > > >
> > > > From: Bin Meng
> > >
Does the spice protocol / any spice client allow access to compatmonitor
/ serial /paralel?
Spice can be (if not often / mainly) used for remote access like VNC,
but that does not necessarily mean users would want to host "fully-
headless".
--
You received this bug notification because you are a
On Wed, 2021-01-06 at 08:04 +0800, Bin Meng wrote:
> Hi Atish,
>
> On Wed, Jan 6, 2021 at 7:44 AM Atish Patra
> wrote:
> >
> > On Tue, 2021-01-05 at 11:11 +0800, Bin Meng wrote:
> > > On Fri, Dec 18, 2020 at 5:48 AM Atish Patra
> > > wrote:
> > > >
> > > > Currently, we place the DTB at 2MB fr
The following changes since commit 52d25464605dc20022ad94aa8bc8e8473e600833:
Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20210104' into
staging (2021-01-05 16:18:20 +)
are available in the Git repository at:
https://gitlab.com/dgibson/qemu.git tags/ppc-for-6.0-2021010
From: Peter Maydell
Switch the bamboo board to directly creating and configuring the UIC,
rather than doing it via the old ppcuic_init() helper function.
Signed-off-by: Peter Maydell
Message-Id: <20201212001537.24520-5-peter.mayd...@linaro.org>
Signed-off-by: David Gibson
---
hw/ppc/ppc440_ba
From: Peter Maydell
Switch the virtex_ml507 board to directly creating and
configuring the UIC, rather than doing it via the old
ppcuic_init() helper function.
This fixes a trivial Coverity-detected memory leak where
we were leaking the array of IRQs returned by ppcuic_init().
Fixes: Coverity C
From: Peter Maydell
Currently the PPC UIC ("Universal Interrupt Controller") is implemented
as a non-QOM device in ppc4xx_devs.c. Convert it to a proper QOM device
in hw/intc.
The ppcuic_init() function is retained for the moment with its current
interface; in subsequent commits this will be tid
From: Peter Maydell
In a following commit we will move the PPC UIC implementation to
its own file in hw/intc. To prevent checkpatch complaining about that
code-motion, fix up the minor style issues first.
Signed-off-by: Peter Maydell
Message-Id: <20201212001537.24520-2-peter.mayd...@linaro.org>
From: Greg Kurz
Running a guest with 128 NUMA nodes crashes QEMU:
../../util/error.c:59: error_setv: Assertion `*errp == NULL' failed.
The crash happens when setting the FWNMI migration blocker:
2861if (spapr_get_cap(spapr, SPAPR_CAP_FWNMI) == SPAPR_CAP_ON) {
2862/* Create
From: Cédric Le Goater
Signed-off-by: Cédric Le Goater
Message-Id: <20201215174025.2636824-1-...@kaod.org>
Signed-off-by: David Gibson
---
hw/intc/spapr_xive.c| 2 +-
include/hw/ppc/spapr_xive.h | 2 --
2 files changed, 1 insertion(+), 3 deletions(-)
diff --git a/hw/intc/spapr_xive.c
From: Greg Kurz
Section 13.5.2 of LoPAPR mandates various DR related indentifiers
for all hot-pluggable entities to be exposed in the "ibm,drc-indexes",
"ibm,drc-power-domains", "ibm,drc-names" and "ibm,drc-types" properties
of their parent node. These properties are created with spapr_dt_drc().
From: Greg Kurz
Non-transient DRCs are either in the empty or the ready state,
which means spapr_drc_reset() doesn't change their state. It
is thus not needed to do any checking. Call spapr_drc_reset()
unconditionally and squash spapr_drc_transient() into its
only user, spapr_drc_needed().
Signe
From: Greg Kurz
Use a less generic name for an easier experience with tools such as
cscope or grep.
Signed-off-by: Greg Kurz
Message-Id: <20201218103400.689660-6-gr...@kaod.org>
Reviewed-by: Daniel Henrique Barboza
Tested-by: Daniel Henrique Barboza
Signed-off-by: David Gibson
---
hw/ppc/sp
From: Greg Kurz
No need to expose the way DRCs are traversed outside of spapr_drc.c.
Signed-off-by: Greg Kurz
Message-Id: <20201218103400.689660-4-gr...@kaod.org>
Reviewed-by: Daniel Henrique Barboza
Tested-by: Daniel Henrique Barboza
Signed-off-by: David Gibson
---
hw/ppc/spapr_drc.c
From: Greg Kurz
It is currently impossible to hot-unplug a memory device between
machine reset and CAS.
(qemu) device_del dimm1
Error: Memory hot unplug not supported for this guest
This limitation was introduced in order to provide an explicit
error path for older guests that didn't support ho
From: Greg Kurz
qemu-system-ppc64 built with --without-default-devices crashes:
Type 'pnv-phb4-root-port' is missing its parent 'pcie-root-port-base'
Aborted (core dumped)
Have POWERNV to select PCIE_PORT. This is done through a
new PCI_POWERNV config in hw/pci-host/Kconfig since POWERNV
doesn'
From: Greg Kurz
All memory DRC objects are created during machine init. It is thus safe
to assume spapr_drc_by_id() cannot return NULL when hot-plug/unplugging
memory.
Make this clear with an assertion, like the code already does a few lines
above when looping over memory DRCs. This fixes Coveri
From: BALATON Zoltan via
Dependency on FDT_PPC was added in commit b0048f76095
("hw/ppc/Kconfig: Only select FDT helper for machines using it") but
it does not seem to be really necessary so remove it again.
Signed-off-by: BALATON Zoltan
Reviewed-by: Philippe Mathieu-Daudé
Message-Id:
<7461a2
From: Greg Kurz
Documentation of object_property_iter_init() clearly stipulates that
"it is forbidden to modify the property list while iterating". But this
is exactly what we do when resetting transient DR connectors during CAS.
The call to spapr_drc_reset() can finalize the hot-unplug sequence
From: Greg Kurz
Linking of the qemu-system-ppc64 fails on a POWER9 host when
--without-default-devices is passed to configure:
$ ./configure --without-default-devices \
--target-list=ppc64-softmmu && make
...
libqemu-ppc64-softmmu.fa.p/hw_ppc_e500.c.o: In function `ppce500_init_m
From: Greg Kurz
Documentation of object_child_foreach_recursive() clearly stipulates
that "it is forbidden to add or remove children from @obj from the @fn
callback". But this is exactly what we do during machine reset. The call
to spapr_drc_reset() can finalize the hot-unplug sequence of a PHB o
From: BALATON Zoltan via
All machines that select SERIAL also select PPC4XX so we can just add
this common dependency there once.
Signed-off-by: BALATON Zoltan
Message-Id:
<94f1eb7cfb7f315bd883d825f3ce7e0cfc2f2b69.1609636173.git.bala...@eik.bme.hu>
Signed-off-by: David Gibson
---
hw/ppc/Kcon
From: Greg Kurz
Have PSERIES to select XICS and XIVE, and directly check PSERIES
in hw/intc/meson.build to enable build of the XICS and XIVE sPAPR
backends, like POWERNV already does. This allows to get rid of the
intermediate XICS_SPAPR and XIVE_SPAPR.
Signed-off-by: Greg Kurz
Message-Id: <160
From: BALATON Zoltan via
The trace event for pci_host_config_write() was also using the trace
event for read. Add corresponding trace and correct this.
Signed-off-by: BALATON Zoltan
Message-Id:
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: David Gibson
---
hw/ppc/ppc440_pcix.c | 2 +-
From: BALATON Zoltan via
The code mapping all PCI interrupts to a single CPU IRQ works but is
not trivial so document it in a comment.
Signed-off-by: BALATON Zoltan
Message-Id:
Reviewed-by: Peter Maydell
Signed-off-by: David Gibson
---
hw/ppc/ppc440_pcix.c | 11 +--
1 file changed,
From: BALATON Zoltan via
This fixes a long standing issue with MorphOS booting on sam460ex
which turns out to be because of suspicious values written to PCI
config address that apparently works on real machine but caused wrong
access on this device model. This replaces a previous work around for
在 2021/1/5 下午6:05, Philippe Mathieu-Daudé 写道:
Hi Richard,
On 1/5/21 9:34 AM, Philippe Mathieu-Daudé wrote:
On 1/5/21 12:30 AM, Richard Henderson wrote:
On 1/4/21 12:11 PM, Philippe Mathieu-Daudé wrote:
MIPS 64-bit ISA is introduced with MIPS3.
Introduce the CPU_MIPS64 definition aliased to t
When the length of mname is less than 5, memcpy("xenfv", mname, 5) will cause
heap buffer overflow. Therefore, use strncmp to avoid this problem.
The asan showed stack:
ERROR: AddressSanitizer: heap-buffer-overflow on address 0x6020f2f4 at
pc 0x7f65d8cc2225 bp 0x7ffe93cc5a60 sp 0x7ffe93cc5208
On 1/6/21 5:23 AM, Jiaxun Yang wrote:
> 在 2021/1/5 下午6:05, Philippe Mathieu-Daudé 写道:
[...]
>>> I based the decodetree logic on the R6 ISA manual, decoding the
>>> bits from the more recent feature (a leaf) to the root, following
>>> this tree:
>>> https://images.anandtech.com/doci/8457/MIPS%20ISA%
Thank you for review!
Jinhao Gao
-Original Message-
From: Dr. David Alan Gilbert [mailto:dgilb...@redhat.com]
Sent: 2021年1月5日 19:18
To: gaojinhao
Cc: qemu-...@nongnu.org; qemu-devel@nongnu.org; Michael S . Tsirkin
; David Gibson ; Greg Kurz
; Marc-André Lureau ; Stefan
Berger ; Jason
From: Xuzhou Cheng
When a write to ECSPI_CONREG register to disable the SPI controller,
imx_spi_reset() is called to reset the controller, during which CS
lines should have been disabled, otherwise the state machine of any
devices (e.g.: SPI flashes) connected to the SPI master is stuck to
its la
From: Bin Meng
This series fixes a bunch of bugs in current implementation of the imx
spi controller, including the following issues:
- chip select signal was not lower down when spi controller is reset
- transfer incorrect data when the burst length is larger than 32 bit
- spi controller tx and
From: Bin Meng
Avoid using a magic number (4) everywhere for the number of chip
selects supported.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
---
(no changes since v1)
include/hw/ssi/imx_spi.h | 5 -
hw/ssi/imx_spi.c | 4 ++--
2 files changed, 6 insertions(+), 3 delet
From: Bin Meng
For the ECSPIx_CONREG register BURST_LENGTH field, the manual says:
0x020 A SPI burst contains the 1 LSB in first word and all 32 bits in second
word.
0x021 A SPI burst contains the 2 LSB in first word and all 32 bits in second
word.
Current logic uses either s->burst_length or
From: Bin Meng
The endianness of data exchange between tx and rx fifo is incorrect.
Earlier bytes are supposed to show up on MSB and later bytes on LSB,
ie: in big endian. The manual does not explicitly say this, but the
U-Boot and Linux driver codes have a swap on the data transferred
to tx fifo
On Wed, Jan 6, 2021 at 8:22 AM Bin Meng wrote:
>
> On Wed, Jan 6, 2021 at 5:11 AM Peter Maydell wrote:
> >
> > On Tue, 5 Jan 2021 at 21:09, Alistair Francis wrote:
> > >
> > > On Wed, Dec 16, 2020 at 2:25 AM Bin Meng wrote:
> > > >
> > > > Hi Alistair, Peter,
> > > >
> > > > On Wed, Dec 2, 2020
On Thu, Dec 31, 2020 at 6:31 PM Philippe Mathieu-Daudé wrote:
>
> On 12/17/20 6:28 AM, Bin Meng wrote:
> > From: Bin Meng
> >
> > For the ECSPIx_CONREG register BURST_LENGTH field, the manual says:
> >
> > 0x020 A SPI burst contains the 1 LSB in first word and all 32 bits in
> > second word.
> >
On Wed, 6 Jan 2021, David Gibson wrote:
The following changes since commit 52d25464605dc20022ad94aa8bc8e8473e600833:
Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20210104' into
staging (2021-01-05 16:18:20 +)
are available in the Git repository at:
https://gitlab.com/d
From: Bin Meng
At present the upstream U-Boot (as of today, v2021.01-rc3) does not
boot on QEMU sabrelite machine.
This fixes several issues to improve emulation fidelity of the i.MX6
sabrelite board. With this series, upstream U-Boot can boot to U-Boot
command shell. While we are here, add a t
From: Bin Meng
At present, when booting U-Boot on QEMU sabrelite, we see:
Net: Board Net Initialization Failed
No ethernet found.
U-Boot scans PHY at address 4/5/6/7 (see board_eth_init() in the
U-Boot source: board/boundary/nitrogen6x/nitrogen6x.c). On the real
board, the Ethernet PHY is
From: Bin Meng
U-Boot expects PMU_MISC0 register bit 7 is set (see init_bandgap()
in arch/arm/mach-imx/mx6/soc.c) during boot. This bit indicates the
bandgap has stabilized.
With this change, the latest upstream U-Boot (v2021.01-rc3) for imx6
sabrelite board (mx6qsabrelite_defconfig), with a sli
From: Bin Meng
Currently when U-Boot boots, it prints "??" for i.MX processor:
CPU: Freescale i.MX?? rev1.0 at 792 MHz
The register that was used to determine the silicon type is
undocumented in the latest IMX6DQRM (Rev. 6, 05/2020), but we
can refer to get_cpu_rev() in arch/arm/mach-imx/mx
From: Bin Meng
This adds the target guide for SABRE Lite board, and documents how
to boot a Linux kernel and U-Boot bootloader.
Signed-off-by: Bin Meng
Reviewed-by: Alex Bennée
---
Changes in v3:
- correct 2 typos in sabrelite.rst
Changes in v2:
- new patch: add sabrelite target guide
doc
Friendly ping ...
Hi, please queue this well reviewed series, Thanks :-)
Keqian
On 2020/12/17 9:49, Keqian Zhu wrote:
> Hi all,
>
> This series fixes memory waste and adds alignment check for unmatched
> qemu_real_host_page_size and TARGET_PAGE_SIZE.
>
> Thanks.
>
> Keqian Zhu (2):
> accel:
Correct sample code to avoid confusing readers.
Signed-off-by: Keqian Zhu
Cc: qemu-triv...@nongnu.org
Reviewed-by: Paolo Bonzini
Reviewed-by: Peter Xu
---
v2:
- Add Cc and R-b.
---
docs/devel/rcu.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/docs/devel/rcu.txt b/do
201 - 268 of 268 matches
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