[PULL 07/36] tests/qtest/npcm7xx_rng-test: dump random data on failure

From: Havard Skinnemoen Dump the collected random data after a randomness test failure. Note that this relies on the test having called g_test_set_nonfatal_assertions() so we don't abort immediately on the assertion failure. Signed-off-by: Havard Skinnemoen Reviewed-by: Peter Maydell [PMM: mi

[PULL 18/36] target/arm: Refactor M-profile VMSR/VMRS handling

Currently M-profile borrows the A-profile code for VMSR and VMRS (access to the FP system registers), because all it needs to support is the FPSCR. In v8.1M things become significantly more complicated in two ways: * there are several new FP system registers; some have side effects on read, a

[PULL 26/36] target/arm: For v8.1M, always clear R0-R3, R12, APSR, EPSR on exception entry

In v8.0M, on exception entry the registers R0-R3, R12, APSR and EPSR are zeroed for an exception taken to Non-secure state; for an exception taken to Secure state they become UNKNOWN, and we chose to leave them at their previous values. In v8.1M the behaviour is specified more tightly and these re

[PULL 09/36] i.MX31: Fix bad printf format specifiers

From: Alex Chen We should use printf format specifier "%u" instead of "%d" for argument of type "unsigned int". Reported-by: Euler Robot Signed-off-by: Alex Chen Message-id: 2020112609.112238-3-alex.c...@huawei.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/misc/imx3

[PULL 19/36] target/arm: Move general-use constant expanders up in translate.c

The constant-expander functions like negate, plus_2, etc, are generally useful; move them up in translate.c so we can use them in the VFP/Neon decoders as well as in the A32/T32/T16 decoders. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20201119215617.29887-9-peter.may

[PULL 22/36] target/arm: Use new FPCR_NZCV_MASK constant

We defined a constant name for the mask of NZCV bits in the FPCR/FPSCR in the previous commit; use it in a couple of places in existing code, where we're masking out everything except NZCV for the "load to Rt=15 sets CPSR.NZCV" special case. Signed-off-by: Peter Maydell Reviewed-by: Richard Hende

[PULL 23/36] target/arm: Factor out preserve-fp-state from full_vfp_access_check()

Factor out the code which handles M-profile lazy FP state preservation from full_vfp_access_check(); accesses to the FPCXT_NS register are a special case which need to do just this part (corresponding in the pseudocode to the PreserveFPState() function), and not the full set of actions matching the

[PULL 20/36] target/arm: Implement VLDR/VSTR system register

Implement the new-in-v8.1M VLDR/VSTR variants which directly read or write FP system registers to memory. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20201119215617.29887-10-peter.mayd...@linaro.org --- target/arm/vfp.decode | 14 ++ target/arm/translate

[PULL 08/36] i.MX25: Fix bad printf format specifiers

From: Alex Chen We should use printf format specifier "%u" instead of "%d" for argument of type "unsigned int". Reported-by: Euler Robot Signed-off-by: Alex Chen Message-id: 2020112609.112238-2-alex.c...@huawei.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/misc/imx2

[PULL 31/36] hw/intc/armv7m_nvic: Support v8.1M CCR.TRD bit

v8.1M introduces a new TRD flag in the CCR register, which enables checking for stack frame integrity signatures on SG instructions. This bit is not banked, and is always RAZ/WI to Non-secure code. Adjust the code for handling CCR reads and writes to handle this. Signed-off-by: Peter Maydell Revi

[PULL 27/36] target/arm: In v8.1M, don't set HFSR.FORCED on vector table fetch failures

In v8.1M, vector table fetch failures don't set HFSR.FORCED (see rule R_LLRP). (In previous versions of the architecture this was either required or IMPDEF.) Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20201119215617.29887-18-peter.mayd...@linaro.org --- target/arm/

[PULL 11/36] i.MX6ul: Fix bad printf format specifiers

From: Alex Chen We should use printf format specifier "%u" instead of "%d" for argument of type "unsigned int". Reported-by: Euler Robot Signed-off-by: Alex Chen Message-id: 2020112609.112238-5-alex.c...@huawei.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/misc/imx6

[PULL 25/36] hw/intc/armv7m_nvic: Update FPDSCR masking for v8.1M

The FPDSCR register has a similar layout to the FPSCR. In v8.1M it gains new fields FZ16 (if half-precision floating point is supported) and LTPSIZE (always reads as 4). Update the reset value and the code that handles writes to this register accordingly. Signed-off-by: Peter Maydell Reviewed-b

[PULL 34/36] target/arm: Implement M-profile "minimal RAS implementation"

For v8.1M the architecture mandates that CPUs must provide at least the "minimal RAS implementation" from the Reliability, Availability and Serviceability extension. This consists of: * an ESB instruction which is a NOP -- since it is in the HINT space we need only add a comment * an RFSR regi

[PULL 28/36] target/arm: Implement v8.1M REVIDR register

In v8.1M a REVIDR register is defined, which is at address 0xe00ecfc and is a read-only IMPDEF register providing implementation specific minor revision information, like the v8A REVIDR_EL1. Implement this. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20201119215617.29

[PULL 14/36] target/arm: Don't clobber ID_PFR1.Security on M-profile cores

In arm_cpu_realizefn() we check whether the board code disabled EL3 via the has_el3 CPU object property, which we create if the CPU starts with the ARM_FEATURE_EL3 feature bit. If it is disabled, then we turn off ARM_FEATURE_EL3 and also zero out the relevant fields in the ID_PFR1 and ID_AA64PFR0

[PULL 29/36] target/arm: Implement new v8.1M NOCP check for exception return

In v8.1M a new exception return check is added which may cause a NOCP UsageFault (see rule R_XLTP): before we clear s0..s15 and the FPSCR we must check whether access to CP10 from the Security state of the returning exception is disabled; if it is then we must take a fault. (Note that for our impl

[PULL 32/36] target/arm: Implement CCR_S.TRD behaviour for SG insns

v8.1M introduces a new TRD flag in the CCR register, which enables checking for stack frame integrity signatures on SG instructions. Add the code in the SG insn implementation for the new behaviour. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20201119215617.29887-24-p

Re: [PATCH 2/4] target/arm: Fixup contiguous first-fault and no-fault loads

On 2020/12/9 4:16, Richard Henderson wrote: On 12/6/20 10:46 PM, LIU Zhiwei wrote: First-fault or no-fault doesn't mean only access one page. But the implementation is *allowed* to access only one page. Thus the comment: -/* - * MemSingleNF is allowed to fail for any reason. We hav

[PULL 15/36] target/arm: Implement VSCCLRM insn

Implement the v8.1M VSCCLRM insn, which zeros floating point registers if there is an active floating point context. This requires support in write_neon_element32() for the MO_32 element size, so add it. Because we want to use arm_gen_condlabel(), we need to move the definition of that function up

[PULL 30/36] target/arm: Implement new v8.1M VLLDM and VLSTM encodings

v8.1M adds new encodings of VLLDM and VLSTM (where bit 7 is set). The only difference is that: * the old T1 encodings UNDEF if the implementation implements 32 Dregs (this is currently architecturally impossible for M-profile) * the new T2 encodings have the implementation-defined option to

[Bug 1336794] Re: 9pfs does not honor open file handles on unlinked files

Closed by accident, Christian just told me that this is not fixed yet. Sorry for the inconvenience. ** Changed in: qemu Status: Fix Released => Confirmed -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.n

[PULL 12/36] hw/intc/armv7m_nvic: Make all of system PPB range be RAZWI/BusFault

For M-profile CPUs, the range from 0xe000 to 0xe00f is the Private Peripheral Bus range, which includes all of the memory mapped devices and registers that are part of the CPU itself, including the NVIC, systick timer, and debug and trace components like the Data Watchpoint and Trace unit (

[PULL 35/36] hw/intc/armv7m_nvic: Implement read/write for RAS register block

The RAS feature has a block of memory-mapped registers at offset 0x5000 within the PPB. For a "minimal RAS" implementation we provide no error records and so the only registers that exist in the block are ERRIIDR and ERRDEVID. The "RAZ/WI for privileged, BusFault for nonprivileged" behaviour of t

[PULL 33/36] hw/intc/armv7m_nvic: Fix "return from inactive handler" check

In commit 077d7449100d824a4 we added code to handle the v8M requirement that returns from NMI or HardFault forcibly deactivate those exceptions regardless of what interrupt the guest is trying to deactivate. Unfortunately this broke the handling of the "illegal exception return because the returni

[PULL 21/36] target/arm: Implement M-profile FPSCR_nzcvqc

v8.1M defines a new FP system register FPSCR_nzcvqc; this behaves like the existing FPSCR, except that it reads and writes only bits [31:27] of the FPSCR (the N, Z, C, V and QC flag bits). (Unlike the FPSCR, the special case for Rt=15 of writing the CPSR.NZCV is not permitted.) Implement the regi

[PATCH v10 00/32] i386 cleanup

Hello, this is version 10 of the cleanup, changed from RFC to PATCH. v9 -> v10: minor tweaks and fixes * in "i386: split cpu accelerators from cpu.c", use kvm/kvm-cpu.c, hvf/hvf-cpu.c, tcg/tcg-cpu.c. Easier to understand compared to editing multiple cpu.c files, and matches the header files if n

[PATCH v10 02/32] accel/tcg: split tcg_start_vcpu_thread

after the initial split into 3 tcg variants, we proceed to also split tcg_start_vcpu_thread. We actually split it in 2 this time, since the icount variant just uses the round robin function. Suggested-by: Richard Henderson Signed-off-by: Claudio Fontana Reviewed-by: Richard Henderson --- acce

[PATCH v10 07/32] i386: hvf: remove stale MAINTAINERS entry for old hvf stubs

Signed-off-by: Claudio Fontana Reviewed-by: Roman Bolshakov Reviewed-by: Alex Bennée --- MAINTAINERS | 1 - 1 file changed, 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index 448593c904..f53f2678d8 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -444,7 +444,6 @@ M: Cameron Esfahani M:

[PULL 24/36] target/arm: Implement FPCXT_S fp system register

Implement the new-in-v8.1M FPCXT_S floating point system register. This is for saving and restoring the secure floating point context, and it reads and writes bits [27:0] from the FPSCR and the CONTROL.SFPA bit in bit [31]. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id:

[PATCH v10 03/32] accel/tcg: rename tcg-cpus functions to match module name

Signed-off-by: Claudio Fontana Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- accel/tcg/tcg-cpus-icount.h | 6 +-- accel/tcg/tcg-cpus-rr.h | 2 +- accel/tcg/tcg-cpus.h| 6 +-- accel/tcg/tcg-cpus-icount.c | 24 ++-- accel/tcg/tcg-cpus-mttcg.c | 10

[PATCH v10 11/32] tcg: cpu_exec_{enter,exit} helpers

From: Eduardo Habkost Move invocation of CPUClass.cpu_exec_*() to separate helpers, to make it easier to refactor that code later. Signed-off-by: Eduardo Habkost Signed-off-by: Claudio Fontana Reviewed-by: Alex Bennée --- accel/tcg/cpu-exec.c | 23 ++- 1 file changed, 18

[PATCH v10 06/32] i386: move hax accel files into hax/

Signed-off-by: Claudio Fontana Reviewed-by: Alex Bennée --- target/i386/{ => hax}/hax-cpus.h | 0 target/i386/{ => hax}/hax-i386.h | 6 +++--- target/i386/{ => hax}/hax-interface.h | 0 target/i386/{ => hax}/hax-posix.h | 0 target/i386/{ => hax}/hax-windows.h | 0 target/i386/{

[PULL 36/36] hw/arm/armv7m: Correct typo in QOM object name

Correct a typo in the name we give the NVIC object. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-id: 20201119215617.29887-28-peter.mayd...@linaro.org --- hw/arm/armv7m.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git

[PATCH v10 04/32] i386: move kvm accel files into kvm/

Signed-off-by: Claudio Fontana Reviewed-by: Alex Bennée --- meson.build | 1 + target/i386/cpu.h| 2 +- target/i386/{ => kvm}/hyperv-proto.h | 0 target/i386/{ => kvm}/hyperv.h | 0 target/i386/{ => kvm}/kvm_i386.h | 0 target/i386/kvm/trace

[PATCH v10 15/32] cpu: Introduce TCGCpuOperations struct

From: Eduardo Habkost The TCG-specific CPU methods will be moved to a separate struct, to make it easier to move accel-specific code outside generic CPU code in the future. Start by moving tcg_initialize(). The new CPUClass.tcg_opts field may eventually become a pointer, but keep it an embedded

[PATCH v10 12/32] tcg: make CPUClass.cpu_exec_* optional

From: Eduardo Habkost This will let us simplify the code that initializes CPU class methods, when we move cpu_exec_*() to a separate struct. Signed-off-by: Eduardo Habkost Signed-off-by: Claudio Fontana Reviewed-by: Alex Bennée --- accel/tcg/cpu-exec.c | 11 --- 1 file changed, 8 ins

[PATCH v10 10/32] i386: move TCG cpu class initialization out of helper.c

Signed-off-by: Claudio Fontana --- target/i386/cpu.h | 97 ++--- target/i386/tcg/helper-tcg.h | 112 ++ target/i386/tcg/tcg-cpu.h | 15 + target/i386/cpu.c | 33 -- target/i386/helper.c |

[PATCH v10 20/32] cpu: Move tlb_fill to tcg_ops

From: Eduardo Habkost Signed-off-by: Eduardo Habkost [claudio: wrapped in CONFIG_TCG] Signed-off-by: Claudio Fontana Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alex Bennée --- include/hw/core/cpu.h | 9 - include/hw/core/tcg-cpu-ops.h | 12 accel/tcg/c

Re: [RFC PATCH 07/27] vhost: Route guest->host notification through qemu

On Wed, Dec 09, 2020 at 06:08:14PM +0100, Eugenio Perez Martin wrote: > On Mon, Dec 7, 2020 at 6:42 PM Stefan Hajnoczi wrote: > > On Fri, Nov 20, 2020 at 07:50:45PM +0100, Eugenio Pérez wrote: > > > +{ > > > +struct vhost_vring_file file = { > > > +.index = idx > > > +}; > > > +

[PATCH v10 16/32] target/riscv: remove CONFIG_TCG, as it is always TCG

for now only TCG is allowed as an accelerator for riscv, so remove the CONFIG_TCG use. Signed-off-by: Claudio Fontana Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index a52e0ce4

[PATCH v10 13/32] tcg: Make CPUClass.debug_excp_handler optional

From: Eduardo Habkost Signed-off-by: Eduardo Habkost Signed-off-by: Claudio Fontana Reviewed-by: Alex Bennée --- accel/tcg/cpu-exec.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 890b88861a..64cba89356 100644 --- a/ac

[PATCH v10 24/32] cpu: move cc->transaction_failed to tcg_ops

Signed-off-by: Claudio Fontana Reviewed-by: Alex Bennée --- include/hw/core/cpu.h | 18 +++--- include/hw/core/tcg-cpu-ops.h | 10 ++ hw/mips/jazz.c| 9 +++-- target/alpha/cpu.c| 2 +- target/arm/cpu.c | 4 ++-- target/m

Re: [RFC PATCH 13/27] vhost: Send buffers to device

On Wed, Dec 09, 2020 at 07:41:23PM +0100, Eugenio Perez Martin wrote: > On Tue, Dec 8, 2020 at 9:16 AM Stefan Hajnoczi wrote: > > On Fri, Nov 20, 2020 at 07:50:51PM +0100, Eugenio Pérez wrote: > > > +while (true) { > > > +int r; > > > +if (virtio_queue_full(vq)) { >

[PATCH v10 18/32] cpu: Move synchronize_from_tb() to tcg_ops

From: Eduardo Habkost Signed-off-by: Eduardo Habkost [claudio: wrapped in CONFIG_TCG] Signed-off-by: Claudio Fontana Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alex Bennée --- include/hw/core/cpu.h | 8 include/hw/core/tcg-cpu-ops.h | 12 accel/tcg/cpu-ex

[PATCH v10 21/32] cpu: Move debug_excp_handler to tcg_ops

From: Eduardo Habkost Signed-off-by: Eduardo Habkost Signed-off-by: Claudio Fontana Reviewed-by: Alex Bennée --- include/hw/core/cpu.h | 2 -- include/hw/core/tcg-cpu-ops.h | 2 ++ accel/tcg/cpu-exec.c | 4 ++-- target/arm/cpu.c | 2 +- target/i386/tcg/tcg-cpu.c

[PATCH v10 27/32] accel: replace struct CpusAccel with AccelOpsClass

also centralize the registration of the cpus.c module accelerator operations in accel/accel-softmmu.c Consequently, rename all tcg-cpus.c, kvm-cpus.c etc to tcg-accel-ops.c, kvm-accel-ops.c etc, also matching the object type names. Signed-off-by: Claudio Fontana --- accel/accel-softmmu.h

Re: [RFC PATCH 16/27] virtio: Expose virtqueue_alloc_element

On Wed, Dec 09, 2020 at 07:46:49PM +0100, Eugenio Perez Martin wrote: > On Tue, Dec 8, 2020 at 9:26 AM Stefan Hajnoczi wrote: > > > > On Fri, Nov 20, 2020 at 07:50:54PM +0100, Eugenio Pérez wrote: > > > Specify VirtQueueElement * as return type makes no harm at this moment. > > > > The reason for

[PATCH v10 23/32] cpu: move cc->do_interrupt to tcg_ops

Signed-off-by: Claudio Fontana Reviewed-by: Alex Bennée --- include/hw/core/cpu.h | 2 -- include/hw/core/tcg-cpu-ops.h | 3 +++ accel/tcg/cpu-exec.c| 4 ++-- target/alpha/cpu.c | 2 +- target/arm/cpu.c| 6 -- target/arm/cpu_tcg.c

[PATCH v10 31/32] hw/core/cpu: call qemu_init_vcpu in cpu_common_realizefn

move the call to qemu_init_vcpu inside cpu_common_realizefn, so it does not need to be done explicitly in each target cpu. This makes it a little bit better, but still the way realize is done continues to be bad; ideally the cpu_list_add would be done in common_cpu, and in this case we could avoid

[PATCH v10 19/32] cpu: Move cpu_exec_* to tcg_ops

From: Eduardo Habkost Signed-off-by: Eduardo Habkost [claudio: wrapped in CONFIG_TCG] Signed-off-by: Claudio Fontana Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alex Bennée --- include/hw/core/cpu.h | 6 -- include/hw/core/tcg-cpu-ops.h | 6 ++ accel/tcg/cpu-exec.c

[Bug 1877384] Re: 9pfs file create with mapped-xattr can fail on overlayfs

Closed by accident, Christian just told me that this is not fixed yet. Sorry for the inconvenience. ** Changed in: qemu Status: Fix Released => Confirmed -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.n

[PULL 00/11] Microvm 20201210 patches

The following changes since commit 5e7b204dbfae9a562fc73684986f936b97f63877: Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging (2020-12-09 20:08:54 +) are available in the Git repository at: git://git.kraxel.org/qemu tags/microvm-20201210-pull-reques

[PATCH v10 25/32] cpu: move do_unaligned_access to tcg_ops

make it consistently SOFTMMU-only. Signed-off-by: Claudio Fontana Reviewed-by: Alex Bennée --- include/hw/core/cpu.h | 17 +++-- include/hw/core/tcg-cpu-ops.h | 7 +++ target/alpha/cpu.c | 2 +- target/arm/cpu.c| 2 +- target/hppa/cpu.

[PULL 09/11] tests/acpi: add ioapic2=on test for microvm

APIC table changes: [034h 0052 1]Subtable Type : 01 [I/O APIC] [035h 0053 1] Length : 0C [036h 0054 1] I/O Apic ID : 00 [037h 0055 1] Reserved : 00 [038h 0056 4] Address : FEC0 [03Ch

[PATCH v10 01/32] accel/tcg: split CpusAccel into three TCG variants

split up the CpusAccel tcg_cpus into three TCG variants: tcg_cpus_rr (single threaded, round robin cpus) tcg_cpus_icount (same as rr, but with instruction counting enabled) tcg_cpus_mttcg (multi-threaded cpus) Suggested-by: Richard Henderson Signed-off-by: Claudio Fontana Reviewed-by: Richard H

[PULL 051/113] treewide: do not use short-form boolean options

They are going to be deprecated, avoid warnings on stdout while the tests run. Signed-off-by: Paolo Bonzini --- docs/specs/tpm.rst | 2 +- python/qemu/machine.py | 2 +- qemu-options.hx | 32 ++-- tests/qtest/bios-tab

[PULL 07/11] tests/acpi: allow updates for expected data files

Signed-off-by: Gerd Hoffmann Reviewed-by: Michael S. Tsirkin Reviewed-by: Igor Mammedov Reviewed-by: Sergio Lopez Message-id: 20201203105423.10431-9-kra...@redhat.com --- tests/qtest/bios-tables-test-allowed-diff.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/tests/qtest/bios-tables-t

[PATCH v10 28/32] accel: introduce AccelCPUClass extending CPUClass

add a new optional interface to CPUClass, which allows accelerators to extend the CPUClass with additional accelerator-specific initializations. Signed-off-by: Claudio Fontana --- include/hw/core/accel-cpu.h | 25 + include/hw/core/cpu.h | 13 +++ accel/accel-co

[PATCH v10 05/32] i386: move whpx accel files into whpx/

Signed-off-by: Claudio Fontana Reviewed-by: Alex Bennée --- target/i386/{ => whpx}/whp-dispatch.h | 0 target/i386/{ => whpx}/whpx-cpus.h| 0 target/i386/{ => whpx}/whpx-all.c | 0 target/i386/{ => whpx}/whpx-cpus.c| 0 MAINTAINERS | 5 + target/i386/mes

[PATCH v10 29/32] i386: split cpu accelerators from cpu.c, using AccelCPUClass

i386 is the first user of AccelCPUClass, allowing to split cpu.c into: cpu.ccpuid and common x86 cpu functionality host-cpu.c host x86 cpu functions and "host" cpu type kvm/kvm-cpu.cKVM x86 AccelCPUClass hvf/hvf-cpu.cHVF x86 AccelCPUClass tcg/tcg-cpu.cTCG x86 AccelCPU

[PULL 05/11] microvm: drop microvm_gsi_handler()

With the improved gsi_handler() we don't need our private version any more. Signed-off-by: Gerd Hoffmann Reviewed-by: Igor Mammedov Reviewed-by: Michael S. Tsirkin Reviewed-by: Sergio Lopez Message-id: 20201203105423.10431-7-kra...@redhat.com --- hw/i386/microvm.c | 14 +- 1 file

[PATCH v10 08/32] i386: move TCG accel files into tcg/

Signed-off-by: Claudio Fontana Reviewed-by: Alex Bennée --- target/i386/{ => tcg}/bpt_helper.c | 0 target/i386/{ => tcg}/cc_helper.c | 0 target/i386/{ => tcg}/excp_helper.c | 0 target/i386/{ => tcg}/fpu_helper.c | 0 target/i386/{ => tcg}/int_helper.c | 0 target/i386/{ => tcg}/mem_

[PULL 0/5] aspeed queue

The following changes since commit 5e7b204dbfae9a562fc73684986f936b97f63877: Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging (2020-12-09 20:08:54 +) are available in the Git repository at: https://github.com/legoater/qemu/ tags/pull-aspeed-20201210

[PULL 001/113] target/i386: fix operand order for PDEP and PEXT

For PDEP and PEXT, the mask is provided in the memory (mod+r/m) operand, and therefore is loaded in s->T0 by gen_ldst_modrm. The source is provided in the second source operand (VEX.) and therefore is loaded in s->T1. Fix the order in which they are passed to the helpers. Reported-by: Lenard

[PULL 03/11] microvm: make number of virtio transports runtime changeable

This will allow to increase the number of transports in case we have enough irq lines available for them all. Signed-off-by: Gerd Hoffmann Reviewed-by: Michael S. Tsirkin Reviewed-by: Igor Mammedov Reviewed-by: Sergio Lopez Message-id: 20201203105423.10431-5-kra...@redhat.com --- include/hw/i

[PATCH v10 09/32] i386: move cpu dump out of helper.c into cpu-dump.c

Signed-off-by: Claudio Fontana Reviewed-by: Alex Bennée --- target/i386/cpu.h | 1 + target/i386/cpu-dump.c | 537 target/i386/helper.c| 514 -- target/i386/meson.build | 1 + 4 files changed, 539 inserti

[PULL 2/5] aspeed: Add support for the g220a-bmc board

From: John Wang G220A is a 2 socket x86 motherboard supported by OpenBMC. Strapping configuration was obtained from hardware. Signed-off-by: John Wang Reviewed-by: Cédric Le Goater Reviewed-by: Joel Stanley Message-Id: <20201122105134.671-2-wangzhiqiang...@bytedance.com> Signed-off-by: Cédric

Re: [PATCH] virtiofsd: make the debug log timestamp on stderr more human-readable

* Laszlo Ersek (ler...@redhat.com) wrote: > The current timestamp format doesn't help me visually notice small jumps > in time ("small" as defined on human scale, such as a few seconds or a few > ten seconds). Replace it with a local time format where such differences > stand out. > > Before: > >

[PULL 02/11] x86: add support for second ioapic

Add ioapic_init_secondary to initialize it, wire up in gsi handling and acpi apic table creation. Signed-off-by: Gerd Hoffmann Reviewed-by: Michael S. Tsirkin Reviewed-by: Igor Mammedov Reviewed-by: Sergio Lopez Message-id: 20201203105423.10431-4-kra...@redhat.com --- include/hw/i386/ioapic.h

[PATCH v10 14/32] cpu: Remove unnecessary noop methods

From: Eduardo Habkost Signed-off-by: Eduardo Habkost Signed-off-by: Claudio Fontana Reviewed-by: Alex Bennée --- hw/core/cpu.c | 13 - 1 file changed, 13 deletions(-) diff --git a/hw/core/cpu.c b/hw/core/cpu.c index 576fa1d7ba..994a12cb35 100644 --- a/hw/core/cpu.c +++ b/hw/core/

[PULL 1/5] hw/misc: add an EMC141{3,4} device model

From: John Wang Largely inspired by the TMP421 temperature sensor, here is a model for the EMC1413/EMC1414 temperature sensors. Specs can be found here : http://ww1.microchip.com/downloads/en/DeviceDoc/20005274A.pdf Cc: Philippe Mathieu-Daudé Signed-off-by: John Wang Reviewed-by: Cédric Le

[PATCH v10 17/32] accel/tcg: split TCG-only code from cpu_exec_realizefn

move away TCG-only code, make it compile only on TCG. Signed-off-by: Claudio Fontana Reviewed-by: Alex Bennée --- include/hw/core/cpu.h | 8 + accel/tcg/cpu-exec.c | 28 + cpu.c | 70 --- hw/core/cpu.c | 6 ++

[PULL 10/11] tests/acpi: update expected data files

Signed-off-by: Gerd Hoffmann Reviewed-by: Michael S. Tsirkin Reviewed-by: Igor Mammedov Reviewed-by: Sergio Lopez Message-id: 20201203105423.10431-12-kra...@redhat.com --- tests/data/acpi/microvm/APIC.ioapic2 | Bin 70 -> 82 bytes tests/data/acpi/microvm/DSDT.ioapic2 | Bin 365 -> 365 bytes 2

[PULL 4/5] aspeed/smc: Add support for address lane disablement

The controller can be configured to disable or enable address and data byte lanes when issuing commands. This is useful in read command mode to send SPI NOR commands that don't have an address space, such as RDID. It's a good way to have a unified read operation for registers and flash contents acc

[PATCH v10 22/32] target/arm: do not use cc->do_interrupt for KVM directly

cc->do_interrupt is in theory a TCG callback used in accel/tcg only, to prepare the emulated architecture to take an interrupt as defined in the hardware specifications, but in reality the _do_interrupt style of functions in targets are also occasionally reused by KVM to prepare the architecture s

[PULL 04/11] microvm: make pcie irq base runtime changeable

Allows to move them in case we have enough irq lines available. Signed-off-by: Gerd Hoffmann Reviewed-by: Igor Mammedov Reviewed-by: Michael S. Tsirkin Reviewed-by: Sergio Lopez Message-id: 20201203105423.10431-6-kra...@redhat.com --- include/hw/i386/microvm.h | 2 +- hw/i386/microvm.c

[PATCH] block/nvme: Implement fake truncate() coroutine

NVMe drive can not be shrunk. Since commit c80d8b06cfa we can use the @exact parameter (set to false) to return success if the block device is larger than the requested offset (even if we can not be shrunk). Use this parameter to implement the NVMe truncate() coroutine, similarly how it is done f

Re: [PATCH 1/1] spapr.c: set a 'kvm-type' default value instead of relying on NULL

On 12/10/20 9:47 AM, Greg Kurz wrote: On Thu, 10 Dec 2020 13:34:59 +0100 Paolo Bonzini wrote: To sum up everything: LGTM I just sent a v2 with a bit more done (e.g. added ignore case compare for 'auto'). Feel free to use that version or this one amended by this diff from Paolo. Thank

[PULL 11/11] tests/acpi: disallow updates for expected data files

Signed-off-by: Gerd Hoffmann Reviewed-by: Michael S. Tsirkin Reviewed-by: Igor Mammedov Reviewed-by: Sergio Lopez Message-id: 20201203105423.10431-13-kra...@redhat.com --- tests/qtest/bios-tables-test-allowed-diff.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/tests/qtest/bios-tables-t

[PATCH v10 26/32] accel: extend AccelState and AccelClass to user-mode

Signed-off-by: Claudio Fontana Reviewed-by: Alex Bennée --- include/hw/boards.h| 2 +- include/{sysemu => qemu}/accel.h | 14 + include/sysemu/hvf.h | 2 +- include/sysemu/kvm.h | 2 +- include/sysemu/kvm_int.h | 2 +- target/i3

[PULL 3/5] ast2600: SRAM is 89KB

From: Joel Stanley On the AST2600A1, the SRAM size was increased to 89KB. Fixes: 7582591ae745 ("aspeed: Support AST2600A1 silicon revision") Signed-off-by: Joel Stanley Reviewed-by: Cédric Le Goater Message-Id: <20201112012113.835858-1-j...@jms.id.au> Signed-off-by: Cédric Le Goater --- hw/a

Re: [PATCH v10 25/32] cpu: move do_unaligned_access to tcg_ops

On 12/10/20 2:14 PM, Claudio Fontana wrote: > On 12/10/20 2:01 PM, Philippe Mathieu-Daudé wrote: >> On 12/10/20 1:12 PM, Claudio Fontana wrote: >>> make it consistently SOFTMMU-only. >>> >>> Signed-off-by: Claudio Fontana >>> Reviewed-by: Alex Bennée >>> --- >>> include/hw/core/cpu.h |

[PATCH v10 30/32] cpu: call AccelCPUClass::cpu_realizefn in cpu_exec_realizefn

move the call to the accel_cpu_interface method to the general cpu_exec_realizefn from target/i386, so it does not need to be called for every target explicitly as we enable more targets. Signed-off-by: Claudio Fontana --- cpu.c | 5 + target/i386/cpu.c | 15 --- 2 f

[PULL 08/11] tests/acpi: add data files for ioapic2 test variant

Copy microvm/APIC -> microvm/APIC.ioapic2 Copy microvm/DSDT -> microvm/DSDT.ioapic2 Signed-off-by: Gerd Hoffmann Reviewed-by: Michael S. Tsirkin Reviewed-by: Igor Mammedov Reviewed-by: Sergio Lopez Message-id: 20201203105423.10431-10-kra...@redhat.com --- tests/data/acpi/microvm/APIC.ioapic2

Re: [PATCH v6 1/4] migration: introduce 'background-snapshot' migration capability

Andrey Gruzdev via writes: > Add new capability to 'qapi/migration.json' schema. > Update migrate_caps_check() to validate enabled capability set > against introduced one. Perform checks for required kernel features > and compatibility with guest memory backends. > > Signed-off-by: Andrey Gruzdev

[PATCH v10 32/32] cpu: introduce cpu_accel_instance_init

centralize the calls to cpu->accel_cpu_interface Signed-off-by: Claudio Fontana --- include/hw/core/cpu.h | 6 ++ hw/core/cpu.c | 9 + target/i386/cpu.c | 9 ++--- 3 files changed, 17 insertions(+), 7 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/

[PATCH 0/1] Fix for one more race on scsi device removal

This is a patch from Paulo that he suggested to fix bz #1854811. (https://bugzilla.redhat.com/show_bug.cgi?id=1854811) I think that the race that is described in this bug can still happen (in theory) so it is better to plug it with a refcount as it was suggested. Best regards, Maxim Levit

Re: [RFC 5/8] s390x/pci: Fix memory_region_access_valid call

On Wed, 9 Dec 2020 15:34:23 -0500 Matthew Rosato wrote: > In pcistb_service_handler, a call is made to validate that the memory > region can be accessed. However, the call is made using the entire length > of the pcistb operation, which can be larger than the allowed memory > access size (8).

[PULL 01/11] x86: rewrite gsi_handler()

Rewrite function to use switch() for IRQ number mapping. Check i8259_irq exists before raising it so the function also works in case no i8259 (aka pic) is present. Signed-off-by: Gerd Hoffmann Reviewed-by: Igor Mammedov Reviewed-by: Michael S. Tsirkin Message-id: 20201203105423.10431-3-kra...@r

Re: [PATCH v10 25/32] cpu: move do_unaligned_access to tcg_ops

On 12/10/20 1:12 PM, Claudio Fontana wrote: > make it consistently SOFTMMU-only. > > Signed-off-by: Claudio Fontana > Reviewed-by: Alex Bennée > --- > include/hw/core/cpu.h | 17 +++-- > include/hw/core/tcg-cpu-ops.h | 7 +++ > target/alpha/cpu.c | 2 +

[PULL 06/11] microvm: add second ioapic

Create second ioapic, route virtio-mmio IRQs to it, allow more virtio-mmio devices (24 instead of 8). Needs ACPI, enabled by default, can be turned off using -machine ioapic2=off Signed-off-by: Gerd Hoffmann Reviewed-by: Michael S. Tsirkin Reviewed-by: Igor Mammedov Reviewed-by: Sergio Lopez

[PATCH v2 1/1] spapr.c: set a 'kvm-type' default value instead of relying on NULL

spapr_kvm_type() is considering 'vm_type=NULL' as a valid input, where the function returns 0. This is relying on the current QEMU machine options handling logic, where the absence of the 'kvm-type' option will be reflected as 'vm_type=NULL' in this function. This is not robust, and will break if

Re: [PATCH v12 08/19] multi-process: define MPQemuMsg format and transmission functions

On Thu, Dec 10, 2020 at 12:20:06PM +0400, Marc-André Lureau wrote: > Hi > > On Thu, Dec 10, 2020 at 5:42 AM Elena Ufimtseva > wrote: > > > On Mon, Dec 07, 2020 at 05:18:46PM +0400, Marc-André Lureau wrote: > > > Hi > > > > > > On Wed, Dec 2, 2020 at 12:25 AM Jagannathan Raman > > > wrote: > > >

[PULL 002/113] target/i386: Support up to 32768 CPUs without IRQ remapping

From: David Woodhouse The IOAPIC has an 'Extended Destination ID' field in its RTE, which maps to bits 11-4 of the MSI address. Since those address bits fall within a given 4KiB page they were historically non-trivial to use on real hardware. The Intel IOMMU uses the lowest bit to indicate a rem

Re: [Bug 1877384] Re: 9pfs file create with mapped-xattr can fail on overlayfs

It might be, I revisited a month back and could no longer trigger the bug, so it's possible unrelated changes or kernel changes have fixed the overlayfs copy-up semantics in cases where it would cause issues with QEMU. If I ever see it again I can resubmit evidence, so it may be better off closed.

[PATCH 1/1] scsi: fix device removal race vs IO restart callback on resume

There is (mostly theoretical) race between removal of a scsi device and scsi_dma_restart_bh. It used to be easier to hit this race prior to my / Paulo's patch series that added rcu to scsi bus device handling code, but IMHO this race should still be possible to hit, at least in theory. Buglink: h

[PULL v2 000/113] First batch of misc (i386, kernel-doc, memory, vl.c) changes for QEMU 6.0

The following changes since commit 5e7b204dbfae9a562fc73684986f936b97f63877: Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging (2020-12-09 20:08:54 +) are available in the Git repository at: https://gitlab.com/bonzini/qemu.git tags/for-upstream for you to fetch

Re: [PATCH] fuzz: map all BARs and enable PCI devices

On 12/10/20 12:36 PM, Darren Kenny wrote: > Hi Alex, > > On Wednesday, 2020-12-09 at 15:10:54 -05, Alexander Bulekov wrote: >> Prior to this patch, the fuzzer found inputs to map PCI device BARs and >> enable the device. While it is nice that the fuzzer can do this, it >> added significant overhea

Re: [PATCH] sdl2: Add extra mouse buttons

Hi, > @@ -275,6 +275,8 @@ static void sdl_send_mouse_event(struct > sdl2_console *scon, int dx, int dy, Patch is corrupted (mailer wrapped the line). Can you resend with git send-email? thanks, Gerd

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