Signed-off-by: Claudio Fontana
---
target/i386/cpu-dump.c | 537
target/i386/cpu.h | 1 +
target/i386/helper.c| 514 --
target/i386/meson.build | 1 +
4 files changed, 539 insertions(+), 514 deletions(-)
On 08/12/20 20:14, Alejandro Jimenez wrote:
##
+# @reboot-set-action:
+#
+# Set reboot action
+#
+# Since: 6.0
+##
+{ 'command': 'reboot-set-action', 'data' : {'action': 'RebootAction'} }
+
+##
+# @shutdown-set-action:
+#
+# Set shutdown action
+#
+# Since: 6.0
+##
+{ 'command': 'shutdown-set-a
Signed-off-by: Claudio Fontana
---
target/i386/meson.build | 14 +-
target/i386/{ => tcg}/bpt_helper.c | 0
target/i386/{ => tcg}/cc_helper.c | 0
target/i386/{ => tcg}/excp_helper.c | 0
target/i386/{ => tcg}/fpu_helper.c | 0
target/i386/{ => tcg}/int_helper.c |
Signed-off-by: Claudio Fontana
---
target/i386/cpu.c | 33 --
target/i386/cpu.h | 97 ++---
target/i386/helper-tcg.h | 112 ++
target/i386/helper.c | 23 ---
target/i386/meson.build
Hi Klaus,
Thank you for your review! Please see replies below...
On Thu, 2020-11-12 at 20:36 +0100, Klaus Jensen wrote:
> Hi Dmitry,
>
> I know you posted v10, but my comments should be relevant to that as
> well.
>
> On Nov 5 11:53, Dmitry Fomichev wrote:
> > The emulation code has been chan
for now only TCG is allowed as an accelerator for riscv,
so remove the CONFIG_TCG use.
Signed-off-by: Claudio Fontana
---
target/riscv/cpu.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index a52e0ce466..27dd1645c9 100644
--- a/tar
From: Eduardo Habkost
The TCG-specific CPU methods will be moved to a separate struct,
to make it easier to move accel-specific code outside generic CPU
code in the future. Start by moving tcg_initialize().
The new CPUClass.tcg_opts field may eventually become a pointer,
but keep it an embedded
Signed-off-by: Claudio Fontana
---
accel/tcg/cpu-exec.c| 4 ++--
include/hw/core/cpu.h | 2 --
include/hw/core/tcg-cpu-ops.h | 3 +++
target/alpha/cpu.c | 2 +-
target/arm/cpu.c| 6 --
target/arm/cpu_tcg.c| 9 -
ta
From: Eduardo Habkost
This will let us simplify the code that initializes CPU class
methods, when we move cpu_exec_*() to a separate struct.
Signed-off-by: Eduardo Habkost
Signed-off-by: Claudio Fontana
---
accel/tcg/cpu-exec.c | 11 ---
1 file changed, 8 insertions(+), 3 deletions(-)
move away TCG-only code, make it compile only on TCG.
Signed-off-by: Claudio Fontana
---
accel/tcg/cpu-exec.c | 28 +
cpu.c | 70 ---
hw/core/cpu.c | 6 +++-
include/hw/core/cpu.h | 8 +
4 files changed, 74 in
The majority of code in nvme_rw() is becoming read- or write-specific.
Move these parts to two separate handlers, nvme_read() and nvme_write()
to make the code more readable and to remove multiple is_write checks
that has been present in the i/o path.
This is a refactoring patch, no change in func
make it consistently SOFTMMU-only.
Signed-off-by: Claudio Fontana
---
include/hw/core/cpu.h | 17 +++--
include/hw/core/tcg-cpu-ops.h | 7 +++
target/alpha/cpu.c | 2 +-
target/arm/cpu.c| 2 +-
target/hppa/cpu.c | 4 +++-
From: Eduardo Habkost
Signed-off-by: Eduardo Habkost
Signed-off-by: Claudio Fontana
---
accel/tcg/cpu-exec.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
index 890b88861a..64cba89356 100644
--- a/accel/tcg/cpu-exec.c
+++ b/a
Signed-off-by: Claudio Fontana
---
MAINTAINERS| 2 +-
accel/accel-common.c | 50 ++
accel/{accel.c => accel-softmmu.c} | 27 ++--
accel/accel-user.c | 24 ++
accel/meson.build
move the call to qemu_init_vcpu inside cpu_common_realizefn,
so it does not need to be done explicitly in each target cpu.
This makes it a little bit better, but still the way realize
is done continues to be bad; ideally the cpu_list_add would
be done in common_cpu, and in this case we could avoid
From: Eduardo Habkost
Signed-off-by: Eduardo Habkost
[claudio: wrapped in CONFIG_TCG]
Signed-off-by: Claudio Fontana
Reviewed-by: Philippe Mathieu-Daudé
---
accel/tcg/cpu-exec.c | 4 ++--
include/hw/core/cpu.h | 8
include/hw/core/tcg-cpu-ops.h | 14 +++---
From: Niklas Cassel
Many CNS commands have "allocated" command variants. These include
a namespace as long as it is allocated, that is a namespace is
included regardless if it is active (attached) or not.
While these commands are optional (they are mandatory for controllers
supporting the namesp
i386 is the first user of AccelCPUClass, allowing to split
cpu.c into:
cpu.ccpuid and common x86 cpu functionality
host-cpu.c host x86 cpu functions and "host" cpu type
kvm/cpu.cKVM x86 AccelCPUClass
hvf/cpu.cHVF x86 AccelCPUClass
tcg/cpu.cTCG x86 AccelCPU
From: Eduardo Habkost
Signed-off-by: Eduardo Habkost
[claudio: wrapped in CONFIG_TCG]
Signed-off-by: Claudio Fontana
Reviewed-by: Philippe Mathieu-Daudé
---
accel/tcg/cputlb.c | 6 +++---
accel/tcg/user-exec.c | 6 +++---
include/hw/core/cpu.h | 9 -
add a new optional interface to CPUClass,
which allows accelerators to extend the CPUClass
with additional accelerator-specific initializations.
Signed-off-by: Claudio Fontana
---
MAINTAINERS | 1 +
accel/accel-common.c| 44 +
include/
Define values and structures that are needed to support Zoned
Namespace Command Set (NVMe TP 4053).
Signed-off-by: Dmitry Fomichev
---
include/block/nvme.h | 114 ++-
1 file changed, 113 insertions(+), 1 deletion(-)
diff --git a/include/block/nvme.h b/inc
On 08/12/20 20:57, Paolo Bonzini wrote:
On 08/12/20 20:14, Alejandro Jimenez wrote:
##
+# @reboot-set-action:
+#
+# Set reboot action
+#
+# Since: 6.0
+##
+{ 'command': 'reboot-set-action', 'data' : {'action': 'RebootAction'} }
+
+##
+# @shutdown-set-action:
+#
+# Set shutdown action
+#
+# Sin
From: Eduardo Habkost
Signed-off-by: Eduardo Habkost
[claudio: wrapped in CONFIG_TCG]
Signed-off-by: Claudio Fontana
Reviewed-by: Philippe Mathieu-Daudé
---
accel/tcg/cpu-exec.c| 12 ++--
include/hw/core/cpu.h | 6 --
include/hw/core/tcg-cpu-ops.h | 9 +++
On 12/8/20 8:33 PM, Michael S. Tsirkin wrote:
> The following changes since commit 553032db17440f8de011390e5a1cfddd13751b0b:
>
> Update version for v5.2.0 release (2020-12-08 15:55:19 +)
>
> are available in the Git repository at:
>
> git://git.kernel.org/pub/scm/virt/kvm/mst/qemu.git ta
Zone Descriptor Extension is a label that can be assigned to a zone.
It can be set to an Empty zone and it stays assigned until the zone
is reset.
This commit adds a new optional module property,
"zoned.descr_ext_size". Its value must be a multiple of 64 bytes.
If this value is non-zero, it become
This log page becomes necessary to implement to allow checking for
Zone Append command support in Zoned Namespace Command Set.
This commit adds the code to report this log page for NVM Command
Set only. The parts that are specific to zoned operation will be
added later in the series.
All incoming
On 12/8/20 8:48 PM, Claudio Fontana wrote:
> v8 -> v9: move additional methods to CPUClass->tcg_ops
>
> do_unaligned_access, transaction_failed and do_interrupt.
>
> do_interrupt is a bit tricky, as the same code is reused
> (albeit not usually directly) for KVM under certain odd conditions.
>
>
Signed-off-by: Claudio Fontana
---
hw/mips/jazz.c| 4 ++--
include/hw/core/cpu.h | 18 +++---
include/hw/core/tcg-cpu-ops.h | 9 +
target/alpha/cpu.c| 2 +-
target/arm/cpu.c | 4 ++--
target/m68k/cpu.c | 2 +-
t
cc->do_interrupt is in theory a TCG callback used in accel/tcg only,
to prepare the emulated architecture to take an interrupt as defined
in the hardware specifications,
but in reality the _do_interrupt style of functions in targets are
also occasionally reused by KVM to prepare the architecture s
In NVMe 1.4, a namespace must report an ID descriptor of UUID type
if it doesn't support EUI64 or NGUID. Add a new namespace property,
"uuid", that provides the user the option to either specify the UUID
explicitly or have a UUID generated automatically every time a
namespace is initialized.
Sugge
From: Niklas Cassel
Define the structures and constants required to implement
Namespace Types support.
Namespace Types introduce a new command set, "I/O Command Sets",
that allows the host to retrieve the command sets associated with
a namespace. Introduce support for the command set and enable
centralize the calls to cpu->accel_cpu_interface
Signed-off-by: Claudio Fontana
---
hw/core/cpu.c | 9 +
include/hw/core/cpu.h | 6 ++
target/i386/cpu.c | 9 ++---
3 files changed, 17 insertions(+), 7 deletions(-)
diff --git a/hw/core/cpu.c b/hw/core/cpu.c
index f41c
Move write processing to nvme_do_write() that now handles both WRITE
and WRITE ZEROES. Both nvme_write() and nvme_write_zeroes() become
inline helper functions.
Signed-off-by: Dmitry Fomichev
Reviewed-by: Niklas Cassel
Acked-by: Klaus Jensen
---
hw/block/nvme.c | 78 -
Added brief descriptions of the new device properties that are
now available to users to configure features of Zoned Namespace
Command Set in the emulator.
This patch is for documentation only, no functionality change.
Signed-off-by: Dmitry Fomichev
Reviewed-by: Niklas Cassel
---
hw/block/nvme
On Dec 08 17:56, Alex Bennée wrote:
> Aaron Lindsay writes:
> > On Dec 08 12:17, Alex Bennée wrote:
> >> For registers I think there needs to be some re-factoring of QEMU's
> >> internals to do it cleanly. Currently we have each front-end providing
> >> hooks to the gdbstub as well as buildi
The emulation code has been changed to advertise NVM Command Set when
"zoned" device property is not set (default) and Zoned Namespace
Command Set otherwise.
Define values and structures that are needed to support Zoned
Namespace Command Set (NVMe TP 4053) in PCI NVMe controller emulator.
Define t
On Tue, Dec 08, 2020 at 08:53:19PM +0100, Philippe Mathieu-Daudé wrote:
> On 12/8/20 8:33 PM, Michael S. Tsirkin wrote:
> > The following changes since commit 553032db17440f8de011390e5a1cfddd13751b0b:
> >
> > Update version for v5.2.0 release (2020-12-08 15:55:19 +)
> >
> > are available i
Add two module properties, "zoned.max_active" and "zoned.max_open"
to control the maximum number of zones that can be active or open.
Once these variables are set to non-default values, these limits are
checked during I/O and Too Many Active or Too Many Open command status
is returned if they are e
On 12/6/20 10:46 PM, LIU Zhiwei wrote:
> If the split element is also the first active element of the vector,
> mem_off_first[0] should equal to mem_off_split.
>
> Signed-off-by: LIU Zhiwei
> ---
> target/arm/sve_helper.c | 7 ---
> 1 file changed, 4 insertions(+), 3 deletions(-)
>
> diff -
v10 -> v11:
- Address review comments by Klaus.
- Add a patch to separate the handling of controller reset
and subsystem shutdown. Place the patch at the beginning
of the series so it can be picked up separately.
- Rebase on the current nvme-next branch.
v9 -> v10:
- Correctly check
ZNS specification defines two zone conditions for the zones that no
longer can function properly, possibly because of flash wear or other
internal fault. It is useful to be able to "inject" a small number of
such zones for testing purposes.
This commit defines two optional device properties, "offl
Controller reset ans subsystem shutdown are handled very much the same
in the current code, but some of the steps should be different in these
two cases.
Introduce two new functions, nvme_reset_ctrl() and nvme_shutdown_ctrl(),
to separate some portions of the code from nvme_clear_ctrl(). The steps
On Dec 8 20:02, Dmitry Fomichev wrote:
> Hi Klaus,
>
> Thank you for your review! Please see replies below...
>
>
> On Thu, 2020-11-12 at 20:36 +0100, Klaus Jensen wrote:
> > Hi Dmitry,
> >
> > I know you posted v10, but my comments should be relevant to that as
> > well.
> >
> > On Nov 5 11
LSA and LDSA opcodes are also available with MIPS release 6.
Introduce the decodetree config files and call the decode()
helpers in the main decode_opc() loop.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/translate.h | 2 ++
target/mips/isa-mips32r6.decode | 17
On 12/6/20 10:46 PM, LIU Zhiwei wrote:
> First-fault or no-fault doesn't mean only access one page.
But the implementation is *allowed* to access only one page.
Thus the comment:
> -/*
> - * MemSingleNF is allowed to fail for any reason. We have special
> - * code above to handle the
COP1x opcode has been removed from the Release 6.
Add a single decodetree entry for it, triggering
Reserved Instruction if ever used.
Remove unreachable check_insn_opc_removed() call.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/isa-mips32r6.decode | 2 ++
target/mips/translate.c
LLD/SCD opcodes have been removed from the Release 6.
Add a single decodetree entry for the opcodes, triggering
Reserved Instruction if ever used.
Remove unreachable check_insn_opc_removed() calls.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/isa-mips64r6.decode | 3 +++
target/mips/tr
Add the LSA opcode to the MSA32 decodetree config, add DLSA
to a new config for the MSA64 ASE, and call decode_msa64()
in the main decode_opc() loop.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/translate.h | 3 +++
target/mips/mod-msa32.decode| 4
target/mips/mod-msa
Missed in previous "Convert MSA to decodetree" series.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/translate.h | 8 +++-
target/mips/translate.c | 4 ++--
2 files changed, 9 insertions(+), 3 deletions(-)
diff --git a/target/mips/translate.h b/target/mips/translate.h
index cba28f49
On 12/6/20 10:46 PM, LIU Zhiwei wrote:
> From DDI0487Fc_armv8_arm.pdf, the CPTR_EL2 has two kinds
> of layouts according to HCR_EL2.E2H.
>
> When HCR_EL2.E2H is 1, fp_exception_el should refer to
> HCR_EL2.FPEN and sve_exception_el should refer to HCR_EL2.ZEN.
>
> Reviewed-by: Richard Henderson
Special2 opcode have been removed from the Release 6.
Add a single decodetree entry for all the opcode class,
triggering Reserved Instruction if ever used.
Remove unreachable check_insn_opc_removed() call.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/isa-mips32r6.decode | 2 ++
t
LWL/LWR/SWL/SWR opcodes have been removed from the Release 6.
Add a single decodetree entry for the opcodes, triggering
Reserved Instruction if ever used.
Remove unreachable check_insn_opc_removed() calls.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/isa-mips32r6.decode | 5 +
targ
Complete the MSA conversion with the LSA/DLSA opcodes,
which are shared with the Release 6.
Keep going converting the removed opcodes.
We now have 2 decoders on 32-bit, and 4 on 64-bit.
Extensions are decoded first, then ISA.
I might introduce a macro to have a generic decode()
function to hide
CACHE/PREF opcodes have been removed from the Release 6.
Add a single decodetree entry for the opcodes, triggering
Reserved Instruction if ever used.
Remove unreachable check_insn_opc_removed() calls.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/isa-mips32r6.decode | 3 +++
target/mips
LWLE/LWRE/SWLE/SWRE (EVA) opcodes have been removed from
the Release 6. Add a single decodetree entry for the opcodes,
triggering Reserved Instruction if ever used.
Remove unreachable check_insn_opc_removed() calls.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/isa-mips32r6.decode | 5 +
Extract gen_lsa() from translate.c and explode it as
gen_LSA() and gen_DLSA().
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/translate.h| 8 +
target/mips/translate.c| 35 +++
target/mips/translate_addr_const.c | 54 +++
Hello,
On behalf of the QEMU Team, I'd like to announce the availability of
the QEMU 5.2.0 release. This release contains 3200+ commits from 216
authors.
A note from the maintainer:
This is the final release of v5.2.0; there are no changes since rc4.
Note that QEMU has switched build syst
LL/SC opcodes have been removed from the Release 6.
Add a single decodetree entry for the opcodes, triggering
Reserved Instruction if ever used.
Remove unreachable check_insn_opc_removed() calls.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/isa-mips32r6.decode | 2 ++
target/mips/trans
Since we switched to decodetree-generated processing,
we can remove this now unreachable code.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/translate.c | 29 +
1 file changed, 5 insertions(+), 24 deletions(-)
diff --git a/target/mips/translate.c b/target/mip
On 12/6/20 10:46 PM, LIU Zhiwei wrote:
> For SIMD fcmla(by element), if the number of elements is less than
> the number of elements within one segment，i.e. 4H arrangement,
> we should not calculate the entire segment.
>
> Signed-off-by: LIU Zhiwei
> ---
> target/arm/vec_helper.c | 8
>
On 12/6/20 5:39 PM, Philippe Mathieu-Daudé wrote:
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> target/mips/op_helper.c | 4
> 1 file changed, 4 deletions(-)
Reviewed-by: Richard Henderson
r~
LDL/LDR/SDL/SDR opcodes have been removed from the Release 6.
Add a single decodetree entry for the opcodes, triggering
Reserved Instruction if ever used.
Remove unreachable check_insn_opc_removed() calls.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/isa-mips64r6.decode | 6 ++
tar
On 12/6/20 5:39 PM, Philippe Mathieu-Daudé wrote:
> Remove unused headers and add missing "qemu/log.h" since
> qemu_log() is called.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> target/mips/cp0_helper.c | 4 +---
> 1 file changed, 1 insertion(+), 3 deletions(-)
Reviewed-by: Richard Henders
On 12/6/20 5:39 PM, Philippe Mathieu-Daudé wrote:
> The rest of helper.c is TLB related. Extract the non TLB
> specific functions to a new file, so we can rename helper.c
> as tlb_helper.c in the next commit.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> Any better name? xxx_helper.c are usua
On 12/6/20 5:39 PM, Philippe Mathieu-Daudé wrote:
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> target/mips/kvm.c | 2 --
> 1 file changed, 2 deletions(-)
Reviewed-by: Richard Henderson
r~
Add command-line option that lets the SMBIOS entry point type to
be configured.
SMBIOS 3.0 support is necessary to allow us to support more
than 720 VCPUs in x86_64, due to SMBIOS 2.1 table size limits.
Note that it's still up to firmware to decide whether to generate
SMBIOS 2.1 and/or 3.0 entry
On 12/6/20 5:39 PM, Philippe Mathieu-Daudé wrote:
> mips_cpu_do_transaction_failed() requires MemTxAttrs
> and MemTxResult declarations.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> target/mips/internal.h | 1 +
> target/mips/kvm.c | 1 -
> 2 files changed, 1 insertion(+), 1 deletion(-
On 12/8/2020 2:58 PM, Paolo Bonzini wrote:
On 08/12/20 20:57, Paolo Bonzini wrote:
On 08/12/20 20:14, Alejandro Jimenez wrote:
##
+# @reboot-set-action:
+#
+# Set reboot action
+#
+# Since: 6.0
+##
+{ 'command': 'reboot-set-action', 'data' : {'action':
'RebootAction'} }
+
+##
+# @shutdow
On Tue, Dec 08, 2020 at 09:33:39AM +0100, Klaus Jensen wrote:
> +static uint16_t nvme_copy(NvmeCtrl *n, NvmeRequest *req)
> +{
> +for (i = 0; i < nr; i++) {
> +uint32_t _nlb = le16_to_cpu(range[i].nlb) + 1;
> +if (_nlb > le16_to_cpu(ns->id_ns.mssrl)) {
> +return N
On Tue, Dec 08, 2020 at 10:16:58AM +0100, Klaus Jensen wrote:
> From: Klaus Jensen
>
> Commit 37712e00b1f0 ("hw/block/nvme: factor out pmr setup") changed the
> control flow such that the CAP register is erronously cleared after
> nvme_init_pmr() has configured it. Since the entire NvmeCtrl struc
On 12/6/20 5:39 PM, Philippe Mathieu-Daudé wrote:
> Address translation is an architectural thing (not hardware
> related). Move the helpers from hw/ to target/.
>
> As physical address and KVM are specific to system mode
> emulation, restrict this file to softmmu, so it doesn't
> get compiled for
On 12/6/20 5:39 PM, Philippe Mathieu-Daudé wrote:
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> target/mips/internal.h | 1 +
> target/mips/tlb_helper.c | 46 ++
> target/mips/translate_init.c.inc | 48
> 3 files ch
On Thu, Dec 3, 2020 at 4:55 AM Yifei Jiang wrote:
>
> Get isa info from kvm while kvm init.
>
> Signed-off-by: Yifei Jiang
> Signed-off-by: Yipeng Yin
> ---
> target/riscv/kvm.c | 27 ++-
> 1 file changed, 26 insertions(+), 1 deletion(-)
>
> diff --git a/target/riscv/kvm
On 12/6/20 5:39 PM, Philippe Mathieu-Daudé wrote:
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> target/mips/fpu_helper.c | 4
> 1 file changed, 4 deletions(-)
Reviewed-by: Richard Henderson
r~
On 12/7/20 4:10 AM, Stephane Duverger wrote:
> This leads me to that simple reflection:
>
> If we want to filter on every memory accesses, *out of the fast-path*,
> the most natural place to do so would be in store_helper() and
> load_helper() from accel/tcg/cputlb.c. By doing so, every target wou
On 12/6/20 5:39 PM, Philippe Mathieu-Daudé wrote:
> Move cpu_supports*() and cpu_set_exception_base() from
> translate.c to cpu.c.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> target/mips/cpu.c | 18 ++
> target/mips/translate.c | 18 --
> 2 files chang
On Thu, Dec 3, 2020 at 4:57 AM Yifei Jiang wrote:
>
> Currently, time base frequency was fixed as SIFIVE_CLINT_TIMEBASE_FREQ.
> Here introduce "time-frequency" property to set time base frequency
> dynamically
> of which default value is still SIFIVE_CLINT_TIMEBASE_FREQ. The virt machine
> uses f
On 12/6/20 5:39 PM, Philippe Mathieu-Daudé wrote:
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> target/mips/cpu.c| 33 +
> target/mips/helper.c | 33 -
> 2 files changed, 33 insertions(+), 33 deletions(-)
Reviewed-by: Richard
On 12/6/20 5:39 PM, Philippe Mathieu-Daudé wrote:
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> target/mips/cpu.c | 20
> 1 file changed, 8 insertions(+), 12 deletions(-)
Reviewed-by: Richard Henderson
r~
On 12/6/20 5:39 PM, Philippe Mathieu-Daudé wrote:
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> target/mips/translate.c | 2 --
> 1 file changed, 2 deletions(-)
Reviewed-by: Richard Henderson
r~
On 12/6/20 5:39 PM, Philippe Mathieu-Daudé wrote:
> To help understand ifdef'ry, add comment after #endif.
This does more than that.
> @@ -550,9 +552,7 @@ hwaddr mips_cpu_get_phys_page_debug(CPUState *cs, vaddr
> addr)
> }
> return phys_addr;
> }
> -#endif
>
> -#if !defined(CONFIG_U
On Thu, Dec 3, 2020 at 4:47 AM Yifei Jiang wrote:
>
> Only support supervisor external interrupt currently.
>
> Signed-off-by: Yifei Jiang
> Signed-off-by: Yipeng Yin
> ---
> hw/intc/sifive_plic.c| 31 ++-
> target/riscv/kvm.c | 19 +++
> ta
Aaron Lindsay writes:
> On Dec 08 17:56, Alex Bennée wrote:
>> Aaron Lindsay writes:
>> > On Dec 08 12:17, Alex Bennée wrote:
>> >> For registers I think there needs to be some re-factoring of QEMU's
>> >> internals to do it cleanly. Currently we have each front-end providing
>> >> hooks
On 12/6/20 5:39 PM, Philippe Mathieu-Daudé wrote:
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> We are very close to build with '--enable-kvm --disable-tcg' :)
> ---
> target/mips/meson.build | 8 +---
> 1 file changed, 5 insertions(+), 3 deletions(-)
Reviewed-by: Richard Henderson
r~
On 12/6/20 5:39 PM, Philippe Mathieu-Daudé wrote:
> This file contains functions related to TLB management,
> rename it as 'tlb_helper.c'.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> Maybe I missed some functions not TLB specific...
> ---
> target/mips/{helper.c => tlb_helper.c} | 2 +-
>
Patchew URL: https://patchew.org/QEMU/20201208194839.31305-1-cfont...@suse.de/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20201208194839.31305-1-cfont...@suse.de
Subject: [RFC v9 00/22] i386 cleanup
=== TEST SCRIPT
On 12/6/20 5:39 PM, Philippe Mathieu-Daudé wrote:
> We are going to move this code, fix its style first.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> target/mips/translate_init.c.inc | 36
> 1 file changed, 18 insertions(+), 18 deletions(-)
Reviewed-by: Ric
On Tue, Dec 08, 2020 at 03:18:54PM -0600, Richard Henderson wrote:
> As for modifying the fast path cases, the code is quite delicate,
> and you run into problems with live registers. Which could be
> worked around in each backend, but... why?
Perhaps thinking that working at IR level would preve
On Tue, Dec 8, 2020 at 12:52 PM Claudio Fontana wrote:
>
> for now only TCG is allowed as an accelerator for riscv,
> so remove the CONFIG_TCG use.
>
> Signed-off-by: Claudio Fontana
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/cpu.c | 3 +--
> 1 file changed, 1 insertion(+),
On Thu, Nov 26, 2020 at 07:56:05PM +0100, Klaus Jensen wrote:
> From: Gollu Appalanaidu
>
> Add the Compare command.
>
> This implementation uses a bounce buffer to read in the data from
> storage and then compare with the host supplied buffer.
>
> Signed-off-by: Gollu Appalanaidu
> [k.jensen:
On 12/7/20 3:52 PM, Philippe Mathieu-Daudé wrote:
> Philippe Mathieu-Daudé (2):
> target/mips: Rename cpu_supports_FEAT() as cpu_type_supports_FEAT()
> target/mips: Introduce cpu_supports_isa() taking CPUMIPSState argument
Reviewed-by: Richard Henderson
r~
On 12/8/20 9:00 PM, Philippe Mathieu-Daudé wrote:
> On 12/8/20 8:48 PM, Claudio Fontana wrote:
>> v8 -> v9: move additional methods to CPUClass->tcg_ops
>>
>> do_unaligned_access, transaction_failed and do_interrupt.
>>
>> do_interrupt is a bit tricky, as the same code is reused
>> (albeit not usua
On Thu, Dec 3, 2020 at 4:58 AM Yifei Jiang wrote:
>
> Get kernel and fdt start address in virt.c, and pass them to KVM
> when cpu reset. In addition, add kvm_riscv.h to place riscv specific
> interface.
This doesn't seem right. Why do we need to do this? Other
architectures don't seem to do this.
On Thu, Dec 3, 2020 at 4:55 AM Yifei Jiang wrote:
>
> Currently, host cpu is inherited simply.
>
> Signed-off-by: Yifei Jiang
> Signed-off-by: Yipeng Yin
> ---
> target/riscv/cpu.c | 6 ++
> target/riscv/cpu.h | 1 +
> 2 files changed, 7 insertions(+)
>
> diff --git a/target/riscv/cpu.c b/t
On 12/6/20 5:39 PM, Philippe Mathieu-Daudé wrote:
> Nothing TCG specific there, move to common cpu code.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> target/mips/internal.h | 4 -
> target/mips/cpu.c | 243
> target/mips/translate.c | 240 --
On 12/7/20 5:55 PM, Philippe Mathieu-Daudé wrote:
> Extract DisasContext to a new 'translate.h' header so
> different translation files (ISA, ASE, extensions)
> can use it.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> target/mips/translate.h | 50 +
>
On 12/6/20 5:39 PM, Philippe Mathieu-Daudé wrote:
> This file is not TCG specific, contains CPU definitions
> and is consumed by cpu.c. Rename it as such.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> cpu-defs.c still contains fpu_init()/mvp_init()/msa_reset().
> They are moved out in differe
Signed-off-by: Alistair Francis
Reviewed-by: Bin Meng
Tested-by: Bin Meng
---
target/riscv/cpu.h | 6 ++
1 file changed, 6 insertions(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index c0a326c843..9c064f3094 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -44,6 +44,1
Currently the riscv_is_32_bit() function only supports the generic rv32
CPUs. Extend the function to support the SiFive and LowRISC CPUs as
well.
Signed-off-by: Alistair Francis
---
hw/riscv/boot.c | 14 +-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/hw/riscv/boot.c
Signed-off-by: Alistair Francis
Reviewed-by: Bin Meng
Tested-by: Bin Meng
---
include/hw/riscv/boot.h | 8 +++---
hw/riscv/boot.c | 55 ++---
hw/riscv/sifive_u.c | 2 +-
hw/riscv/spike.c| 3 ++-
hw/riscv/virt.c | 2 +-
5 files
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