> Whilst testing a Windows build of git master of qemu-system-ppc in
> MSYS2/MingW64 I noticed the following assertion message in the console after
> booting into OpenBIOS and then closing the GTK GUI window without booting a
> client OS:
>
> $ ./qemu-system-ppc
> **
> ERROR:../util/aio-win32.c:
Hi folks,
Addressing code style issues that were found by patchew.
Also big thanks to Richard Henderson for reviewing the series and giving great
comments!
Thanks
Alexey Baturo (4):
[RISCV_PM] Add J-extension into RISC-V
[RISCV_PM] Support CSRs required for RISC-V PM extension except for
Signed-off-by: Alexey Baturo
---
target/riscv/cpu.c | 1 +
target/riscv/cpu.h | 12 ++
target/riscv/cpu_bits.h | 66 ++
target/riscv/csr.c | 271
4 files changed, 350 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/
Signed-off-by: Alexey Baturo
---
target/riscv/cpu.c | 25 +
1 file changed, 25 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index d63031eb08..5916ebe5c2 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -255,6 +255,31 @@ static void riscv_c
Signed-off-by: Alexey Baturo
---
target/riscv/insn_trans/trans_rva.c.inc | 3 +++
target/riscv/insn_trans/trans_rvd.c.inc | 2 ++
target/riscv/insn_trans/trans_rvf.c.inc | 2 ++
target/riscv/insn_trans/trans_rvi.c.inc | 2 ++
target/riscv/translate.c| 14 ++
5 file
Signed-off-by: Alexey Baturo
---
target/riscv/cpu.c | 4
target/riscv/cpu.h | 2 ++
2 files changed, 6 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 0bbfd7f457..fe6bab4a52 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -438,6 +438,9 @@ static void ris
From: Anatoly Parshintsev
Signed-off-by: Anatoly Parshintsev
---
target/riscv/cpu.h | 19 +++
target/riscv/translate.c | 34 --
2 files changed, 51 insertions(+), 2 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index c23
>> Hi Claudio,
>>
>> is there a reason why you removed current_cpu = cpu; from
>> hax_cpu_thread_fn() when you moved that function to target/i386/hax-cpus.c?
>> This change broke HAX on Windows. Adding back that line makes it work again.
>
> Hello Volker, I see the change in the history and it
On Sat, Oct 17, 2020 at 08:55:34AM +0200, Jann Horn wrote:
> My suggestion is to use a counter *in the UAPI*, not in the hypervisor
> protocol. (And as long as that counter can only miss increments in a
> cryptographically negligible fraction of cases, everything's fine.)
OK I got it now and I agr
> From: Kevin Wolf
>
> This moves the QMP dispatcher to a coroutine and runs all QMP command
> handlers that declare 'coroutine': true in coroutine context so they
> can avoid blocking the main loop while doing I/O or waiting for other
> events.
>
> For commands that are not declared safe to run i
On 10/16/20 11:07 PM, Richard Henderson wrote:
Since the FAR_ELx fix at 38d931687fa1, it is reported that
page granularity flushing is broken.
This makes sense, since TCG will record the entire virtual
address in its TLB, not simply the 56 significant bits.
With no other TCG support, the ARM bac
On 10/16/20 6:50 PM, Philippe Mathieu-Daudé wrote:
On 10/16/20 5:40 PM, Philippe Mathieu-Daudé wrote:
On 10/15/20 1:25 PM, Pavel Dovgalyuk wrote:
This patch adds MIPS-targeted acceptance tests for
record/replay functions.
Signed-off-by: Pavel Dovgalyuk
---
0 files changed
diff --git a/test
On 10/16/20 7:28 PM, Richard Henderson wrote:
On 10/16/20 6:33 AM, Philippe Mathieu-Daudé wrote:
Per "MIPS32 34K Processor Core Family Software User's Manual,
Revision 01.13" page 8 in "Joint TLB (JTLB)" section:
"The JTLB is a fully associative TLB cache containing 16, 32,
or 64-dual-en
On 10/16/20 8:42 PM, Richard Henderson wrote:
Fixing this now will clarify following patches.
Signed-off-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
---
linux-user/elfload.c | 12 +---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/linux-user/elfload
On 10/16/20 8:42 PM, Richard Henderson wrote:
The second loop uses a loop induction variable, and the first
does not. Transform the first to match the second, to simplify
a following patch moving code between them.
Signed-off-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
---
On 10/16/20 8:42 PM, Richard Henderson wrote:
This is a bit clearer than open-coding some of this
with a bare c string.
c -> C?
Signed-off-by: Richard Henderson
---
linux-user/elfload.c | 37 -
1 file changed, 20 insertions(+), 17 deletions(-)
Review
On 10/16/20 8:42 PM, Richard Henderson wrote:
This is slightly clearer than just using strerror, though
the different forms produced by error_setg_file_open and
error_setg_errno isn't entirely convenient.
Signed-off-by: Richard Henderson
---
linux-user/elfload.c | 15 ---
1 file
Signed-off-by: Bihong Yu
---
migration/block.c | 36 ++--
migration/page_cache.c | 13 +++--
migration/trace-events | 13 +
3 files changed, 34 insertions(+), 28 deletions(-)
diff --git a/migration/block.c b/migration/block.c
index 273392b
On 10/16/20 8:27 PM, Mark Cave-Ayland wrote:
This function is no longer used within the codebase.
Signed-off-by: Mark Cave-Ayland
---
hw/rtc/m48t59-isa.c | 25 -
include/hw/rtc/m48t59.h | 2 --
2 files changed, 27 deletions(-)
Reviewed-by: Philippe Mathieu-Dau
On 10/16/20 8:27 PM, Mark Cave-Ayland wrote:
Signed-off-by: Mark Cave-Ayland
---
hw/sparc/sun4m.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/hw/sparc/sun4m.c b/hw/sparc/sun4m.c
index 54a2b2f9ef..a9bb60f2b2 100644
--- a/hw/sparc/sun4m.c
+++ b/hw/sparc/sun4m.c
On 10/16/20 8:27 PM, Mark Cave-Ayland wrote:
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Philippe Mathieu-Daudé
---
hw/sparc64/sun4u.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/hw/sparc64/sun4u.c b/hw/sparc64/sun4u.c
index ad5ca2472a..05e659c8a4 100644
-
On 10/16/20 10:38 PM, BALATON Zoltan via wrote:
On Fri, 16 Oct 2020, Mark Cave-Ayland wrote:
Signed-off-by: Mark Cave-Ayland
---
hw/ppc/ppc405_boards.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c
index 6198ec1035..
On 10/16/20 8:27 PM, Mark Cave-Ayland wrote:
Now that all of the callers of this function have been switched to use qdev
properties, this legacy init function can now be removed.
Signed-off-by: Mark Cave-Ayland
---
hw/rtc/m48t59.c | 35 ---
include/hw/
On 10/17/20 11:35 AM, Bihong Yu wrote:
Signed-off-by: Bihong Yu
---
migration/block.c | 36 ++--
migration/page_cache.c | 13 +++--
migration/trace-events | 13 +
3 files changed, 34 insertions(+), 28 deletions(-)
...
diff --git a/m
On 10/10/20 6:05 PM, Philippe Mathieu-Daudé wrote:
On 10/10/20 3:57 PM, Luc Michel wrote:
PLLs are composed of multiple channels. Each channel outputs one clock
signal. They are modeled as one device taking the PLL generated clock as
input, and outputting a new clock.
A channel shares the CM re
On 10/17/20 11:05 AM, Philippe Mathieu-Daudé wrote:
On 10/16/20 6:50 PM, Philippe Mathieu-Daudé wrote:
On 10/16/20 5:40 PM, Philippe Mathieu-Daudé wrote:
On 10/15/20 1:25 PM, Pavel Dovgalyuk wrote:
This patch adds MIPS-targeted acceptance tests for
record/replay functions.
Signed-off-by: Pave
On Sat, 17 Oct 2020, Philippe Mathieu-Daudé wrote:
On 10/16/20 10:38 PM, BALATON Zoltan via wrote:
On Fri, 16 Oct 2020, Mark Cave-Ayland wrote:
Signed-off-by: Mark Cave-Ayland
---
hw/ppc/ppc405_boards.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/hw/ppc/ppc405_
On Thu, 15 Oct 2020 at 17:45, Eduardo Habkost wrote:
>
> The following changes since commit 57c98ea9acdcef5021f5671efa6475a5794a51c4:
>
> Merge remote-tracking branch 'remotes/kraxel/tags/ui-20201014-pull-request'
> into staging (2020-10-14 13:56:06 +0100)
>
> are available in the Git repositor
On Thu, 15 Oct 2020 at 22:04, Christian Schoenebeck
wrote:
>
> The following changes since commit 57c98ea9acdcef5021f5671efa6475a5794a51c4:
>
> Merge remote-tracking branch 'remotes/kraxel/tags/ui-20201014-pull-request'
> into staging (2020-10-14 13:56:06 +0100)
>
> are available in the Git rep
On Fri, 16 Oct 2020 at 06:28, Gerd Hoffmann wrote:
>
> The following changes since commit 57c98ea9acdcef5021f5671efa6475a5794a51c4:
>
> Merge remote-tracking branch 'remotes/kraxel/tags/ui-20201014-pull-request'
> into staging (2020-10-14 13:56:06 +0100)
>
> are available in the Git repository
On 17/10/2020 10:42, Philippe Mathieu-Daudé wrote:
On 10/16/20 8:27 PM, Mark Cave-Ayland wrote:
Signed-off-by: Mark Cave-Ayland
---
hw/sparc/sun4m.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/hw/sparc/sun4m.c b/hw/sparc/sun4m.c
index 54a2b2f9ef..a9bb60f2b2 10
On 17/10/2020 10:45, Philippe Mathieu-Daudé wrote:
On 10/16/20 10:38 PM, BALATON Zoltan via wrote:
On Fri, 16 Oct 2020, Mark Cave-Ayland wrote:
Signed-off-by: Mark Cave-Ayland
---
hw/ppc/ppc405_boards.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/hw/ppc/ppc405
On 17/10/2020 10:53, Philippe Mathieu-Daudé wrote:
On 10/16/20 8:27 PM, Mark Cave-Ayland wrote:
Now that all of the callers of this function have been switched to use qdev
properties, this legacy init function can now be removed.
Signed-off-by: Mark Cave-Ayland
---
hw/rtc/m48t59.c |
Hi Damien, Peter,
On 4/30/20 1:51 PM, Peter Maydell wrote:
This object may be used to represent a clock inside a clock tree.
A clock may be connected to another clock so that it receives update,
through a callback, whenever the source/parent clock is updated.
Although only the root clock of a
Public bug reported:
Env:
Host: Power9 HW ppc64le
# lscpu
Architecture:ppc64le
Byte Order: Little Endian
CPU(s): 128
On-line CPU(s) list: 24-31,40-159
Thread(s) per core: 4
Core(s) per socket:
Did a git bisect and the bad commit is
acbdb9956fe93f4669141f103cb543d3025775db is the first bad commit
commit acbdb9956fe93f4669141f103cb543d3025775db
Author: Cédric Le Goater
Date: Thu Aug 20 15:45:46 2020 +0200
spapr/xive: Allocate IPIs independently from the other sources
The
On 17/10/2020 11:44, BALATON Zoltan via wrote:
On Sat, 17 Oct 2020, Philippe Mathieu-Daudé wrote:
On 10/16/20 10:38 PM, BALATON Zoltan via wrote:
On Fri, 16 Oct 2020, Mark Cave-Ayland wrote:
Signed-off-by: Mark Cave-Ayland
---
hw/ppc/ppc405_boards.c | 10 +-
1 file changed, 9 insertio
On Samstag, 17. Oktober 2020 12:50:13 CEST Peter Maydell wrote:
> On Thu, 15 Oct 2020 at 22:04, Christian Schoenebeck
>
> wrote:
> > The following changes since commit
57c98ea9acdcef5021f5671efa6475a5794a51c4:
> > Merge remote-tracking branch
> > 'remotes/kraxel/tags/ui-20201014-pull-request
On 16/10/2020 13:19, BALATON Zoltan via wrote:
On Fri, 16 Oct 2020, Mark Cave-Ayland wrote:
On 16/10/2020 00:47, BALATON Zoltan via wrote:
This is the cut down version of the earlier series omitting unfinished
patches that I plan to rework later and rebased to Mark's qemu-macppc
branch. Compar
On Sat, 17 Oct 2020 at 12:55, Christian Schoenebeck
wrote:
> Oops, get_current_dir_name() is a GNU extension. I just enabled Cirrus-CI to
> prevent this from happening again. Sorry Peter.
>
> Am I supposed to rebase for v2 PRs?
Yeah, just rebase and resend, please.
thanks
-- PMM
On 16/10/2020 01:26, BALATON Zoltan via wrote:
As said in previous message the i2c and SPD patches are not quite ready yet so I've
omitted those from this series, I may rework them later once this part is merged and
can rebase the rest on top of that. We would also need your screamer patches to
On Fri, 16 Oct 2020 at 16:56, Paolo Bonzini wrote:
>
> The following changes since commit 3e40748834923798aa57e3751db13a069e2c617b:
>
> Merge remote-tracking branch 'remotes/rth/tags/pull-mb-20201014' into
> staging (2020-10-15 20:30:24 +0100)
>
> are available in the Git repository at:
>
> h
On Sat, 17 Oct 2020 at 14:09, Peter Maydell wrote:
>
> On Fri, 16 Oct 2020 at 16:56, Paolo Bonzini wrote:
> >
> > The following changes since commit 3e40748834923798aa57e3751db13a069e2c617b:
> >
> > Merge remote-tracking branch 'remotes/rth/tags/pull-mb-20201014' into
> > staging (2020-10-15 2
After discussing this offline with Jann a bit, I have a few general
comments on the design of this.
First, the UUID communicated by the hypervisor should be consumed by
the kernel -- added as another input to the rng -- and then userspace
should be notified that it should reseed any userspace RNGs
On 17/10/20 15:09, Peter Maydell wrote:
> Traceback (most recent call last):
> File "scripts/mtest2make.py", line 37, in
> introspect = json.load(sys.stdin)
> File "/usr/lib/python3.6/json/__init__.py", line 299, in load
> parse_constant=parse_constant, object_pairs_hook=object_pairs_h
On 17/10/20 15:22, Peter Maydell wrote:
> I'm updating various build machines and will give the pullreq a
> retry, but in the meantime:
>
> The NetBSD tests/vm setup fails slightly differently:
>
> ERROR: Could not detect Ninja v1.7 or newer
That's because ninja is apparently a chat program on N
On 10/17/20 1:19 PM, Mark Cave-Ayland wrote:
On 17/10/2020 10:53, Philippe Mathieu-Daudé wrote:
On 10/16/20 8:27 PM, Mark Cave-Ayland wrote:
Now that all of the callers of this function have been switched to
use qdev
properties, this legacy init function can now be removed.
Signed-off-by: Ma
From: Jiaxun Yang
LDC2/SDC2 opcodes have been rewritten as "load & store with offset"
group of instructions by loongson-ext ASE.
This patch add implementation of these instructions:
gslbx: load 1 bytes to GPR
gslhx: load 2 bytes to GPR
gslwx: load 4 bytes to GPR
gsldx: load 8 bytes to G
The following changes since commit 7daf8f8d011cdd5d3e86930ed2bde969425c790c:
Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into staging=
(2020-10-16 17:39:01 +0100)
are available in the Git repository at:
https://gitlab.com/philmd/qemu.git tags/mips-next-2020101
From: Aleksandar Markovic
Remove function definitions via macros to achieve better code clarity.
Signed-off-by: Aleksandar Markovic
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <1602103041-32017-4-git-send-email-aleksandar.qemu.de...@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé
---
ta
Instead of directly aborting, display a hint to help the developer
figure out the problem (likely trying to connect a clock to a device
pre-dating the Clock API, thus not expecting clocks).
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Luc Michel
Reviewed-by: Damien Hedde
Reviewed-by: Edga
From: zhaolichang
There are many spelling errors in the comments in target/mips/.
Use spellcheck to check the spelling errors.
Signed-off-by: zhaolichang
Reviewed-by: David Edmondson
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20201009064449.2336-7-zhaolich...@huawei.com>
Signed-off-by:
Introduce freq_to_str() to convert frequency values in human
friendly units using the SI units for Hertz.
Suggested-by: Luc Michel
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
Reviewed-by: Luc Michel
Message-Id: <20201012095804.3335117-2-f4...@amsat.org>
---
include/qem
From: Jiaxun Yang
LWC2 & SWC2 have been rewritten by Loongson EXT vendor ASE
as "load/store quad word" and "shifted load/store" groups of
instructions.
This patch add implementation of these instructions:
gslwlc1: similar to lwl but RT is FPR instead of GPR
gslwrc1: similar to lwr but RT is
The CP0 timer period is a function of the CPU frequency.
Start using the default values, which will be replaced by
properties in the next commits.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Jiaxun Yang
Message-Id: <20201012095804.3335117-10-f4...@amsat.org>
---
target/mips/cpu.c | 4 ++-
From: Aleksandar Markovic
Remove function definitions via macros to achieve better code clarity.
Signed-off-by: Aleksandar Markovic
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <1602103041-32017-2-git-send-email-aleksandar.qemu.de...@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé
---
ta
From: Luc Michel
This function creates a clock and parents it to another object with a
given name. It calls clock_setup_canonical_path before returning the
new clock.
This function is useful to create clocks in devices when one doesn't
want to expose it at the qdev level (as an input or an outpu
Since not all CPU implementations use a cores use a CP0 timer
at half the frequency of the CPU, make this variable a property.
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20201012095804.3335117-11-f4...@amsat.org>
---
target/mips/cpu.h | 9 +
target/mips/cpu.c | 19 +++---
From: Aleksandar Markovic
Remove function definitions via macros to achieve better code clarity.
Signed-off-by: Aleksandar Markovic
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <1602103041-32017-3-git-send-email-aleksandar.qemu.de...@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé
---
ta
QEMU does not model caches, so there is not much to do with the
Invalidate/Writeback opcodes. Make it explicit adding a comment.
Suggested-by: Jiaxun Yang
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Reviewed-by: Jiaxun Yang
Message-Id: <20200813181527.22551-3-f4...@ams
In case the guest uses a cache opcode we are not expecting,
log it to give us a chance to notice it, in case we should
actually do something.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Reviewed-by: Jiaxun Yang
Message-Id: <20200813181527.22551-4-f4...@amsat.org>
---
t
The Magnum 4000PC CPU runs at 100 MHz, and the Acer PICA-61
CPU at ~134 MHz.
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20201012095804.3335117-17-f4...@amsat.org>
---
hw/mips/jazz.c | 15 ++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/hw/mips/jazz.c b/hw/mi
To avoid the MIPS target being orphan, volunteer to keep an eye
on it and put together pull requests.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Jiaxun Yang
Reviewed-by: Thomas Huth
Message-Id: <20201013101659.3557154-2-f4...@amsat.org>
---
MAINTAINERS | 6 --
1 file changed, 4 ins
The get_random() helper uses the CP0_Wired register, which is
unrelated to the CP0_Count register used as timer.
Commit e16fe40c872 ("Move the MIPS CPU timer in a separate file")
incorrectly moved this get_random() helper with timer specific
code. Move it back to generic CP0 helpers.
Signed-off-by
From: Jiaxun Yang
LWC2 & SWC2 have been rewritten by Loongson EXT vendor ASE
as "load/store quad word" and "shifted load/store" groups of
instructions.
This patch add implementation of these instructions:
gslq: load 16 bytes to GPR
gssq: store 16 bytes from GPR
gslqc1: load 16 bytes to FP
Since 82790064116 ("Cast ELF datatypes properly to host 64bit types")
we don't need to sign-extend the entry_point address. Remove this
unnecessary code.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20200927163943.614604-2-f4...@amsat.org>
---
hw/mips/mipssi
The cache operation is encoded in bits [20:18] of the instruction.
The 'op' argument of helper_cache() contains the bits [20:16].
Extract the 3 bits and parse them using a switch case. This allow
us to handle multiple cache types (the cache type is encoded in
bits [17:16]).
Previously the if() blo
Paul's Wavecomp email has been bouncing for months. He told us
he "no longer has access to modern MIPS CPUs or Boston hardware,
and wouldn't currently have time to spend on them if he did." [1]
but "perhaps that might change in the future." [2].
Be fair and downgrade the status of the Boston board
Name variables holding nanoseconds with the '_ns' suffix.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Aleksandar Markovic
Message-Id: <20201012095804.3335117-7-f4...@amsat.org>
---
target/mips/cp0_timer.c | 19 ++-
1 file changed, 10 insertions(+), 9 deletions(-)
diff --
TIMER_PERIOD value of '10 ns' can be explained looking at
commit 6af0bf9c7c3doc, where the CPU frequency is 200 MHz
and CP0 default count rate is half the frequency of the
CPU. Document that.
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20201012095804.3335117-8-f4...@amsat.org>
---
target/
From: Huacai Chen
Add Loongson-3A CPU models description.
Signed-off-by: Huacai Chen
Message-Id: <1602059975-10115-10-git-send-email-che...@lemote.com>
[PMD: Split patch in 2: CPU / machine]
Signed-off-by: Philippe Mathieu-Daudé
---
docs/system/cpu-models-mips.rst.inc | 10 --
1 file
Currently the CP0 timer period is fixed at 10 ns, corresponding
to a fixed CPU frequency of 200 MHz (using half the speed of the
CPU).
In few commits we will be able to use a different CPU frequency.
In preparation, move the cp0_count_ns variable to CPUMIPSState
so we can modify it.
Signed-off-by
From: Aleksandar Markovic
I have been working on project other than QEMU for some time, and would
like to devote myself to that project. It is impossible for me to find
enough time to perform maintainer's duties with needed meticulousness
and patience.
I wish prosperous future to QEMU and all co
Use the Clock API and let the CPU object have an input clock.
If no clock is connected, keep using the default frequency of
200 MHz used since the introduction of the 'r4k' machine in
commit 6af0bf9c7c3.
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20201012095804.3335117-12-f4...@amsat.org
Since its introduction in commit 6af0bf9c7c3,
the 'r4k' machine runs at 200 MHz.
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20201012095804.3335117-14-f4...@amsat.org>
---
hw/mips/r4k.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/hw/mips/r4k.c b/hw/mips/r4k.c
The CPU frequency is normally provided by the firmware in the
"cpuclock" environment variable. The 2E board can handles up
to 660MHz, but be conservative and take the same value used
by the Linux kernel: 533 MHz.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Jiaxun Yang
Message-Id: <2020101
Introduce an helper to create a MIPS CPU and connect it to
a reference clock. This helper is not MIPS specific, but so
far only MIPS CPUs need it.
Suggested-by: Huacai Chen
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20201012095804.3335117-13-f4...@amsat.org>
---
target/mips/cpu.h | 12 +
The I6400 can run at 1 GHz or more. Create a 'cpuclk'
output clock and connect it to the CPU input clock.
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20201012095804.3335117-19-f4...@amsat.org>
---
hw/mips/boston.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/hw/mips/
All existing 9pfs test cases are using the 'synth' fs driver so far, which
means they are not accessing real files, but a purely simulated (in RAM
only) file system.
Let's make this clear by changing the prefix of the individual qtest case
names from 'fs/' to 'synth/'. That way they'll be easily d
The MIPSsim machine CPU frequency is too fast running at 200 MHz,
while it should be 12 MHz for the 24K and 6 MHz for the 5K core.
Ref: Linux commit c78cbf49c4ed
("Support for MIPSsim, the cycle accurate MIPS simulator.")
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20201012095804.3335117-
The 'empty_slot' region created is related to the gt64120.
Move its creation close to the gt64120 instance creation.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20201012160503.3472140-2-f4...@amsat.org>
---
hw/mips/malta.c | 13 ++---
1 file changed
Expose a qdev input clock named 'clk-in', and connect it to each
core to forward-propagate the clock.
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20201012095804.3335117-18-f4...@amsat.org>
---
include/hw/mips/cps.h | 2 ++
hw/mips/cps.c | 4
2 files changed, 6 insertions(+)
This patch introduces 9pfs test cases using the 9pfs 'local'
filesystem driver which reads/writes/creates/deletes real files
and directories.
In this initial version, there is only one local test which actually
only checks if the 9pfs 'local' device was created successfully.
Before the 9pfs 'loca
The CoreLV card with ID 0x420's CPU clocked at 320 MHz. Create
a 'cpuclk' output clock and connect it to the CPU input clock.
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20201012095804.3335117-20-f4...@amsat.org>
---
hw/mips/malta.c | 19 ---
1 file changed, 16 insertions(
In order to be consistent with the other code base uses,
rewrite slightly how the MIPS_MALTA object is created.
No logical change.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20201012160503.3472140-3-f4...@amsat.org>
---
hw/mips/malta.c | 8
1 file
Before running the first 9pfs test case, make sure the test directory
for running the 9pfs 'local' tests on is entirely empty. For that
reason simply delete the test directory (if any) before (re)creating
it on test suite startup.
Note: The preferable precise behaviour would be the test directory
Now than all QOM users provides the input clock, do not allow
using a CPS without input clock connected.
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20201012095804.3335117-21-f4...@amsat.org>
---
hw/mips/cps.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/hw/mips/cps.c b/hw/mip
Instead of using a INITRD_PAGE_MASK definition, use the
simpler INITRD_PAGE_SIZE one which allows us to simplify
the code by using directly the self-explicit ROUND_UP()
macro.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20200927163943.614604-3-f4...@amsat.or
This new public function virtio_9p_test_path() allows 9pfs
'local' tests to translate a path from guest scope to host
scope. For instance by passing an empty string it would
return the root path on host of the exported 9pfs tree.
Signed-off-by: Christian Schoenebeck
Message-Id:
Signed-off-by: C
From: Pavel Dovgalyuk
This patch updates MIPS-based machines to allow starting them without ROM.
In this case CPU starts to execute instructions from the empty memory,
but QEMU allows introspecting the machine configuration.
Signed-off-by: Pavel Dovgalyuk
Reviewed-by: Philippe Mathieu-Daudé
Me
All our QOM users provides an input clock. In order to avoid
avoid future machines added without clock, display a warning.
User-mode emulation use the CP0 timer with the RDHWR instruction
(see commit cdfcad788394) so keep using the fixed 200 MHz clock
without diplaying any warning. Only display it
From: Pavel Dovgalyuk
This patch adds MIPS-targeted acceptance tests for
record/replay functions.
Signed-off-by: Pavel Dovgalyuk
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
Message-Id: <160276110297.2705.10918105269658307206.stgit@pasha-ThinkPad-X280>
[PMD: Moved 'ov
The FPGA present on the CoreCard has an I/O region 1MiB wide.
Refs:
- Atlas User’s Manual (Document Number: MD5)
- Malta User’s Manual (Document Number: MD00048)
Fixes: ea85df72b60 ("mips_malta: convert to memory API")
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20200905213049.761949-
gs/pull-9p-20201017
for you to fetch changes up to fa4551e3f4416cc8c62086ac430b1ceb4f03eb6b:
tests/9pfs: add local Tmkdir test (2020-10-17 15:58:39 +0200)
9pfs: add tests using local fs driver
The currently existing 9pfs test cas
From: Eduardo Habkost
This will make the type name constant consistent with the name of
the type checking macro.
Signed-off-by: Eduardo Habkost
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
Message-Id: <20200902224311.1321159-19-ehabk...@redhat.com>
Signed-off-by: Phil
Hi Jens.
On Sat, Oct 17, 2020 at 3:07 AM Jens Axboe wrote:
>
> Would be great if you could try 5.4.71 and see if that helps for your
> issue.
>
Oh wow, yeah it did fix the issue.
I'm able to reliably turn off and start the VM multiple times in a row.
Double checked by confirming QEMU is dynamic
The Malta tests are already covered in the Malta section.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Thomas Huth
Message-Id: <20201013101659.3557154-3-f4...@amsat.org>
---
MAINTAINERS | 2 --
1 file changed, 2 deletions(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 8770cd6d05a..a7f0a
On Sat, 17 Oct 2020 at 14:38, Paolo Bonzini wrote:
> OpenBSD and NetBSD call the ninja package "ninja-build" unlike FreeBSD.
> I'm sure I had used the right name but well I didn't. I'll send a v3.
OpenBSD built OK but meson produces this new warning:
Library iconv found: NO
../src/meson.build:
Per "MIPS32 34K Processor Core Family Software User's Manual,
Revision 01.13" page 8 in "Joint TLB (JTLB)" section:
"The JTLB is a fully associative TLB cache containing 16, 32,
or 64-dual-entries mapping up to 128 virtual pages to their
corresponding physical addresses."
There is no part
This test case uses the 9pfs 'local' driver to create a directory
and then checks if the expected directory was actually created
(as real directory) on host side.
This patch introduces a custom split() implementation, because
the test code requires non empty array elements as result. For
that reas
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