As we want to make the number of TLB entries configurable,
store it in CPUMIPSState. Introduce the init_tlb_entries()
helper which initializes it from the CP0C1_MMU config content.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/cpu.h| 1 +
target/mips/translate.c
To be able to propagate error to our caller, make
cpu_mips_realize_env() take an Error argument and
return a boolean value indicating an error is set or
not, following the example documented since commit
e3fe3988d7 ("error: Document Error API usage rules").
Signed-off-by: Philippe Mathieu-Daudé
-
Per "MIPS32 34K Processor Core Family Software User's Manual,
Revision 01.13" page 8 in "Joint TLB (JTLB)" section:
"The JTLB is a fully associative TLB cache containing 16, 32,
or 64-dual-entries mapping up to 128 virtual pages to their
corresponding physical addresses."
Add these values
On Thu, Oct 15, 2020 at 7:39 PM Volker Rümelin wrote:
>
> >
> > Thanks Paolo,
> >
> > Then only the issue regarding the pcbios/optionrom stuff remains ;-)
> >
> > make[1]: *** No rule to make target 'multiboot.bin', needed by 'all'.
> Stop.
> > make: *** [Makefile:171: pc-bios/optionrom/all] Erro
The board firmware expect these to be at fixed addresses and programs
them without probing, this patch puts the macio device at the expected
PCI address.
Signed-off-by: BALATON Zoltan
Reviewed-by: Mark Cave-Ayland
---
hw/ppc/mac_oldworld.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Half of the occurances already use get_system_memory() directly
instead of sysmem variable, convert the two other uses to
get_system_memory() too which seems to be more common and drop the
variable.
Signed-off-by: BALATON Zoltan
Reviewed-by: Mark Cave-Ayland
Reviewed-by: Philippe Mathieu-Daudé
Values not used frequently enough may not worth putting in a local
variable, especially with names almost as long as the original value
because that does not improve readability, to the contrary it makes it
harder to see what value is used. Drop a few such variables.
Signed-off-by: BALATON Zoltan
This is the cut down version of the earlier series omitting unfinished
patches that I plan to rework later and rebased to Mark's qemu-macppc
branch. Compared to v7 the only change is the cast to (target_ulong)
from (uint32_t) as requested by Mark in patch 1.
Regards,
BALATON Zoltan
BALATON Zoltan
Fall back to load binary ROM image if loading ELF fails. This also
moves PROM_BASE and PROM_SIZE defines to board as these are matching
the ROM size and address on this board and removes the now unused
PROM_ADDR and BIOS_SIZE defines from common mac.h.
Signed-off-by: BALATON Zoltan
Reviewed-by: P
The beige G3 Power Macintosh has a 4MB firmware ROM. Fix the size of
the rom region and fall back to loading a binary image with -bios if
loading ELF image failed. This allows testing emulation with a ROM
image from real hardware as well as using an ELF OpenBIOS image.
Signed-off-by: BALATON Zolta
On Thu, 15 Oct 2020, Mark Cave-Ayland wrote:
I've queued the grackle/uninorth patches to my qemu-macppc branch, however
when I try to apply patches from the above series git fails with the
following message:
Applying: mac_oldworld: Drop a variable, use get_system_memory() directly
error: sha1
On Thu, Oct 15, 2020 at 11:03:18PM +0200, Laurent Vivier wrote:
> If we hotplug a CPU during the first second of the kernel boot,
> the IRQ can be sent to the kernel while the RTAS event handler
> is not installed. The event is queued, but the kernel doesn't
> collect it and ignores the new CPU.
>
On Tue, Oct 13, 2020 at 12:49:21PM +0100, Mark Cave-Ayland wrote:
> Currently an object link property is used to pass a reference to the Heathrow
> PIC into the PCI host bridge so that grackle_init_irqs() can connect the PCI
> IRQs to the PIC itself.
>
> This can be simplified by defining the PCI
On Tue, Oct 13, 2020 at 12:49:22PM +0100, Mark Cave-Ayland wrote:
> Currently an object link property is used to pass a reference to the OpenPIC
> into the PCI host bridge so that pci_unin_init_irqs() can connect the PCI
> IRQs to the PIC itself.
>
> This can be simplified by defining the PCI IRQs
On Tue, Oct 13, 2020 at 12:49:20PM +0100, Mark Cave-Ayland wrote:
> Instead use qdev_prop_set_chr() to configure the ESCC serial chardevs at the
> Mac Old World and New World machine level.
>
> Also remove the now obsolete comment referring to the use of serial_hd() and
> the setting of user_creat
On Tue, Oct 13, 2020 at 05:58:52PM +0100, Mark Cave-Ayland wrote:
> On 13/10/2020 14:38, BALATON Zoltan via wrote:
>
> > On Tue, 13 Oct 2020, Mark Cave-Ayland wrote:
> > > Currently an object link property is used to pass a reference to the
> > > OpenPIC
> > > into the PCI host bridge so that pci
On Wed, Oct 14, 2020 at 07:15:47AM -0700, Elena Afanasova wrote:
> On Tue, 2020-10-13 at 16:32 +1100, David Gibson wrote:
> > On Mon, Oct 12, 2020 at 03:45:02PM +0200, Paolo Bonzini wrote:
> > > On 12/10/20 12:44, Thomas Huth wrote:
> > > > I think this is one of the tasks from:
> > > >
> > > >
On Tue, Oct 13, 2020 at 09:33:44AM +0200, Greg Kurz wrote:
> On Tue, 13 Oct 2020 11:40:14 +1100
> David Gibson wrote:
>
> > On Mon, Oct 12, 2020 at 12:15:21PM +0200, Greg Kurz wrote:
> > > The spapr_create_nvdimm_dr_connectors() function doesn't need to access
> > > any internal details of the sP
On 10/10/2020 10:27 AM, cenjiahui wrote:
Hi Kevin,
Could you please spend some time reviewing and commenting on this patch series.
Thanks,
Jiahui Cen
This feature is confirmed effective in a cloud storage environment since
it can help to improve the availability without pausing the entire
On Thu, Oct 15, 2020 at 09:46:47PM +0200, Philippe Mathieu-Daudé wrote:
> Pass a MemoryRegion* to m48t59_init(), directly call
> memory_region_add_subregion() instead of sysbus_mmio_map().
>
> Signed-off-by: Philippe Mathieu-Daudé
ppc parts
Acked-by: David Gibson
> ---
> include/hw/rtc/m48t5
On 2020/9/25 下午11:13, Cindy Lu wrote:
If the peer's type is vdpa, we need to set the mac address to hardware
in virtio_net_device_realize,
Signed-off-by: Cindy Lu
---
hw/net/virtio-net.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/hw/net/virtio-net.c b/hw/net/virtio-net.c
ind
On 2020/10/15 下午3:58, Zhang, Chen wrote:
-Original Message-
From: Jason Wang
Sent: Thursday, October 15, 2020 3:56 PM
To: Zhang, Chen ; qemu-dev
Cc: Zhang Chen
Subject: Re: [PATCH 00/10] COLO project queued patches 20-Oct
On 2020/10/14 下午3:25, Zhang Chen wrote:
From: Zhang Chen
On Fri, Oct 16, 2020 at 6:19 AM Paolo Bonzini wrote:
>
>
>
> Il ven 16 ott 2020, 00:06 Yonggang Luo ha scritto:
>>
>> meson didn't support running ../scripts/kernel-do directly
>
>
> Can you explain why this matters? Meson does not look at docs/conf.py.
>
> Paolo
>
>>
>> Signed-off-by: Yonggang L
Fix the bug that while Check qemu supported netdev,
there is no vhost-vdpa
Signed-off-by: Cindy Lu
---
net/net.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/net/net.c b/net/net.c
index 7a2a0fb5ac..794c652282 100644
--- a/net/net.c
+++ b/net/net.c
@@ -1049,6 +1049,9 @@ static void show
fix the bug that fd will still open after the cleanup
Signed-off-by: Cindy Lu
---
net/vhost-vdpa.c | 4
1 file changed, 4 insertions(+)
diff --git a/net/vhost-vdpa.c b/net/vhost-vdpa.c
index bc0e0d2d35..0480b92102 100644
--- a/net/vhost-vdpa.c
+++ b/net/vhost-vdpa.c
@@ -144,6 +144,10 @@ st
Am Sun, 4 Oct 2020 20:25:06 +0200
schrieb Philippe Mathieu-Daudé :
> These individual contributors have a number of contributions,
> add them to the 'individual' group map.
>
> Cc: Ahmed Karaman
> Cc: Aleksandar Markovic
> Cc: Alistair Francis
> Cc: Artyom Tarasenko
> Cc: David Carlier
> Cc
> -Original Message-
> From: Jason Wang
> Sent: Friday, October 16, 2020 10:24 AM
> To: Zhang, Chen ; qemu-dev de...@nongnu.org>
> Cc: Zhang Chen
> Subject: Re: [PATCH 00/10] COLO project queued patches 20-Oct
>
>
> On 2020/10/15 下午3:58, Zhang, Chen wrote:
> >
> >> -Original Mess
From: Paul Zimmerman
Change several assert()s to qemu_log_mask(LOG_GUEST_ERROR...),
to prevent the guest from causing Qemu to assert. Also fix up
several existing qemu_log_mask()s to include the function name in
the message.
Suggested-by: Peter Maydell
Signed-off-by: Paul Zimmerman
Message-id:
From: Anthony PERARD via
The EHCI Host Controller emulation attempt to locate the device
associated with a periodic isochronous transfer description (iTD) and
when this fail the host controller is reset.
But according the EHCI spec 1.0 section 5.15.2.4 Host System
Error, the host controller is s
The following changes since commit 57c98ea9acdcef5021f5671efa6475a5794a51c4:
Merge remote-tracking branch 'remotes/kraxel/tags/ui-20201014-pull-request'
into staging (2020-10-14 13:56:06 +0100)
are available in the Git repository at:
git://git.kraxel.org/qemu tags/usb-20201016-pull-request
From: Mauro Matteo Cascella
Check the value of mps to avoid potential divide-by-zero later in the function.
Since HCCHAR_MPS is guest controllable, this prevents a malicious/buggy guest
from crashing the QEMU process on the host.
Signed-off-by: Mauro Matteo Cascella
Reviewed-by: Paul Zimmerman
From: Zhang Chen
Hi Jason, this series include latest COLO related patches.
please check and merge it.
Li Zhijian (2):
colo-compare: fix missing compare_seq initialization
colo-compare: check mark in mutual exclusion
Pan Nengyuan (1):
net/filter-rewriter: destroy g_hash_table in colo_rewr
From: "Rao, Lei"
The seq of tcp has been filled in fill_pkt_tcp_info, it
can be used directly here.
Signed-off-by: Lei Rao
Signed-off-by: Zhang Chen
Reviewed-by: Li Zhijian
Reviewed-by: Zhang Chen
---
net/colo-compare.c | 7 ++-
1 file changed, 2 insertions(+), 5 deletions(-)
diff --gi
From: Zhang Chen
This parameter need compare with the return of qemu_clock_get_ms(),
it is uint64_t. So we need fix this issue here.
Fixes: 9cc43c94b31 ("net/colo-compare.c: Expose "compare_timeout" to users")
Reported-by: Derek Su
Signed-off-by: Zhang Chen
Reviewed-by: Li Zhijian
Reviewed-b
From: Pan Nengyuan
s->connection_track_table forgot to destroy in colo_rewriter_cleanup. Fix it.
Reported-by: Euler Robot
Signed-off-by: Pan Nengyuan
Signed-off-by: Zhang Chen
Reviewed-by: Zhang Chen
Reviewed-by: Li Qiang
---
net/filter-rewriter.c | 2 ++
1 file changed, 2 insertions(+)
d
From: "Rao, Lei"
In COLO mode, if the startup parameters of QEMU include "no-shutdown",
QEMU will crash when the guest shutdown. The root cause is when the
guest shutdown, the state of VM will switch COLO to SHUTDOWN. When do
checkpoint again, the state will be changed to COLO. But the state
swit
From: Li Zhijian
Signed-off-by: Li Zhijian
Signed-off-by: Zhang Chen
Reviewed-by: Zhang Chen
---
net/colo-compare.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/net/colo-compare.c b/net/colo-compare.c
index a35c10fb59..8d476bbd99 100644
--- a/net/colo-compare.c
++
From: "Rao, Lei"
we should set ram_bulk_stage to false after ram_state_init,
otherwise the bitmap will be unused in migration_bitmap_find_dirty.
all pages in ram cache will be flushed to the ram of secondary guest
for each checkpoint.
Signed-off-by: Lei Rao
Signed-off-by: Derek Su
Signed-off-b
From: Li Zhijian
Fixes: f449c9e549c ("colo: compare the packet based on the tcp sequence
number")
Signed-off-by: Li Zhijian
Signed-off-by: Zhang Chen
Reviewed-by: Zhang Chen
Reviewed-by: Philippe Mathieu-Daudé
---
net/colo.c | 5 +
1 file changed, 1 insertion(+), 4 deletions(-)
diff --
From: Zhang Chen
The virtual clock only runs during the emulation. It stops
when the virtual machine is stopped.
The host clock should be used for device models that emulate accurate
real time sources. It will continue to run when the virtual machine
is suspended. COLO need to know the host time
From: Zhang Chen
Detect queued secondary packet to sync VM state in time.
Signed-off-by: Zhang Chen
Reviewed-by: Li Zhijian
---
net/colo-compare.c | 25 -
1 file changed, 16 insertions(+), 9 deletions(-)
diff --git a/net/colo-compare.c b/net/colo-compare.c
index 12632
From: Zhang Chen
In my test, use this default parameter looks better.
Signed-off-by: Zhang Chen
---
net/colo-compare.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/net/colo-compare.c b/net/colo-compare.c
index 0c87fd9e33..337025b44f 100644
--- a/net/colo-compare.c
+++ b/
Not even reverting the patch worked for me, and it's still broken on
qemu 5.1.
For example:
~/OSS/qemu/ppc-softmmu/qemu-system-ppc -machine mpc8544ds -nographic
-cpu e500mc -serial mon:stdio -kernel zImage -initrd rootfs.ird -append
'console=ttyS0,115200' -device e1000,netdev=main -netdev
hubport
On Fri, Oct 16, 2020 at 2:30 AM David Gibson
wrote:
> On Tue, Oct 13, 2020 at 12:49:21PM +0100, Mark Cave-Ayland wrote:
> > Currently an object link property is used to pass a reference to the
> Heathrow
> > PIC into the PCI host bridge so that grackle_init_irqs() can connect the
> PCI
> > IRQs t
> From: Claudio Fontana
>
> register a "CpusAccel" interface for HAX as well.
>
> diff --git a/softmmu/cpus.c b/softmmu/cpus.c
> index 9fa73735a2..900fff827a 100644
> --- a/softmmu/cpus.c
> +++ b/softmmu/cpus.c
> @@ -416,35 +403,6 @@ void qemu_wait_io_event(CPUState *cpu)
> qemu_wait_io_even
Loongson-3 CPU family include Loongson-3A R1/R2/R3/R4 and Loongson-3B
R1/R2. Loongson-3A R1 is the oldest and its ISA is the smallest, while
Loongson-3A R4 is the newest and its ISA is almost the superset of all
others. To reduce complexity, in QEMU we just define two CPU types:
1, "Loongson-3A100
From: Jiaxun Yang
Our current code assumed the target page size is always 4k
when handling PageMask and VPN2, however, variable page size
was just added to mips target and that's no longer true.
Fixes: ee3863b9d414 ("target/mips: Support variable page size")
Signed-off-by: Jiaxun Yang
Signed-of
From: Jiaxun Yang
LWC2 & SWC2 have been rewritten by Loongson EXT vendor ASE
as "load/store quad word" and "shifted load/store" groups of
instructions.
This patch add implementation of these instructions:
gslq: load 16 bytes to GPR
gssq: store 16 bytes from GPR
gslqc1: load 16 bytes to FPR
gssqc
On 16/10/2020 07:45, Howard Spoelstra wrote:
Hi,
I see compilation of the current ppc-for-5.2 branch fail with:
../hw/pci-host/grackle.c: In function ‘grackle_realize’:
../hw/pci-host/grackle.c:68:11: error: ‘GrackleState’ has no member named ‘pic’
68 | if (!s->pic) {
|
Preparing to add Loongson-3 machine support, add Loongson-3's LEFI (a
UEFI-like interface for BIOS-Kernel boot parameters) helpers first.
Signed-off-by: Huacai Chen
Co-developed-by: Jiaxun Yang
---
hw/mips/loongson3_bootp.c | 162 +++
hw/mips/loongson3_bootp.h | 225
Add Loongson-3 based machine support, it use liointc as the interrupt
controler and use GPEX as the pci controller. Currently it can work with
both TCG and KVM.
As the machine model is not based on any exiting physical hardware, the
name of the machine is "loongson3-virt". It may be superseded in
Add Loongson-3A CPU models and Loongson-3 based machine description.
Signed-off-by: Huacai Chen
---
docs/system/cpu-models-mips.rst.inc | 10 --
docs/system/target-mips.rst | 10 ++
2 files changed, 18 insertions(+), 2 deletions(-)
diff --git a/docs/system/cpu-models-mip
From: Jiaxun Yang
LWC2 & SWC2 have been rewritten by Loongson EXT vendor ASE
as "load/store quad word" and "shifted load/store" groups of
instructions.
This patch add implementation of these instructions:
gslwlc1: similar to lwl but RT is FPR instead of GPR
gslwrc1: similar to lwr but RT is FPR
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