Re: [PATCH v3 11/16] scripts/oss-fuzz: Add general-fuzzer build script

On 201008 0935, Paolo Bonzini wrote: > On 21/09/20 04:25, Alexander Bulekov wrote: > > This parses a yaml file containing general-fuzzer configs and builds a > > separate oss-fuzz wrapper binary for each one, changing some > > preprocessor macros for each configuration. To avoid dealing with > > es

Re: Kernel patch cases qemu live migration failed.

On 2020-10-15 14:35, Andrew Jones wrote: On Thu, Oct 15, 2020 at 12:26:10PM +0100, Marc Zyngier wrote: Hi Please don't use my arm.com address anymore, nobody reads it... On 2020-10-15 05:06, 张东旭 wrote: > I'm so sorry for disturbing you. > > When I apply this kernel patch：KVM: arm64/sve: System

Re: [PATCH v5] Add a comment in bios-tables-test.c to clarify the reason behind approach

On 15/10/2020 13.28, Ani Sinha wrote: > > > On Mon, Oct 12, 2020 at 19:43 Thomas Huth > wrote: > > On 12/10/2020 16.07, Ani Sinha wrote: > > Request to queue this patch with the next pull. > > I can take it via qtest-next in case Michael / Igor do not plan

Re: [PATCH v4 00/16] Add a General Virtual Device Fuzzer

Patchew URL: https://patchew.org/QEMU/20201015134137.205958-1-alx...@bu.edu/ Hi, This series seems to have some coding style problems. See output below for more information: Type: series Message-id: 20201015134137.205958-1-alx...@bu.edu Subject: [PATCH v4 00/16] Add a General Virtual Device Fu

Re: [PATCH v5 2/2] hw/arm/sbsa-ref: add SBSA watchdog device

On Wed, Oct 14, 2020 at 01:04:43PM -0400, Shashi Mallela wrote: > This was added as a placeholder for the virt requirement suggested by Maxim > earlier.Agreed that this fdt otherwise has no significance for sbsa-ref > platform nor is being used by ACPI table created for wdt. > > -Shashi > > On We

[PATCH v3 2/3] accel/tcg: split tcg_start_vcpu_thread

after the initial split into 3 tcg variants, we proceed to also split tcg_start_vcpu_thread. We actually split it in 2 this time, since the icount variant just uses the round robin function. Suggested-by: Richard Henderson Signed-off-by: Claudio Fontana --- accel/tcg/tcg-all.c | 5 +++

[PATCH v3 3/3] accel/tcg: rename tcg-cpus functions to match module name

Signed-off-by: Claudio Fontana Reviewed-by: Philippe Mathieu-Daudé --- accel/tcg/tcg-cpus-icount.c | 24 ++-- accel/tcg/tcg-cpus-icount.h | 6 +-- accel/tcg/tcg-cpus-mttcg.c | 10 ++--- accel/tcg/tcg-cpus-rr.c | 74 ++--- accel/tcg/tcg-cpus-rr.h

[PATCH v3 0/3] tcg-cpus: split into 3 tcg variants

The purpose of this series is to split the tcg-cpus into 3 variants: tcg_cpus_mttcg(multithreaded tcg vcpus) tcg_cpus_rr (single threaded round robin vcpus) tcg_cpus_icount (same as RR, but using icount) Ciao, Claudio v2 -> v3: * comments: remove some, replace "vcpu" with "vCPU" (P

[PATCH v3 1/3] accel/tcg: split CpusAccel into three TCG variants

split up the CpusAccel tcg_cpus into three TCG variants: tcg_cpus_rr (single threaded, round robin cpus) tcg_cpus_icount (same as rr, but with instruction counting enabled) tcg_cpus_mttcg (multi-threaded cpus) Suggested-by: Richard Henderson Signed-off-by: Claudio Fontana Reviewed-by: Richard H

Re: [PATCH v4 04/16] fuzz: Add DMA support to the generic-fuzzer

On 201015 0941, Alexander Bulekov wrote: > When a virtual-device tries to access some buffer in memory over DMA, we > add call-backs into the fuzzer(next commit). The fuzzer checks verifies > that the DMA request maps to a physical RAM address and fills the memory > with fuzzer-provided data. The p

[PATCH v5] sev: add sev-inject-launch-secret

From: Tobin Feldman-Fitzthum AMD SEV allows a guest owner to inject a secret blob into the memory of a virtual machine. The secret is encrypted with the SEV Transport Encryption Key and integrity is guaranteed with the Transport Integrity Key. Although QEMU facilitates the injection of the launch

Re: [PATCH v5] sev: add sev-inject-launch-secret

On 10/15/20 9:37 AM, to...@linux.ibm.com wrote: > From: Tobin Feldman-Fitzthum > > AMD SEV allows a guest owner to inject a secret blob > into the memory of a virtual machine. The secret is > encrypted with the SEV Transport Encryption Key and > integrity is guaranteed with the Transport Integri

Re: Kernel patch cases qemu live migration failed.

On Thu, Oct 15, 2020 at 02:52:34PM +0100, Marc Zyngier wrote: > On 2020-10-15 14:35, Andrew Jones wrote: > > On Thu, Oct 15, 2020 at 12:26:10PM +0100, Marc Zyngier wrote: > > > Hi > > > > > > Please don't use my arm.com address anymore, nobody reads it... > > > > > > On 2020-10-15 05:06, 张东旭 wrot

Re: [PATCH v2 02/20] fuse: Allow exporting BDSs via FUSE

On 15.10.20 10:57, Kevin Wolf wrote: > Am 22.09.2020 um 12:49 hat Max Reitz geschrieben: >> block-export-add type=fuse allows mounting block graph nodes via FUSE on >> some existing regular file. That file should then appears like a raw >> disk image, and accesses to it result in accesses to the e

[PATCH] Makefile: Ensure cscope.out/tags/TAGS are generated in the source tree

Tools usually expect the index files to be in the source tree, eg. emacs. This is already the case when doing out-of-tree builds, but with in-tree builds they end up in the build directory. Force cscope, ctags and etags to put them in the source tree. Signed-off-by: Greg Kurz --- Makefile | 1

[PULL 03/10] keyval: Fix parsing of ',' in value of implied key

From: Markus Armbruster The previous commit demonstrated documentation and code disagree on parsing of ',' in the value of an implied key. Fix the code to match the documentation. This breaks uses of keyval_parse() that pass an implied key and accept a value containing ','. None of the existin

[PULL 05/10] qom: Factor out helpers from user_creatable_print_help()

This creates separate helper functions for printing a list of user creatable object types and for printing a list of properties of a given type. This will allow using these parts without having a QemuOpts. Signed-off-by: Kevin Wolf Reviewed-by: Eric Blake Reviewed-by: Markus Armbruster Message-

[PULL 00/10] Block layer patches

The following changes since commit 57c98ea9acdcef5021f5671efa6475a5794a51c4: Merge remote-tracking branch 'remotes/kraxel/tags/ui-20201014-pull-request' into staging (2020-10-14 13:56:06 +0100) are available in the Git repository at: git://repo.or.cz/qemu/kevin.git tags/for-upstream for yo

[PULL 01/10] keyval: Fix and clarify grammar

From: Markus Armbruster The grammar has a few issues: * key-fragment = / [^=,.]* / Prose restricts key fragments: they "must be valid QAPI names or consist only of decimal digits". Technically, '' consists only of decimal digits. The code rejects that. Fix the grammar. * val

[PULL 04/10] keyval: Parse help options

This adds a special meaning for 'help' and '?' as options to the keyval parser. Instead of being an error (because of a missing value) or a value for an implied key, they now request help, which is a new boolean output of the parser in addition to the QDict. A new parameter 'p_help' is added to ke

[PULL 06/10] qom: Add user_creatable_print_help_from_qdict()

This adds a function that, given a QDict of non-help options, prints help for user creatable objects. Signed-off-by: Kevin Wolf Reviewed-by: Eric Blake Reviewed-by: Markus Armbruster Message-Id: <20201007164903.282198-4-kw...@redhat.com> Signed-off-by: Kevin Wolf --- include/qom/object_interf

[PULL 02/10] test-keyval: Demonstrate misparse of ', ' with implied key

From: Markus Armbruster Add a test for "val,,ue" with implied key. Documentation says this should parse as implied key with value "val", then fail. The code parses it as implied key with value "val,ue", then succeeds. The next commit will fix it. Signed-off-by: Markus Armbruster Message-Id:

[PULL 08/10] monitor: Fix order in monitor_cleanup()

We can only destroy Monitor objects after we're sure that they are not in use by the dispatcher coroutine any more. This fixes crashes like the following where we tried to destroy a monitor mutex while the dispatcher coroutine still holds it: (gdb) bt #0 0x7fe541cf4bc5 in raise () at /lib64

[PULL 09/10] block: drop moderated sheepdog mailing list from MAINTAINERS file

From: Daniel P. Berrangé The sheepdog mailing list is setup to stop and queue messages from non-subscribers, pending moderator approval. Unfortunately it seems that the moderation queue is not actively dealt with. Even when messages are approved, the sender is never added to the whitelist, so eve

[PULL 07/10] qemu-storage-daemon: Remove QemuOpts from --object parser

The command line parser for --object parses the input twice: Once into QemuOpts just for detecting help options, and then again into a QDict using the keyval parser for actually creating the object. Now that the keyval parser can also detect help options, we can simplify this and remove the QemuOp

[PULL 10/10] block: deprecate the sheepdog block driver

From: Daniel P. Berrangé This thread from a little over a year ago: http://lists.wpkg.org/pipermail/sheepdog/2019-March/thread.html states that sheepdog is no longer actively developed. The only mentioned users are some companies who are said to have it for legacy reasons with plans to replac

Re: [PATCH v5] Add a comment in bios-tables-test.c to clarify the reason behind approach

On Thu, Oct 15, 2020 at 7:29 PM Thomas Huth wrote: > > On 15/10/2020 13.28, Ani Sinha wrote: > > > > > > On Mon, Oct 12, 2020 at 19:43 Thomas Huth > > wrote: > > > > On 12/10/2020 16.07, Ani Sinha wrote: > > > Request to queue this patch with the next pull. > > >

Re: [PATCH v3] qom: code hardening - have bound checking while looping with integer value

Ping ... On Mon, Oct 12, 2020 at 8:08 PM Ani Sinha wrote: > > Request to queue this patch for the next pull. > > On Mon, Sep 21, 2020 at 15:03 Ani Sinha wrote: >> >> Object property insertion code iterates over an integer to get an unused >> index that can be used as an unique name for an object

Re: [PATCH v2] Adding ani's email as an individual contributor

Ping ... On Mon, Oct 12, 2020 at 8:27 PM Ani Sinha wrote: > > Request to queue this patch for the next pull. > > On Wed, Oct 7, 2020 at 23:25 Philippe Mathieu-Daudé wrote: >> >> On 10/7/20 6:19 PM, Ani Sinha wrote: >> > Ani is an individual contributor into qemu project. Adding my email into >>

Re: Kernel patch cases qemu live migration failed.

On Thu, 15 Oct 2020 at 15:41, Andrew Jones wrote: > The reporter states neither the source nor destination hardware supports > SVE. My guess is that what's happening is the reserved ID register > ID_UNALLOCATED(4,4) was showing up in the KVM_GET_REG_LIST count on > the old kernel, but the new kern

Re: [PATCH] Makefile: Ensure cscope.out/tags/TAGS are generated in the source tree

On 15/10/20 16:49, Greg Kurz wrote: > Tools usually expect the index files to be in the source tree, eg. emacs. > This is already the case when doing out-of-tree builds, but with in-tree > builds they end up in the build directory. > > Force cscope, ctags and etags to put them in the source tree.

[PATCH] build: add --enable/--disable-libudev

Initially, libudev detection was bundled with --enable-mpath because qemu-pr-helper was the only user of libudev. Recently however the USB U2F emulation has also started using libudev, so add a separate option. This also allows 1) disabling libudev if desired for static builds and 2) for non-stat

[PATCH 1/2] hw/core/ptimer: Support ptimer being disabled by timer callback

In ptimer_reload(), we call the callback function provided by the timer device that is using the ptimer. This callback might disable the ptimer. The code mostly handles this correctly, except that we'll still print the warning about "Timer with delta zero, disabling" if the now-disabled timer hap

[PATCH 0/2] armv7m_systick: Rewrite to use ptimers

This patch series rewrites our implementation of the armv7m systick timer to use ptimers. The armv7m systick timer is a 24-bit decrementing, wrap-on-zero, clear-on-write counter. Our current implementation has various bugs and dubious workarounds in it (for instance see https://bugs.launchpad.net

[PATCH 2/2] hw/timer/armv7m_systick: Rewrite to use ptimers

The armv7m systick timer is a 24-bit decrementing, wrap-on-zero, clear-on-write counter. Our current implementation has various bugs and dubious workarounds in it (for instance see https://bugs.launchpad.net/qemu/+bug/1872237). We have an implementation of a simple decrementing counter and we put

Re: [PATCH v2 03/20] fuse: Implement standard FUSE operations

On 15.10.20 11:46, Kevin Wolf wrote: > Am 22.09.2020 um 12:49 hat Max Reitz geschrieben: >> This makes the export actually useful instead of only producing errors >> whenever it is accessed. >> >> Signed-off-by: Max Reitz >> --- >> block/export/fuse.c | 226 +++

Re: [PATCH v5 2/2] hw/arm/sbsa-ref: add SBSA watchdog device

On Thu, 15 Oct 2020 at 17:12, Graeme Gregory wrote: > > On Wed, Oct 14, 2020 at 01:04:43PM -0400, Shashi Mallela wrote: > > This was added as a placeholder for the virt requirement suggested by Maxim > > earlier.Agreed that this fdt otherwise has no significance for sbsa-ref > > platform nor is be

[PATCH v2 1/5] [RISCV_PM] Add J-extension into RISC-V

Signed-off-by: Alexey Baturo --- target/riscv/cpu.c | 4 target/riscv/cpu.h | 2 ++ 2 files changed, 6 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 0bbfd7f457..fe6bab4a52 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -438,6 +438,9 @@ static void ris

[PATCH v2 3/5] [RISCV_PM] Print new PM CSRs in QEMU logs

Signed-off-by: Alexey Baturo --- target/riscv/cpu.c | 19 +++ 1 file changed, 19 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index d63031eb08..6ba3e98508 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -255,6 +255,25 @@ static void riscv_cpu_dum

Re: [PATCH v2 04/20] fuse: Allow growable exports

On 15.10.20 12:41, Kevin Wolf wrote: > Am 22.09.2020 um 12:49 hat Max Reitz geschrieben: >> These will behave more like normal files in that writes beyond the EOF >> will automatically grow the export size. >> >> Signed-off-by: Max Reitz >> --- >> qapi/block-export.json | 6 +- >> block/expo

[PATCH v2 4/5] [RISCV_PM] Support pointer masking for RISC-V for i/c/f/d/a types of instructions

Signed-off-by: Alexey Baturo --- target/riscv/insn_trans/trans_rva.c.inc | 3 +++ target/riscv/insn_trans/trans_rvd.c.inc | 2 ++ target/riscv/insn_trans/trans_rvf.c.inc | 2 ++ target/riscv/insn_trans/trans_rvi.c.inc | 2 ++ target/riscv/translate.c| 14 ++ 5 file

[PATCH v2 5/5] [RISCV_PM] Implement address masking functions required for RISC-V Pointer Masking extension

From: Anatoly Parshintsev Signed-off-by: Anatoly Parshintsev --- target/riscv/cpu.h | 19 +++ target/riscv/translate.c | 39 +-- 2 files changed, 56 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h inde

[PATCH v2 2/5] [RISCV_PM] Support CSRs required for RISC-V PM extension except for ones in hypervisor mode

Signed-off-by: Alexey Baturo --- target/riscv/cpu.c | 1 + target/riscv/cpu.h | 11 ++ target/riscv/cpu_bits.h | 66 ++ target/riscv/csr.c | 277 4 files changed, 355 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/

Re: [PATCH v2 17/20] iotests: Give access to the qemu-storage-daemon

On 15.10.20 13:27, Kevin Wolf wrote: > Am 22.09.2020 um 12:49 hat Max Reitz geschrieben: >> Signed-off-by: Max Reitz >> --- >> tests/qemu-iotests/check | 11 +++ >> tests/qemu-iotests/common.rc | 17 + >> 2 files changed, 28 insertions(+) >> >> diff --git a/tests/qemu-

[Bug 1872237] Re: SysTick reload behavior emulated incorrectly

I believe this bug should be fixed by this patchset, which rewrites the systick implementation to use a 'ptimer' down-counter instead of rolling its own buggy version: https://patchew.org/QEMU/20201015151829.14656-1-peter.mayd...@linaro.org/ ** Changed in: qemu Status: New => In Progress

Re: [PATCH 4/5] [RISCV_PM] Add address masking functions required for RISC-V Pointer Masking extension

Hi folks, I've sent new v2 patches where, I hope, I managed to address all the comments and suggestions that were provided. Thanks! ср, 14 окт. 2020 г. в 23:10, Alexey Baturo : > > I suggest adding a stub version of this function to patch 5, and then > swap patch 4 and patch 5. > Thanks, will do

Re: [PATCH v2 18/20] iotests: Allow testing FUSE exports

On 15.10.20 13:43, Kevin Wolf wrote: > Am 22.09.2020 um 12:49 hat Max Reitz geschrieben: >> This pretends FUSE exports are a kind of protocol. As such, they are >> always tested under the format node. This is probably the best way to >> test them, actually, because this will generate more I/O loa

Re: [PATCH v2 02/20] fuse: Allow exporting BDSs via FUSE

Am 15.10.2020 um 16:46 hat Max Reitz geschrieben: > On 15.10.20 10:57, Kevin Wolf wrote: > > Am 22.09.2020 um 12:49 hat Max Reitz geschrieben: > >> block-export-add type=fuse allows mounting block graph nodes via FUSE on > >> some existing regular file. That file should then appears like a raw > >

Re: [PATCH 2/2] hw/timer/armv7m_systick: Rewrite to use ptimers

On Thu, 15 Oct 2020 at 16:18, Peter Maydell wrote: > > The armv7m systick timer is a 24-bit decrementing, wrap-on-zero, > clear-on-write counter. Our current implementation has various > bugs and dubious workarounds in it (for instance see > https://bugs.launchpad.net/qemu/+bug/1872237). ...and 1

Re: [PATCH v11 09/13] copy-on-read: skip non-guest reads if no copy needed

On 14.10.20 18:39, Vladimir Sementsov-Ogievskiy wrote: > 14.10.2020 19:30, Max Reitz wrote: >> On 14.10.20 17:22, Vladimir Sementsov-Ogievskiy wrote: >>> 14.10.2020 15:51, Max Reitz wrote: On 12.10.20 19:43, Andrey Shinkevich wrote: > If the flag BDRV_REQ_PREFETCH was set, pass it further

Re: [PATCH v11 05/13] copy-on-read: limit COR operations to base in COR driver

On 14.10.20 20:57, Andrey Shinkevich wrote: > On 14.10.2020 15:01, Max Reitz wrote: >> On 12.10.20 19:43, Andrey Shinkevich wrote: >>> Limit COR operations by the base node in the backing chain when the >>> overlay base node name is given. It will be useful for a block stream >>> job when the COR-f

Re: [PATCH v2 03/20] fuse: Implement standard FUSE operations

Am 15.10.2020 um 17:18 hat Max Reitz geschrieben: > On 15.10.20 11:46, Kevin Wolf wrote: > > Am 22.09.2020 um 12:49 hat Max Reitz geschrieben: > >> This makes the export actually useful instead of only producing errors > >> whenever it is accessed. > >> > >> Signed-off-by: Max Reitz > >> +/** > >

Re: [PATCH v2 02/20] fuse: Allow exporting BDSs via FUSE

On 15.10.20 17:41, Kevin Wolf wrote: > Am 15.10.2020 um 16:46 hat Max Reitz geschrieben: >> On 15.10.20 10:57, Kevin Wolf wrote: >>> Am 22.09.2020 um 12:49 hat Max Reitz geschrieben: [...] +static void fuse_export_shutdown(BlockExport *blk_exp) +{ +FuseExport *exp = container_o

Re: [PATCH] docs: Print warning when running Sphinx 3.x and newer

On Thu, Oct 15, 2020 at 01:38:49PM +0100, Peter Maydell wrote: > On Wed, 14 Oct 2020 at 23:34, Eduardo Habkost wrote: > > > > This won't prevent the docs from being built, but will let people > > know Sphinx 3.x is not fully supported yet. > > > > Signed-off-by: Eduardo Habkost > > Sphinx 3.0.1

[PATCH v2 2/2] qga: add ssh-{add,remove}-authorized-keys

From: Marc-André Lureau Add new commands to add and remove SSH public keys from ~/.ssh/authorized_keys. I took a different approach for testing, including the unit tests right with the code. I wanted to overwrite the function to get the user details, I couldn't easily do that over QMP. Furthermo

[PATCH v2 1/2] glib-compat: add g_unix_get_passwd_entry_qemu()

From: Marc-André Lureau The glib function was introduced in 2.64. It's a safer version of getpwnam, and also simpler to use than getpwnam_r. Currently, it's only use by the next patch in qemu-ga, which doesn't (well well...) need the thread safety guarantees. Since the fallback version is still

Re: [PATCH v2 03/20] fuse: Implement standard FUSE operations

On 15.10.20 17:58, Kevin Wolf wrote: > Am 15.10.2020 um 17:18 hat Max Reitz geschrieben: >> On 15.10.20 11:46, Kevin Wolf wrote: >>> Am 22.09.2020 um 12:49 hat Max Reitz geschrieben: This makes the export actually useful instead of only producing errors whenever it is accessed.

[PATCH v2 0/2] qemu-ga: add ssh-{add,remove}-authorized-keys

From: Marc-André Lureau Hi, Add two new commands to help modify ~/.ssh/authorized_keys. Although it's possible already to modify the authorized_keys files via file-{read,write} or exec, the commands are often denied by default, and the logic is left to the client. Let's add specific commands fo

Re: [RFC 1/5] block/nvme: use some NVME_CAP_* macros

Hi Philippe, On 10/15/20 3:36 PM, Philippe Mathieu-Daudé wrote: > On 10/15/20 3:32 PM, Philippe Mathieu-Daudé wrote: >> On 10/15/20 3:29 PM, Philippe Mathieu-Daudé wrote: >>> On 10/15/20 1:52 PM, Eric Auger wrote: let's use NVME_CAP_DSTRD, NVME_CAP_MPSMIN and NVME_CAP_TO macros Sign

Re: [RFC 0/5] NVMe passthrough: Support 64kB page host

Hi Philippe, On 10/15/20 3:49 PM, Philippe Mathieu-Daudé wrote: > On 10/15/20 1:52 PM, Eric Auger wrote: >> This series allows NVMe passthrough on aarch64 with 64kB page host. >> Addresses and sizes of buffers which are VFIO DMA mapped are >> aligned with the host page size. >> >> nvme_register_bu

[PATCH v2 0/5] RISC-V Pointer Masking implementation

Hi all, This patch series adresses comments and suggestions from v1. I hope that I managedd to address all of them. Thanks Alexey Baturo (4): [RISCV_PM] Add J-extension into RISC-V [RISCV_PM] Support CSRs required for RISC-V PM extension except for ones in hypervisor mode [RISCV_PM] Pr

Re: [PATCH v2 0/2] qemu-ga: add ssh-{add,remove}-authorized-keys

Patchew URL: https://patchew.org/QEMU/20201015160819.1471144-1-marcandre.lur...@redhat.com/ Hi, This series seems to have some coding style problems. See output below for more information: Type: series Message-id: 20201015160819.1471144-1-marcandre.lur...@redhat.com Subject: [PATCH v2 0/2] qe

[PATCH v6 0/2] Add watchdog support for SbsaQemu

This patch series adds watchdog timer support for SbsaQemu platform. The watchdog timer has been implemented first based on the generic watchdog timer specifications from ARM BSA v0.9 and then used in the SbsaQemu reference platform Changes in v6: - removed the fdt code for wdt as it has no sign

[PATCH v6 1/2] hw/watchdog: Implement SBSA watchdog device

Generic watchdog device model has been implemented as per ARM BSAv0.9 Signed-off-by: Shashi Mallela --- hw/arm/Kconfig | 1 + hw/watchdog/Kconfig | 4 + hw/watchdog/meson.build | 1 + hw/watchdog/wdt_sbsa_gwdt.c | 346 +++

[PATCH v6 2/2] hw/arm/sbsa-ref: add SBSA watchdog device

Included the newly implemented SBSA generic watchdog device model into SBSA platform Signed-off-by: Shashi Mallela --- hw/arm/sbsa-ref.c | 24 1 file changed, 24 insertions(+) diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c index 01863510d0f5..671859ec9711 100644 ---

[PULL 1/9] i386: drop x86_cpu_get_supported_feature_word() forward declaration

From: Vitaly Kuznetsov We only use x86_cpu_get_supported_feature_word() after its implementation, no forward declaration needed. Signed-off-by: Vitaly Kuznetsov Message-Id: <20200904145431.196885-3-vkuzn...@redhat.com> Signed-off-by: Eduardo Habkost --- target/i386/cpu.c | 3 --- 1 file chang

[PULL 3/9] target/i386: Remove core_id assert check in CPUID 0x8000001E

From: Babu Moger With x2apic enabled, configurations can have more that 255 cores. Noticed the device add test is hitting an assert when during cpu hotplug with core_id > 255. This is due to assert check in the CPUID 0x801E. Remove the assert check and fix the problem. Fixes the bug: Link:

[PULL 2/9] i386/kvm: fix FEATURE_HYPERV_EDX value in hyperv_passthrough case

From: Zhenyu Wang Fix typo to use correct edx value for FEATURE_HYPERV_EDX when hyperv_passthrough is enabled. Signed-off-by: Zhenyu Wang Message-Id: <20190820103030.12515-1-zhen...@linux.intel.com> Fixes: e48ddcc6ce13 ("i386/kvm: implement 'hv-passthrough' mode") Signed-off-by: Eduardo Habkost

[PULL 0/9] x86 queue, 2020-10-15

The following changes since commit 57c98ea9acdcef5021f5671efa6475a5794a51c4: Merge remote-tracking branch 'remotes/kraxel/tags/ui-20201014-pull-request' into staging (2020-10-14 13:56:06 +0100) are available in the Git repository at: git://github.com/ehabkost/qemu.git tags/x86-next-pull-req

[PULL 7/9] kvm: Correct documentation of kvm_irqchip_*()

When split irqchip support was introduced, the meaning of kvm_irqchip_in_kernel() changed: now it only means the LAPIC is in kernel. The PIC, IOAPIC, and PIT might be in userspace if irqchip=split was set. Update the doc comment to reflect that. While at it, remove the "the user asked us" part i

[PULL 9/9] i386: Mark Icelake-Client CPU models deprecated

From: Robert Hoo Icelake-Client CPU models will be removed in the future. Signed-off-by: Robert Hoo Message-Id: <1600758855-80046-2-git-send-email-robert...@linux.intel.com> [ehabkost: reword deprecation note, fix version in doc] Signed-off-by: Eduardo Habkost --- docs/system/deprecated.rst |

[PULL 8/9] cpu: Introduce CPU model deprecation API

From: Robert Hoo Implement the ability of marking some versions deprecated. When that CPU model is chosen, print a warning. The warning message can be customized, e.g. suggesting an alternative CPU model to be used instead. The deprecation message will be printed by x86_cpu_list_entry(), e.g. '

[PULL 4/9] i386/kvm: Require KVM_CAP_IRQ_ROUTING

KVM_CAP_IRQ_ROUTING is available since 2009 (Linux v2.6.30), so it's safe to just make it a requirement on x86. Signed-off-by: Eduardo Habkost Acked-by: Paolo Bonzini Message-Id: <20200922201922.2153598-2-ehabk...@redhat.com> Signed-off-by: Eduardo Habkost --- target/i386/kvm.c | 5 + 1 fi

[PATCH 2/9] qapi: move gen_if/gen_endif to IfCond

From: Marc-André Lureau Move the generating function to the IfCond class. (avoid cluttering and potential missuse of global functions, allow access to private members etc) Signed-off-by: Marc-André Lureau --- scripts/qapi/common.py | 22 ++ scripts/qapi/gen.py|

Re: [PATCH v2 2/5] [RISCV_PM] Support CSRs required for RISC-V PM extension except for ones in hypervisor mode

On 10/15/20 8:21 AM, Alexey Baturo wrote: > +/* Functions to access Pointer Masking feature registers > + * We have to check if current priv lvl could modify > + * csr in given mode > + */ > +static int check_pm_current_disabled(CPURISCVState *env, int csrno) > +{ > +/* m-mode is always allowe

[PULL 5/9] i386/kvm: Remove IRQ routing support checks

KVM_CAP_IRQ_ROUTING is always available on x86, so replace checks for kvm_has_gsi_routing() and KVM_CAP_IRQ_ROUTING with asserts. Signed-off-by: Eduardo Habkost Acked-by: Paolo Bonzini Message-Id: <20200922201922.2153598-3-ehabk...@redhat.com> Signed-off-by: Eduardo Habkost --- hw/i386/kvm/api

Re: [PATCH v2 00/20] block/export: Allow exporting BDSs via FUSE

On 15.10.20 14:01, Kevin Wolf wrote: > Am 22.09.2020 um 12:49 hat Max Reitz geschrieben: >> Based-on: <20200907182011.521007-1-kw...@redhat.com> >> (“block/export: Add infrastructure and QAPI for block exports”) >> >> (Though its patch 16 needs a s/= \&blk_exp_nbd/= drv/ on top.) >> >> v1

[PATCH 3/9] qapi: start building an 'if' predicate tree

From: Marc-André Lureau The following patches are going to express conditions in some target language agostic way. For that, let's start building a predicate tree of configuration options. The tree will be less expressive than full C macros expressions, and will be based only on identifier. For

[PULL 6/9] i386/kvm: Delete kvm_allows_irq0_override()

As IRQ routing is always available on x86, kvm_allows_irq0_override() will always return true, so we don't need the function anymore. Signed-off-by: Eduardo Habkost Acked-by: Paolo Bonzini Message-Id: <20200922201922.2153598-4-ehabk...@redhat.com> Signed-off-by: Eduardo Habkost --- target/i386

Re: [PATCH v3] qom: code hardening - have bound checking while looping with integer value

On Mon, Sep 21, 2020 at 03:03:25PM +0530, Ani Sinha wrote: > Object property insertion code iterates over an integer to get an unused > index that can be used as an unique name for an object property. This loop > increments the integer value indefinitely. Although very unlikely, this can > still ca

[PATCH 4/9] qapi: introduce IfPredicateList and IfAny

From: Marc-André Lureau Generalize IfAll to allow 'any' conditions. Signed-off-by: Marc-André Lureau --- scripts/qapi/common.py | 20 1 file changed, 16 insertions(+), 4 deletions(-) diff --git a/scripts/qapi/common.py b/scripts/qapi/common.py index 29e0697c27..f5166e0bad

[PATCH 5/9] qapi: add IfNot

From: Marc-André Lureau Signed-off-by: Marc-André Lureau --- scripts/qapi/common.py | 19 +++ 1 file changed, 19 insertions(+) diff --git a/scripts/qapi/common.py b/scripts/qapi/common.py index f5166e0bad..566913d69e 100644 --- a/scripts/qapi/common.py +++ b/scripts/qapi/common

[PATCH 0/9] qapi: untie 'if' conditions from C preprocessor

From: Marc-André Lureau Hi, This series makes the 'if' conditions less liberal, by formalizing a simple expression tree based on bare boolean logic of configure option identifiers. (this will allow to express conditions in Rust in my QAPI-Rust PoC series, but it is worth a standalone post) Thi

[PATCH 1/9] qapi: replace List[str] by IfCond

From: Marc-André Lureau Wrap the 'if' condition in a higher-level object. Not only this is allows more type safety but also further refactoring without too much chrun. The following patches will extend the syntax of 'if' and will have some extra handling and types. Signed-off-by: Marc-André Lure

[PATCH 7/9] qapi: convert 'if' C expressions to literal form

From: Marc-André Lureau Signed-off-by: Marc-André Lureau --- qapi/machine-target.json | 20 qapi/misc-target.json| 13 - 2 files changed, 28 insertions(+), 5 deletions(-) diff --git a/qapi/machine-target.json b/qapi/machine-target.json index 698850cc78..de5

[PATCH 6/9] qapi: normalize 'if' condition to IfPredicate

From: Marc-André Lureau Signed-off-by: Marc-André Lureau --- scripts/qapi/common.py| 5 +- scripts/qapi/expr.py | 55 --- tests/qapi-schema/bad-if.err | 3 +- tests/qapi-schema/doc-good.out| 12 +

Re: [PATCH v2 02/20] fuse: Allow exporting BDSs via FUSE

Am 15.10.2020 um 17:59 hat Max Reitz geschrieben: > On 15.10.20 17:41, Kevin Wolf wrote: > > Am 15.10.2020 um 16:46 hat Max Reitz geschrieben: > >> On 15.10.20 10:57, Kevin Wolf wrote: > >>> Am 22.09.2020 um 12:49 hat Max Reitz geschrieben: > > [...] > > +static void fuse_export_shutdown(Blo

Re: [PATCH v2 5/5] [RISCV_PM] Implement address masking functions required for RISC-V Pointer Masking extension

On 10/15/20 8:21 AM, Alexey Baturo wrote: > +switch (priv) { > +case PRV_U: > +pm_enabled = env->mmte & U_PM_ENABLE; > +break; > +case PRV_S: > +pm_enabled = env->mmte & S_PM_ENABLE; > +break; > +case PRV_M: > +

[PATCH 9/9] docs: update the documentation about schema configuration

From: Marc-André Lureau Signed-off-by: Marc-André Lureau --- docs/devel/qapi-code-gen.txt | 26 +++--- 1 file changed, 15 insertions(+), 11 deletions(-) diff --git a/docs/devel/qapi-code-gen.txt b/docs/devel/qapi-code-gen.txt index 3d22a7ae21..517bc29507 100644 --- a/docs/d

[PATCH 8/9] qapi: make 'if' condition strings simple identifiers

From: Marc-André Lureau Change the 'if' condition strings to be C-agnostic and be simple identifiers. Signed-off-by: Marc-André Lureau --- docs/devel/qapi-code-gen.txt | 8 +-- qapi/block-core.json | 16 ++--- qapi/char.json

Re: [PATCH v2 4/5] [RISCV_PM] Support pointer masking for RISC-V for i/c/f/d/a types of instructions

On 10/15/20 8:21 AM, Alexey Baturo wrote: > Signed-off-by: Alexey Baturo > --- > target/riscv/insn_trans/trans_rva.c.inc | 3 +++ > target/riscv/insn_trans/trans_rvd.c.inc | 2 ++ > target/riscv/insn_trans/trans_rvf.c.inc | 2 ++ > target/riscv/insn_trans/trans_rvi.c.inc | 2 ++ > target/risc

Re: [PATCH 9/9] docs: update the documentation about schema configuration

On Thu, Oct 15, 2020 at 8:54 PM wrote: > > From: Marc-André Lureau > > Signed-off-by: Marc-André Lureau > --- > docs/devel/qapi-code-gen.txt | 26 +++--- > 1 file changed, 15 insertions(+), 11 deletions(-) > > diff --git a/docs/devel/qapi-code-gen.txt b/docs/devel/qapi-code-

Re: [PATCH v2] fuzz: Disable QEMU's SIG{INT,HUP,TERM} handlers

On 14/10/20 16:21, Alexander Bulekov wrote: > Prior to this patch, the only way I found to terminate the fuzzer was > either to: > 1. Explicitly specify the number of fuzzer runs with the -runs= flag > 2. SIGKILL the process with "pkill -9 qemu-fuzz-*" or similar > > In addition to being annoyin

Re: [PATCH v11 13/13] block: apply COR-filter to block-stream jobs

On 14.10.2020 19:24, Max Reitz wrote: On 12.10.20 19:43, Andrey Shinkevich wrote: [...] --- block/stream.c | 93 +- tests/qemu-iotests/030 | 51 +++-- tests/qemu-iotests/030.out | 4 +- tests/qemu-iotests/14

Re: [PATCH] meson.build: don't condition iconv detection on library detection

On 15/10/20 00:19, Bruce Rogers wrote: > It isn't necessarily the case that use of iconv requires an additional > library. For that reason we shouldn't conditionalize iconv detection on > libiconv.found. > > Fixes: 5285e593c33 (configure: Fixes ncursesw detection under msys2/mingw by > convert th

Re: [PATCH v2 00/10] softfloat: Implement float128_muladd

Ping. On 9/25/20 8:20 AM, Richard Henderson wrote: > Plus assorted cleanups, passes tests/fp/fp-test. > > Changes in v2: > * Add UInt256 type (david) > * Rewrite and inline shift256RightJamming. This keeps the whole > UInt256 in registers, avoiding long sequences of loads and stores. >

Re: [PATCH v2 2/5] [RISCV_PM] Support CSRs required for RISC-V PM extension except for ones in hypervisor mode

Richard, again thanks for the review! > This is a bit clumsy. I suggest Sure, will fix. > If you try to read this on current hardware, without J, then you get an exception not zero. If I get the spec right, the idea is to read 0 from PM CSRs even if this extension is not present. >I would have

Re: [PATCH v2 4/5] [RISCV_PM] Support pointer masking for RISC-V for i/c/f/d/a types of instructions

That's a great question, but unfortunately, I don't have an answer for it now. Let me ask it on J WG meeting that would happen next Monday along with extension naming and CSR numbers(hopefuly). Thanks! чт, 15 окт. 2020 г. в 20:00, Richard Henderson : > On 10/15/20 8:21 AM, Alexey Baturo wrote: >

Re: [PATCH v2 5/5] [RISCV_PM] Implement address masking functions required for RISC-V Pointer Masking extension

> g_assert_not_reached(); Would fix, thanks. > bool Would fix. >!s->pm_enabled Same. > Don't need the if. Would remove, thanks. > And should it in fact be placed outside the ifdef? Sure, you're right. Richard, thank you for your time and effort reviewing these changes! чт, 15 окт. 2020 г. в 2

Re: [PATCH v11 05/13] copy-on-read: limit COR operations to base in COR driver

On 15.10.2020 18:56, Max Reitz wrote: On 14.10.20 20:57, Andrey Shinkevich wrote: On 14.10.2020 15:01, Max Reitz wrote: On 12.10.20 19:43, Andrey Shinkevich wrote: Limit COR operations by the base node in the backing chain when the overlay base node name is given. It will be useful for a block

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