The emulation code has been changed to advertise NVM Command Set when
"zoned" device property is not set (default) and Zoned Namespace
Command Set otherwise.
Define values and structures that are needed to support Zoned
Namespace Command Set (NVMe TP 4053) in PCI NVMe controller emulator.
Define t
On 2020-10-12 12:49, Daniel P. Berrangé wrote:
On Mon, Oct 12, 2020 at 05:21:15PM +0100, Dr. David Alan Gilbert wrote:
* Tobin Feldman-Fitzthum (to...@linux.vnet.ibm.com) wrote:
> AMD SEV allows a guest owner to inject a secret blob
> into the memory of a virtual machine. The secret is
> encrypt
On Tue, 13 Oct 2020, Philippe Mathieu-Daudé wrote:
On 6/29/20 8:55 PM, BALATON Zoltan wrote:
OpenBIOS gets RAM size via fw_cfg but rhe original board firmware
Typo "the".
detects RAM using SPD data so generate and add SDP eeproms to cover as
EEPROMs?
much RAM as possible to describe with
We can easily register allocate the entire extended basic block
(in this case, the set of blocks connected by fallthru), simply
by not discarding the register state at the branch.
This does not help blocks starting with a label, as they are
reached via a taken branch, and that would require saving
In several cases, it's easy to optimize across a non-taken branch
simply by *not* flushing the relevant tables. This is true both
for value propagation and register allocation.
This comes up in quite a number of cases with arm, most simply in
how conditional execution is implemented. But it also
We can easily propagate temp values through the entire extended
basic block (in this case, the set of blocks connected by fallthru),
simply by not discarding the register state at the branch.
Signed-off-by: Richard Henderson
---
tcg/optimize.c | 35 ++-
1 file cha
On Wed, 14 Oct 2020, BALATON Zoltan via wrote:
On Tue, 13 Oct 2020, Philippe Mathieu-Daudé wrote:
On 6/29/20 8:55 PM, BALATON Zoltan wrote:
This patch is more complex as it should be which I intend to fix once
agreement can be made on how to get back the necessary functionality
removed by previ
On 10/12/20 8:37 AM, Peter Maydell wrote:
> +nextlabel = gen_new_label();
> +tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[a->rn], 0, nextlabel);
> +gen_jmp(s, read_pc(s) + a->imm);
> +
> +gen_set_label(nextlabel);
> +tmp = load_reg(s, a->rn);
> +store_reg(s, 14, tmp);
> +gen_j
Hi Sean,
Thanks much for your detailed replies. It's clear to me why GPAs are
different from HVAs in QEM/KVM. Thanks! I appreciate it if you could
help with the following two more questions.
On Tue, Oct 13, 2020 at 3:03 AM Sean Christopherson
wrote:
>
> This is where memslots come in. Think of
The QMP code was never called by *-user, and we will add
machine-type-specific code there, so add #ifdefs to make it safe.
Signed-off-by: Eduardo Habkost
---
target/i386/cpu.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index c78b2abfb8..bf4b4a
Move find_machine() from vl.c to core/machine.c and rename it to
machine_find_class(), so it can be reused by other code.
The function won't reuse the results of the previous
object_class_get_list() call like it did in vl.c, but this
shouldn't be a problem because the function is expected to be
ca
Changes v1 -> v2:
* Rewrite documentation, with suggestions from Markus
* Try to reduce churn and keep the existing default_cpu_version
static variable
* Replace x86_cpu_class_get_alias_of() with x86_cpu_model_resolve_alias()
Link to v1:
https://lore.kernel.org/qemu-devel/20191025022553.25298-1-
Instead of calling x86_cpu_class_get_alias_of(), just save the
actual CPU model name in X86CPUModel and use it in `-cpu help`.
Signed-off-by: Eduardo Habkost
---
target/i386/cpu.c | 15 +++
1 file changed, 11 insertions(+), 4 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386
We will change query-cpu-definitions to have a new `machine`
parameter. Move the code that reads default_cpu_version to
qmp_query_cpu_definitions() to make that easier to implement.
This patch shouldn't introduce any behavior change. Results of
query-cpu-definition will be exactly the same.
Sig
New function is very similar to the old function, but it just
takes a X86CPUModel as argument, and its name makes its purpose
clearer.
Signed-off-by: Eduardo Habkost
---
target/i386/cpu.c | 33 +
1 file changed, 17 insertions(+), 16 deletions(-)
diff --git a/targ
The new parameter can be used by management software to query for
CPU model alias information for multiple machines without
restarting QEMU.
Signed-off-by: Eduardo Habkost
---
Changes v1 -> v2:
* Rewrite documentation, with suggestions from Markus
---
qapi/machine-target.json |
Currently, the functions that resolve CPU model versions
(x86_cpu_model_resolve_version(), x86_cpu_model_resolve_alias())
need a machine to be initialized first. Get rid of this
requirement by making those functions get an explicit
default_version argument.
No behavior changes are introduced by t
On 10/13/20 6:25 AM, Philippe Mathieu-Daudé wrote:
> Yocto developers have expressed interest in running MIPS32
> CPU with custom number of TLB:
> https://lists.gnu.org/archive/html/qemu-devel/2020-10/msg03428.html
>
> Help them by making the number of TLB entries a CPU property,
> keeping our set
On 10/13/20 5:26 AM, Peter Maydell wrote:
> When using -icount, it's useful for the CPU_LOG_EXEC logging
> to include information about when cpu_io_recompile() was
> called, because it alerts the reader of the log that the
> tracing of a previous TB execution may not actually
> correspond to an act
On 10/12/20 6:20 AM, Philippe Mathieu-Daudé wrote:
> Philippe Mathieu-Daudé (5):
> hw: Replace magic value by PCI_NUM_PINS definition
> hw/pci-host/pam: Use ARRAY_SIZE() instead of magic value
> hw/pci-host/versatile: Add the MEMORY_WINDOW_COUNT definition
> hw/pci-host/versatile: Add the P
On 10/12/20 9:05 AM, Philippe Mathieu-Daudé wrote:
> Philippe Mathieu-Daudé (2):
> hw/mips/malta: Move gt64120 related code together
> hw/mips/malta: Use clearer qdev style
Reviewed-by: Richard Henderson
r~
On Tue, Oct 13, 2020 at 01:19:30PM +0800, Yang Weijiang wrote:
> With more components in XSS being developed on Intel platform,
> it's necessary to clean up existing XSAVE related feature words to
> make the name clearer. It's to prepare for adding CET related support
> in following patches.
>
> S
On 10/3/20 10:49 AM, Philippe Mathieu-Daudé wrote:
> Fix an unlikely memory leak in load_elf_image().
>
> Fixes: bf858897b7 ("linux-user: Re-use load_elf_image for the main binary.")
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> linux-user/elfload.c | 8
> 1 file changed, 4 insertions
Instead of returning the unused entry address from riscv_load_firmware()
instead return the end address. Also return the end address from
riscv_find_and_load_firmware().
This tells the caller if a firmware was loaded and how big it is. This
can be used to determine the load address of the next ima
Allow the user to specify the main application CPU for the sifive_u
machine.
Signed-off-by: Alistair Francis
Reviewed-by: Bin Meng
---
include/hw/riscv/sifive_u.h | 1 +
hw/riscv/sifive_u.c | 18 +-
2 files changed, 14 insertions(+), 5 deletions(-)
diff --git a/include
This series allows loading a noMMU kernel using the -kernel option.
Currently if using -kernel QEMU assumes you also have firmware and loads
the kernel at a hardcoded offset. This series changes that so we only
load the kernel at an offset if a firmware (-bios) was loaded.
This series also adds a
Instead of loading the kernel at a hardcoded start address, let's load
the kernel at the next alligned address after the end of the firmware.
This should have no impact for current users of OpenSBI, but will
allow loading a noMMU kernel at the start of memory.
Signed-off-by: Alistair Francis
---
Signed-off-by: Alistair Francis
---
include/hw/riscv/boot.h | 2 ++
hw/riscv/boot.c | 9 +
2 files changed, 11 insertions(+)
diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h
index 0acbd8aa6e..2975ed1a31 100644
--- a/include/hw/riscv/boot.h
+++ b/include/hw/riscv/boo
On Mon, Oct 12, 2020 at 8:45 AM Peter Maydell wrote:
>
> The netduino2 and netduinoplus2 boards forgot to set the system_clock_scale
> global, which meant that if guest code used the systick timer in "use
> the processor clock" mode it would hang because time never advances.
>
> Set the global to
On Tue, Oct 13, 2020 at 5:29 PM Alistair Francis wrote:
>
> On Mon, Oct 12, 2020 at 8:45 AM Peter Maydell
> wrote:
> >
> > The netduino2 and netduinoplus2 boards forgot to set the system_clock_scale
> > global, which meant that if guest code used the systick timer in "use
> > the processor clock
On Wed, Oct 14, 2020 at 06:42:02AM +0900, Dmitry Fomichev wrote:
> +{
> +NvmeEffectsLog log = {};
> +uint32_t *dst_acs = log.acs, *dst_iocs = log.iocs;
> +uint32_t trans_len;
> +int i;
> +
> +trace_pci_nvme_cmd_supp_and_effects_log_read();
> +
> +if (off >= sizeof(log)) {
>
On Tue, Oct 6, 2020 at 5:48 AM Igor Mammedov wrote:
>
> On Mon, 28 Sep 2020 21:17:31 +0800
> Jiajun Chen wrote:
>
> > Used_memslots is equal to dev->mem->nregions now, it is true for
> > vhost kernel, but not for vhost user, which uses the memory regions
> > that have file descriptor. In fact, no
Hi all -
I've been playing around with qemu-system-arm on a MacOS 10.15 box. I'm trying
to bridge the guest but I haven't had any luck. It looks like the proper way
to do this is with a TAP device. AFAIK, this was done in the past by
installing a TUN/TAP kernel extension (kext), which Apple
> -Original Message-
> From: Max Reitz [mailto:mre...@redhat.com]
> Sent: Tuesday, October 13, 2020 10:47 PM
> To: Chenqun (kuhn) ; qemu-devel@nongnu.org;
> qemu-triv...@nongnu.org
> Cc: vsement...@virtuozzo.com; stefa...@redhat.com; f...@euphon.net;
> ebl...@redhat.com; js...@redhat.com;
On Mon, Oct 12, 2020 at 7:12 AM chenjiajun wrote:
>
>
>
> On 2020/10/2 10:05, Raphael Norwitz wrote:
> > On Mon, Sep 28, 2020 at 9:17 AM Jiajun Chen wrote:
> >>
> >> Used_memslots is equal to dev->mem->nregions now, it is true for
> >> vhost kernel, but not for vhost user, which uses the memory r
Hi, Philippe,
On Tue, Oct 13, 2020 at 9:45 PM Philippe Mathieu-Daudé wrote:
>
> On 10/13/20 1:12 PM, Huacai Chen wrote:
> > Hi, Philippe,
> >
> > On Mon, Oct 12, 2020 at 4:12 PM Philippe Mathieu-Daudé
> > wrote:
> >>
> >> On 10/11/20 4:53 AM, Huacai Chen wrote:
> >>> Hi, Philippe,
> >>>
> >>> O
Also DEBUG_CACHE in migration/page_cache.c is need to rebase on trace_calls.
On 2020/10/13 21:20, Bihong Yu wrote:
> Thank you for your review. OK, I will try to rewrite the DPRINTF to use
> trace_ instead.
>
> On 2020/10/13 17:39, Dr. David Alan Gilbert wrote:
>> * Bihong Yu (yubih...@huawei.co
OK, I will modify it later.
On 2020/10/14 9:29, Zheng Chuan wrote:
> Also DEBUG_CACHE in migration/page_cache.c is need to rebase on trace_calls.
>
> On 2020/10/13 21:20, Bihong Yu wrote:
>> Thank you for your review. OK, I will try to rewrite the DPRINTF to use
>> trace_ instead.
>>
>> On 2020/
Hi Philippe,
Thank you very much for looking at this. I gave a spin to
your 3 patch series in original setup, and as expected with
'-cpu 34Kf,tlb-entries=64' option it works great.
If nobody objects, and your patches could be merged, we
would greatly appreciate it.
Thanks,
Victor
__
On 10/13/20 4:11 PM, Richard Henderson wrote:
> On 10/13/20 6:25 AM, Philippe Mathieu-Daudé wrote:
>> Yocto developers have expressed interest in running MIPS32
>> CPU with custom number of TLB:
>> https://lists.gnu.org/archive/html/qemu-devel/2020-10/msg03428.html
>>
>> Help them by making the num
Hi Richard,
Please forgive my cumbersome mailing agent at work.
Please look inline for 'victor>'
From: Richard Henderson
Sent: Tuesday, October 13, 2020 7:22 PM
To: Philippe Mathieu-Daudé; qemu-devel@nongnu.org; Victor Kamensky (kamensky)
Cc: Aleksandar
Public bug reported:
Hello together,
i build qemu-5.1.0 from source on centos 8 withe the following command:
../configure --prefix=/usr --target-list=x86_64-softmmu,x86_64-linux-
user
make -j4
make install
The build and the installation finished successfully. But when i try the
command
man q
As described in the included documentation, the "custom runner" jobs
extend the GitLab CI jobs already in place.
Those jobs are intended to run on hardware and/or Operating Systems
not provided by GitLab's shared runners.
Signed-off-by: Cleber Rosa
---
.gitlab-ci.d/custom-runners.yml | 14 +
The QEMU project has two machines (aarch64 and s390) that can be used
for jobs that do build and run tests. This introduces those jobs,
which are a mapping of custom scripts used for the same purpose.
Signed-off-by: Cleber Rosa
---
.gitlab-ci.d/custom-runners.yml | 192 +
To run basic jobs on custom runners, the environment needs to be
properly set up. The most common requirement is having the right
packages installed.
The playbook introduced here covers a number of different Linux
distributions and FreeBSD, and are intended to provide a reproducible
environment.
To have the jobs dispatched to custom runners, gitlab-runner must
be installed, active as a service and properly configured. The
variables file and playbook introduced here should help with those
steps.
The playbook introduced here covers a number of different Linux
distributions and FreeBSD, and
TL;DR: this should allow the QEMU maintainer to push to the staging
branch, and have custom jobs running on the project's aarch64 and
s390x machines. Simple usage looks like:
git push remote staging
./scripts/ci/gitlab-pipeline-status --verbose --wait
Long version:
The idea about a public
Hi Green,
On Mon, Sep 28, 2020 at 6:12 PM Green Wan wrote:
>
> - Add write operation to update fuse data bit when PWE bit is on.
> - Add array, fuse_wo, to store the 'written' status for all bits
>of OTP to block the write operation.
>
> Signed-off-by: Green Wan
> Reviewed-by: Alistair Fra
On Mon, Sep 28, 2020 at 6:12 PM Green Wan wrote:
>
> Add '-drive' support to OTP device. Allow users to assign a raw file
> as OTP image.
>
> test commands for 16k otp.img filled with zero:
>
> dd if=/dev/zero of=./otp.img bs=1k count=16
nits: please prefix the command with a leading "$ ", like
On 13.10.2020 22:21, Claudio Fontana wrote:
this fixes non-TCG builds broken recently by replay reverse debugging.
stub the needed functions in stub/, including errors for hmp and qmp.
This includes duplicating some code in replay/, and puts the logic
for non-replay related events in the replay/
Connect CAN0 and CAN1 on the ZynqMP.
Reviewed-by: Francisco Iglesias
Reviewed-by: Edgar E. Iglesias
Signed-off-by: Vikram Garhwal
---
include/hw/arm/xlnx-zynqmp.h | 8
hw/arm/xlnx-zcu102.c | 20
hw/arm/xlnx-zynqmp.c | 34 ++
Changelog:
v10 -> v11:
Resending the series with correct cc.
Replace DB_PRINTS with trace-events.
Removed unnecessary local variables.
Added const with tx/rx buffers in qtest.
Added reviewed-by tags for qtest.
v9 -> v10:
Rebase the series with the new meson build system.
Connect CAN0 and CAN1 on the ZynqMP.
Reviewed-by: Francisco Iglesias
Reviewed-by: Edgar E. Iglesias
Signed-off-by: Vikram Garhwal
---
include/hw/arm/xlnx-zynqmp.h | 8
hw/arm/xlnx-zcu102.c | 20
hw/arm/xlnx-zynqmp.c | 34 ++
The QTests perform five tests on the Xilinx ZynqMP CAN controller:
Tests the CAN controller in loopback, sleep and snoop mode.
Tests filtering of incoming CAN messages.
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Francisco Iglesias
Signed-off-by: Vikram Garhwal
---
tests/qtest/xln
Reviewed-by: Francisco Iglesias
Reviewed-by: Edgar E. Iglesias
Signed-off-by: Vikram Garhwal
---
MAINTAINERS | 8
1 file changed, 8 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 47dd38a..a8c672c 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1559,6 +1559,14 @@ F: hw/net/o
Reviewed-by: Francisco Iglesias
Reviewed-by: Edgar E. Iglesias
Signed-off-by: Vikram Garhwal
---
MAINTAINERS | 8
1 file changed, 8 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 47dd38a..a8c672c 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1559,6 +1559,14 @@ F: hw/net/o
The Xilinx ZynqMP CAN controller is developed based on SocketCAN, QEMU CAN bus
implementation. Bus connection and socketCAN connection for each CAN module
can be set through command lines.
Example for using single CAN:
-object can-bus,id=canbus0 \
-machine xlnx-zcu102.canbus0=canbus0 \
Connect CAN0 and CAN1 on the ZynqMP.
Reviewed-by: Francisco Iglesias
Reviewed-by: Edgar E. Iglesias
Signed-off-by: Vikram Garhwal
---
include/hw/arm/xlnx-zynqmp.h | 8
hw/arm/xlnx-zcu102.c | 20
hw/arm/xlnx-zynqmp.c | 34 ++
Changelog:
v10 -> v11:
Resending the series with correct cc.
Replace DB_PRINTS with trace-events.
Removed unnecessary local variables.
Added const with tx/rx buffers in qtest.
Added reviewed-by tags for qtest.
v9 -> v10:
Rebase the series with the new meson build system.
The QTests perform five tests on the Xilinx ZynqMP CAN controller:
Tests the CAN controller in loopback, sleep and snoop mode.
Tests filtering of incoming CAN messages.
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Francisco Iglesias
Signed-off-by: Vikram Garhwal
---
tests/qtest/xln
The Xilinx ZynqMP CAN controller is developed based on SocketCAN, QEMU CAN bus
implementation. Bus connection and socketCAN connection for each CAN module
can be set through command lines.
Example for using single CAN:
-object can-bus,id=canbus0 \
-machine xlnx-zcu102.canbus0=canbus0 \
Reviewed-by: Francisco Iglesias
Reviewed-by: Edgar E. Iglesias
Signed-off-by: Vikram Garhwal
---
MAINTAINERS | 8
1 file changed, 8 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 47dd38a..a8c672c 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1559,6 +1559,14 @@ F: hw/net/o
The Xilinx ZynqMP CAN controller is developed based on SocketCAN, QEMU CAN bus
implementation. Bus connection and socketCAN connection for each CAN module
can be set through command lines.
Example for using single CAN:
-object can-bus,id=canbus0 \
-machine xlnx-zcu102.canbus0=canbus0 \
Changelog:
v10 -> v11:
Replace DB_PRINTS with trace-events.
Removed unnecessary local variables.
Added const with tx/rx buffers in qtest.
Added reviewed-by tags for qtest.
v9 -> v10:
Rebase the series with the new meson build system.
v8 -> v9:
Use g_autofree to do automat
The QTests perform five tests on the Xilinx ZynqMP CAN controller:
Tests the CAN controller in loopback, sleep and snoop mode.
Tests filtering of incoming CAN messages.
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Francisco Iglesias
Signed-off-by: Vikram Garhwal
---
tests/qtest/xln
Public bug reported:
Hi,
I have a macOS 10.15.7 vm with GPU passthrough (NVIDIA GTX Titan Black),
libvirt xml has path to vbios too.
Qemu 5.1.0-1 with libvirt 6.5.0-2 are installed in manjaro architect 20.1.1
(two kernels tried: 5.4.67 LTS and 5.8.11 stable, no difference).
I have two monitors,
привет Pavel!
On 10/14/20 7:42 AM, Pavel Dovgalyuk wrote:
> On 13.10.2020 22:21, Claudio Fontana wrote:
>> this fixes non-TCG builds broken recently by replay reverse debugging.
>>
>> stub the needed functions in stub/, including errors for hmp and qmp.
>> This includes duplicating some code in re
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