Thomas reminded me on IRC that I hadn't got round to drafting
the release schedule for 5.2 yet. Here's some proposed dates:
https://wiki.qemu.org/Planning/5.2#Release_Schedule
which would put softfreeze on the 27th Oct, Hardfreeze/rc0 on the
3rd Nov, and aiming for final release on the 1st Decembe
Le 10/10/2020 à 13:07, Chen Qun a écrit :
> This if statement judgment is redundant and it will cause a warning:
>
> migration/block-dirty-bitmap.c:1090:13: warning: ‘bitmap_name’ may be used
> uninitialized in this function [-Wmaybe-uninitialized]
> g_strlcpy(s->bitmap_name, bitmap_
Deprecate our Unicore32 target support:
* the Linux kernel dropped support for unicore32 in commit
05119217a9bd199c for its 5.9 release (with rationale in the
cover letter: https://lkml.org/lkml/2020/8/3/232 )
* there is apparently no upstream toolchain that can create unicore32
binaries
Add coverage for the v8.2 DP and v8.2 FHM insns in the Neon extension
space. (We already had the v8.1 VQRDMLAH/VQRDLSH and the v8.3
VCADD/VCMLA, so this brings the risu coverage into line with what
QEMU has implemented so far.)
Signed-off-by: Peter Maydell
---
I added these patterns as part of t
This patchseries implements various minor v8.1M new features,
notably the branch-future and low-overhead-loop extensions.
(None of this will get enabled until we have enough to implement
a CPU model which has v8.1M, which will be the Cortex-M55, but
as usual we can get stuff into the tree graduall
Deprecate our TileGX target support:
* we have no active maintainer for it
* it has had essentially no contributions (other than tree-wide cleanups
and similar) since it was first added
* the Linux kernel dropped support in 2018, as has glibc
Note the deprecation in the manual, but don't try
The config-devices.mak files are generated by "make", and so they
should be deleted by "make clean".
(This is different from config-host.mak and config-all-disas.mak,
which are created by "configure" and so only deleted by
"make distclen".)
If we don't delete these files on "make clean", then the
Deprecate our lm32 target support. Michael Walle (former lm32 maintainer)
suggested that we do this in 2019:
https://www.mail-archive.com/qemu-devel@nongnu.org/msg605024.html
because the only public user of the architecture is the many-years-dead
milkymist project. (The Linux port to lm32 was neve
Add patterns for the fp16 half-precision floating point extension.
Where older pre-fp16 patterns used to include UNDEF encodings
that now mean fp16, constrain them so that tests generated
from those patterns will give the same results on CPUs both
with and without fp16.
Signed-off-by: Peter Maydel
On some hosts (eg Ubuntu Bionic) pkg-config returns a set of
libraries for gio-2.0 which don't actually work when compiling
statically. (Specifically, the returned library string includes
-lmount, but not -lblkid which -lmount depends upon, so linking
fails due to missing symbols.)
Check that the
If the guest is 32 bit then there is a potential problem if the
host gives us back a 64-bit sized value that we can't fit into
the ABI the guest requires. This is a theoretical issue for many
syscalls, but a real issue for directory reads where the host
is using ext3 or ext4. There the 'offset' val
Commit 6a0b7505f1fd6769c which added documentation of the virt board
crossed in the post with commit 6f4e1405b91da0d0 which added a new
'mte' machine option. Update the docs to include the new option.
Signed-off-by: Peter Maydell
---
docs/system/arm/virt.rst | 4
1 file changed, 4 insertion
virtio-input-hid.c undefines CONFIG_CURSES before including
ui/console.h. However since commits e2f82e924d057935 and b0766612d16da18
that header does not have behaviour dependent on CONFIG_CURSES.
Remove the now-unneeded undef.
Signed-off-by: Peter Maydell
---
NB: tested with 'make check' only.
In armsse_realize() we have a loop over [0, info->num_cpus), which
indexes into various fixed-size arrays in the ARMSSE struct. This
confuses Coverity, which warns that we might overrun those arrays
(CID 1430326, 1430337, 1430371, 1430414, 1430430). This can't
actually happen, because the info st
For nested groups like:
{
[
pattern 1
pattern 2
]
pattern 3
}
the intended behaviour is that patterns 1 and 2 must not
overlap with each other; if the insn matches neither then
we fall through to pattern 3 as the next thing in the
outer overlapping group.
Currently we
In commit 176d2cda0dee9f4 we added the @die-id field
to the CpuInstanceProperties struct, but in the process
accidentally removed the newline between the doc-comment
lines for @core-id and @thread-id.
Put the newline back in; this fixes a misformatting in the
generated HTML QMP reference manual.
In gicv3_init_cpuif() we copy the ARMCPU gicv3_maintenance_interrupt
into the GICv3CPUState struct's maintenance_irq field. This will
only work if the board happens to have already wired up the CPU
maintenance IRQ before the GIC was realized. Unfortunately this is
not the case for the 'virt' boar
The netduino2 and netduinoplus2 boards forgot to set the system_clock_scale
global, which meant that if guest code used the systick timer in "use
the processor clock" mode it would hang because time never advances.
Set the global to match the documented CPU clock speed of these boards.
Judging by
Implement a model of the MPS2 with the AN386 firmware. This is
essentially identical to the AN385 firmware, but it has a
Cortex-M4 rather than a Cortex-M3.
Signed-off-by: Peter Maydell
---
hw/arm/mps2.c | 30 +++---
1 file changed, 27 insertions(+), 3 deletions(-)
diff -
The MSF2 SoC model and the Stellaris board code both wire
SYSRESETREQ up to a function that just invokes
qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
This is now the default action that the NVIC does if the line is
not connected, so we can delete the handling code.
Signed-off-by: Pet
In gicv3_init_cpuif() we copy the ARMCPU gicv3_maintenance_interrupt
into the GICv3CPUState struct's maintenance_irq field. This will
only work if the board happens to have already wired up the CPU
maintenance IRQ before the GIC was realized. Unfortunately this is
not the case for the 'virt' boar
The nrf51 SoC model wasn't setting the system_clock_scale
global.which meant that if guest code used the systick timer in "use
the processor clock" mode it would hang because time never advances.
Set the global to match the documented CPU clock speed for this SoC.
This SoC in fact doesn't have a
commit f01496a314d916 moved the logic for detecting libudev from
configure to meson.build, but in the process it dropped the condition
that meant we only ask pkg-config about libudev for a non-static
build.
This breaks static builds of the system emulators on at least Ubuntu
18.04.4, because on th
Fix a typo in an error message in virtio_iommu_pci_realize():
"Check you machine" should be "Check your machine".
Reported-by: Markus Armbruster
Signed-off-by: Peter Maydell
---
hw/virtio/virtio-iommu-pci.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/virtio/virtio-iom
In bcm2835_fb_mbox_push(), Coverity complains (CID 1429989) that we
pass a pointer to a local struct to another function without
initializing all its fields. This is a real bug:
bcm2835_fb_reconfigure() copies the whole of our new BCM2385FBConfig
struct into s->config, so any fields we don't initi
In commit 962fcbf2efe57231a9f5df we converted the uses of the
ARM_FEATURE_CRC bit to use the aa32_crc32 isar_feature test
instead. However we forgot to remove the now-unused definition
of the feature name in the enum. Delete it now.
Signed-off-by: Peter Maydell
---
target/arm/cpu.h | 1 -
1 file
It is the responsibility of board code for an armv7m system to set
system_clock_scale appropriately for the CPU speed of the core.
If it forgets to do this, then QEMU will hang if the guest tries
to use the systick timer in the "tick at the CPU clock frequency" mode.
We forgot that in a couple of
The Arm signal-handling code has some parts ifdeffed with a
TARGET_CONFIG_CPU_32, which is always defined. This is a leftover
from when this code's structure was based on the Linux kernel
signal handling code, where it was intended to support 26-bit
Arm CPUs. The kernel dropped its CONFIG_CPU_32 in
On 12/10/20 17:09, Daniel P. Berrangé wrote:
> On Mon, Oct 12, 2020 at 05:07:18PM +0200, Thomas Huth wrote:
>> On 14/09/2020 13.09, Daniel P. Berrangé wrote:
>>> Sometimes under CI tests non-deterministically take longer to execute
>>> than expected which can trigger timeouts. It is almost impossib
As part of the Neon decodetree conversion we removed all
the uses of the VFP_DREG macros, but forgot to remove the
macro definitions. Do so now.
Signed-off-by: Peter Maydell
---
target/arm/translate.c | 15 ---
1 file changed, 15 deletions(-)
diff --git a/target/arm/translate.c b/ta
The imx_epit device has a software-controllable reset triggered by
setting the SWR bit in the CR register. An error in commit cc2722ec83ad9
means that we will end up assert()ing if the guest does this, because
the code in imx_epit_write() starts ptimer transactions, and then
imx_epit_reset() also s
Using the MSR instruction to write to CPSR.E is deprecated, but it is
required to work from any mode including unprivileged code. We were
incorrectly forbidding usermode code from writing it because
CPSR_USER did not include the CPSR_E bit.
We use CPSR_USER in only three places:
* as the mask of
Add a documentation comment for qemu_get_thread_id(): since this
is rather host-OS-specific it's useful if people writing the
implementation and people thinking of using the function know
what the purpose and limitations are.
Signed-off-by: Peter Maydell
---
Based on conversation with Dan on IRC,
For nested groups like:
{
[
pattern 1
pattern 2
]
pattern 3
}
the intended behaviour is that patterns 1 and 2 must not
overlap with each other; if the insn matches neither then
we fall through to pattern 3 as the next thing in the
outer overlapping group.
Currently we
In commit a8d2532645cf5ce4 we cleaned up usage of the qemu-common.h header
so that it was always included from .c files and never from other .h files.
We missed adding it to net/tap-solaris.c (which previously was pulling it
in via tap-int.h), which broke building on Solaris hosts.
Fixes: a8d25326
v8.1M brings four new insns to M-profile:
* CSEL : Rd = cond ? Rn : Rm
* CSINC : Rd = cond ? Rn : Rm+1
* CSINV : Rd = cond ? Rn : ~Rm
* CSNEG : Rd = cond ? Rn : -Rm
Implement these.
Signed-off-by: Peter Maydell
---
target/arm/t32.decode | 3 +++
target/arm/translate.c | 55 ++
>From v8.1M, disabled-coprocessor handling changes slightly:
* coprocessors 8, 9, 14 and 15 are also governed by the
cp10 enable bit, like cp11
* an extra range of instruction patterns is considered
to be inside the coprocessor space
We previously marked these up with TODO comments; implem
This patchseries implements various minor v8.1M new features,
notably the branch-future and low-overhead-loop extensions.
(None of this will get enabled until we have enough to implement
a CPU model which has v8.1M, which will be the Cortex-M55, but
as usual we can get stuff into the tree graduall
The t32 decode has a group which represents a set of insns
which overlap with B_cond_thumb because they have [25:23]=111
(which is an invalid condition code field for the branch insn).
This group is currently defined using the {} overlap-OK syntax,
but it is almost entirely non-overlapping patterns
In arm_cpu_realizefn(), if the CPU has VFP or Neon disabled then we
squash the ID register fields so that we don't advertise it to the
guest. This code was written for A-profile and needs some tweaks to
work correctly on M-profile:
* A-profile only fields should not be zeroed on M-profile:
-
On Mon, 2020-10-12 at 16:57 +0100, Dr. David Alan Gilbert wrote:
> * Tobin Feldman-Fitzthum (to...@linux.ibm.com) wrote:
> > On 2020-09-21 15:16, Dr. David Alan Gilbert wrote:
> > > * Tobin Feldman-Fitzthum (to...@linux.vnet.ibm.com) wrote:
> > > > AMD SEV allows a guest owner to inject a secret bl
The BLX immediate insn in the Thumb encoding always performs
a switch from Thumb to Arm state. This would be totally useless
in M-profile which has no Arm decoder, and so the instruction
does not exist at all there. Make the encoding UNDEF for M-profile.
(This part of the encoding space is used fo
On Fri, Oct 09, 2020 at 01:44:49PM -0600, Alex Williamson wrote:
> On Fri, 9 Oct 2020 17:18:15 +0100
> Stefan Hajnoczi wrote:
> > Extensibility for new bus types
> > ```
> > It should be possible to support multiple bus types. vhost-user only
> > supports vhost devices.
The 'empty_slot' region created is related to the gt64120.
Move its creation close to the gt64120 instance creation.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/mips/malta.c | 13 ++---
1 file changed, 6 insertions(+), 7 deletions(-)
diff --git a/hw/mips/malta.c b/hw/mips/malta.c
index
v8.1M's "low-overhead-loop" extension has three instructions
for looping:
* DLS (start of a do-loop)
* WLS (start of a while-loop)
* LE (end of a loop)
The loop-start instructions are both simple operations to start a
loop whose iteration count (if any) is in LR. The loop-end
instruction handl
v8.1M implements a new 'branch future' feature, which is a
set of instructions that request the CPU to perform a branch
"in the future", when it reaches a particular execution address.
In hardware, the expected implementation is that the information
about the branch location and destination is cach
Patchew URL:
https://patchew.org/QEMU/20201012153408.9747-10-peter.mayd...@linaro.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20201012153408.9747-10-peter.mayd...@linaro.org
Subject: [PATCH for-5.1] docs/system
If the M-profile low-overhead-branch extension is implemented, FPSCR
bits [18:16] are a new field LTPSIZE. If MVE is not implemented
(currently always true for us) then this field always reads as 4 and
ignores writes.
These bits used to be the vector-length field for the old
short-vector extensio
On Mon, 12 Oct 2020, Peter Maydell wrote:
Deprecate our TileGX target support:
* we have no active maintainer for it
* it has had essentially no contributions (other than tree-wide cleanups
and similar) since it was first added
* the Linux kernel dropped support in 2018, as has glibc
Note the
The M-profile specific part of the sanitizing of the value to
be written to the FPSCR used a mask which always zeroed bit 19,
which is FZ16. This is incorrect when the CPU supports 16-bit
floating point arithmetic, because the bit should be writeable.
Code earlier in the function already handles m
On Mon, 12 Oct 2020 at 16:42, BALATON Zoltan wrote:
>
> On Mon, 12 Oct 2020, Peter Maydell wrote:
> > Deprecate our TileGX target support:
> Is that 5.2?
This mail was patch of an accidental mailbomb of the list
with a couple of dozen stale (already sent weeks/months back)
patches that were hangi
On Sun, Oct 11, 2020 at 07:32:58PM +0100, Peter Maydell wrote:
> On Fri, 9 Oct 2020 at 20:35, Stefan Hajnoczi wrote:
> >
> > The following changes since commit 497d415d76b9f59fcae27f22df1ca2c3fa4df64e:
> >
> > Merge remote-tracking branch
> > 'remotes/pmaydell/tags/pull-target-arm-20201008-1' i
* Tobin Feldman-Fitzthum (to...@linux.ibm.com) wrote:
> On 2020-09-21 15:16, Dr. David Alan Gilbert wrote:
> > * Tobin Feldman-Fitzthum (to...@linux.vnet.ibm.com) wrote:
> > > AMD SEV allows a guest owner to inject a secret blob
> > > into the memory of a virtual machine. The secret is
> > > encryp
Alistair Francis writes:
> On Fri, Oct 9, 2020 at 10:07 AM Alex Bennée wrote:
>>
>> Hi,
>>
>> This series adds the ability to append FDT data for blobs loaded by
>> the generic loader. My principle use-case was to be able to directly
>> boot Xen with a kernel image which avoided having to:
>>
Move some code around to make this big function
easier to review.
Philippe Mathieu-Daudé (2):
hw/mips/malta: Move gt64120 related code together
hw/mips/malta: Use clearer qdev style
hw/mips/malta.c | 21 ++---
1 file changed, 10 insertions(+), 11 deletions(-)
--
2.26.2
Hi Eduardo,
Sorry for the late reply, in general there are also hv-net and hv-scsi
implementations from Roman Kagan, which have not been merged in...
I have a WIP component which does not use vmbus but Windows needs it
to exist and function in order for it to work (it's the synthetic
debugger int
In order to be consistent with the other code base uses,
rewrite slightly how the MIPS_MALTA object is created.
No logical change.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/mips/malta.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/mips/malta.c b/hw/mips/malta
* Tobin Feldman-Fitzthum (to...@linux.vnet.ibm.com) wrote:
> AMD SEV allows a guest owner to inject a secret blob
> into the memory of a virtual machine. The secret is
> encrypted with the SEV Transport Encryption Key and
> integrity is guaranteed with the Transport Integrity
> Key. Although QEMU f
On Thu, Oct 08, 2020 at 04:27:12PM -0400, Eduardo Habkost wrote:
> Fix the following crash:
>
> $ qemu-system-x86_64 -object can-host-socketcan,id=obj0
> Segmentation fault (core dumped)
>
> Signed-off-by: Eduardo Habkost
Reviewed-by: Vikram Garhwal
> ---
> Cc: Pavel Pisa
> Cc: Vikram Garhwa
On Mon, 12 Oct 2020 at 17:19, Alex Bennée wrote:
> So the real question is are there any other -devices that we want to be
> able to graft FDT entries on or is the generic loader enough of a
> special case that we keep all the logic in there?
To my mind the point of the generic loader is exactly
* James Bottomley (j...@linux.ibm.com) wrote:
> On Mon, 2020-10-12 at 16:57 +0100, Dr. David Alan Gilbert wrote:
> > * Tobin Feldman-Fitzthum (to...@linux.ibm.com) wrote:
> > > On 2020-09-21 15:16, Dr. David Alan Gilbert wrote:
> > > > * Tobin Feldman-Fitzthum (to...@linux.vnet.ibm.com) wrote:
> >
On Mon, Oct 12, 2020 at 05:21:15PM +0100, Dr. David Alan Gilbert wrote:
> * Tobin Feldman-Fitzthum (to...@linux.vnet.ibm.com) wrote:
> > AMD SEV allows a guest owner to inject a secret blob
> > into the memory of a virtual machine. The secret is
> > encrypted with the SEV Transport Encryption Key a
On Sun, Oct 11, 2020 at 10:11:39AM -0400, harry harry wrote:
> Hi Maxim,
>
> Thanks much for your reply.
>
> On Sun, Oct 11, 2020 at 3:29 AM Maxim Levitsky wrote:
> >
> > On Sun, 2020-10-11 at 01:26 -0400, harry harry wrote:
> > > Hi QEMU/KVM developers,
> > >
> > > I am sorry if my email distur
On 12/10/20 15:49, Thomas Huth wrote:
>> We chose to use the same name because the new version generally is the
>> one you want and, except for the handling of events, is exactly the same
>> as before. In other words, I'm treating the new semantics more as a
>> bugfix than a feature.
>>
>> The onl
Signed-off-by: Philippe Mathieu-Daudé
---
hw/pci-host/sabre.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/pci-host/sabre.c b/hw/pci-host/sabre.c
index 4412e23131c..67699ac9058 100644
--- a/hw/pci-host/sabre.c
+++ b/hw/pci-host/sabre.c
@@ -122,6 +122,7 @@ static void sabre_config_writ
We only need to zero-initialize 'val' once.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/pci-host/sabre.c | 12 +---
1 file changed, 1 insertion(+), 11 deletions(-)
diff --git a/hw/pci-host/sabre.c b/hw/pci-host/sabre.c
index 0889c9369f6..3645bc962cb 100644
--- a/hw/pci-host/sabre.c
+++
Report unimplemented register accesses using qemu_log_mask(UNIMP).
Signed-off-by: Philippe Mathieu-Daudé
---
hw/pci-host/sabre.c | 12
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/hw/pci-host/sabre.c b/hw/pci-host/sabre.c
index 3645bc962cb..4412e23131c 100644
--- a/
Notes while trying to understand Mark's patch from yesterday:
"sabre: increase number of PCI bus IRQs from 32 to 64"
https://www.mail-archive.com/qemu-devel@nongnu.org/msg749458.html
Philippe Mathieu-Daudé (6):
hw/pci-host/sabre: Update documentation link
hw/pci-host/sabre: Remove superfluous
Peter Maydell writes:
> On Mon, 12 Oct 2020 at 17:19, Alex Bennée wrote:
>> So the real question is are there any other -devices that we want to be
>> able to graft FDT entries on or is the generic loader enough of a
>> special case that we keep all the logic in there?
>
> To my mind the point
The current link redirects to https://www.oracle.com/sun/
announcing "Oracle acquired Sun Microsystems in 2010, ..."
but does not give hint where to find the datasheet.
Use the archived PDF on the Wayback Machine, which works.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/pci-host/sabre.c | 2 +-
The region is registered as 64KiB in sabre_init():
memory_region_init_io(&s->sabre_config, OBJECT(s), &sabre_config_ops, s,
"sabre-config", 0x1);
Remove the superfluous check.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/pci-host/sabre.c | 4 ++--
1 file chang
Report accesses to reserved registers using qemu_log_mask(GUEST_ERROR).
Signed-off-by: Philippe Mathieu-Daudé
---
hw/pci-host/sabre.c | 8
1 file changed, 8 insertions(+)
diff --git a/hw/pci-host/sabre.c b/hw/pci-host/sabre.c
index 67699ac9058..cc97c266a57 100644
--- a/hw/pci-host/sabr
Stefan Hajnoczi writes:
> I just posted the following on my blog to outline the requirements that
> have been discussed over the past few months around out-of-process
> device emulation (vhost-user, vfio-user, etc). I hope it's helpful for
> covering various angles of out-of-process device emul
On Mon, Oct 12, 2020 at 05:02:57PM +0100, Alex Bennée wrote:
>
> Alistair Francis writes:
>
> > On Fri, Oct 9, 2020 at 10:07 AM Alex Bennée wrote:
> >>
> >> Hi,
> >>
> >> This series adds the ability to append FDT data for blobs loaded by
> >> the generic loader. My principle use-case was to be
On 10/7/20 7:28 PM, Daniel Henrique Barboza wrote:
A new function called spapr_numa_define_associativity_domains()
is created to calculate the associativity domains and change
the associativity arrays considering user input. This is how
the associativity domain between two NUMA nodes A and B is
c
The iotest case test_stream_parallel still does not pass after the
COR-filter is inserted into the backing chain. As the test case may not
be initialized, it does not make a sense and was removed again.
v11:
04: Base node overlay is used instead of base.
05: Base node overlay is used instead o
Add support for the recently introduced functions
bdrv_co_preadv_part()
and
bdrv_co_pwritev_part()
to the COR-filter driver.
Signed-off-by: Andrey Shinkevich
Reviewed-by: Vladimir Sementsov-Ogievskiy
---
block/copy-on-read.c | 28
1 file changed, 16 insertions(+), 1
Provide API for the COR-filter insertion/removal.
Also, drop the filter child permissions for an inactive state when the
filter node is being removed.
Signed-off-by: Andrey Shinkevich
Reviewed-by: Vladimir Sementsov-Ogievskiy
---
block/copy-on-read.c | 88 +++
We are going to use the COR-filter for a block-stream job.
To limit COR operations by the base node in the backing chain during
stream job, pass the name of overlay base node to the copy-on-read
driver as base node itself may change due to possible concurrent jobs.
The rest of the functionality wil
Provide the possibility to pass the 'filter-node-name' parameter to the
block-stream job as it is done for the commit block job.
Signed-off-by: Andrey Shinkevich
Reviewed-by: Vladimir Sementsov-Ogievskiy
---
block/monitor/block-hmp-cmds.c | 4 ++--
block/stream.c | 4 +++-
block
Limit COR operations by the base node in the backing chain when the
overlay base node name is given. It will be useful for a block stream
job when the COR-filter is applied. The overlay base node is passed as
the base itself may change due to concurrent commit jobs on the same
backing chain.
Signe
Modify the comment for the flag BDRV_REQ_PREFETCH as we are going to
use it alone and pass it to the COR-filter driver for further
processing.
Signed-off-by: Andrey Shinkevich
---
include/block/block.h | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/include/block/block
Add the new member supported_read_flags to BlockDriverState structure.
It will control the BDRV_REQ_PREFETCH flag set for copy-on-read
operations.
Signed-off-by: Andrey Shinkevich
---
include/block/block_int.h | 4
1 file changed, 4 insertions(+)
diff --git a/include/block/block_int.h b/in
Add support for the BDRV_REQ_PREFETCH flag to the supported_write_flags
of the COR-filter.
Signed-off-by: Andrey Shinkevich
---
block/copy-on-read.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/block/copy-on-read.c b/block/copy-on-read.c
index dfbd6ad..b136895 100644
--- a/block/copy-on-r
If the flag BDRV_REQ_PREFETCH was set, pass it further to the
COR-driver to skip unneeded reading. It can be taken into account for
the COR-algorithms optimization. That check is being made during the
block stream job by the moment.
Signed-off-by: Andrey Shinkevich
---
block/copy-on-read.c | 13
Avoid writing a filter JSON-name to QCOW2 image when the backing file
is changed after the block stream job.
Signed-off-by: Andrey Shinkevich
---
block/stream.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/block/stream.c b/block/stream.c
index e0540ee..51462bd 100
Whereas the block-stream job starts using a backing file name of the
base node overlay after the block-stream job completes, mark the QMP
'backing-file' argument as deprecated.
Signed-off-by: Andrey Shinkevich
---
docs/system/deprecated.rst | 6 ++
1 file changed, 6 insertions(+)
diff --git
This patch completes the series with the COR-filter insertion for
block-stream operations. Adding the filter makes it possible for copied
regions to be discarded in backing files during the block-stream job,
what will reduce the disk overuse.
The COR-filter insertion incurs changes in the iotests c
The 'backing-file' argument is not used by the block-stream job. It
designates a backing file name to set in QCOW2 image header after the
block-stream job finished. A backing file name of the node above base
is used instead.
Signed-off-by: Andrey Shinkevich
---
block/stream.c| 6 +--
CC: Laurent Vivier
CC: qemu-triv...@nongnu.org
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Sergei Trofimovich
---
meson.build | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/meson.build b/meson.build
index a02c743794..48e7c56cc1 100644
--- a/meson.build
+++ b/meson.bu
The following changes since commit 2387df497b4b4bcf754eb7398edca82889e2ef54:
Merge remote-tracking branch 'remotes/armbru/tags/pull-qapi-2020-10-10' into
staging (2020-10-12 11:29:42 +0100)
are available in the Git repository at:
https://gitlab.com/stefanha/qemu.git tags/block-pull-request
From: Philippe Mathieu-Daudé
Keep statistics of some hardware errors, and number of
aligned/unaligned I/O accesses.
QMP example booting a full RHEL 8.3 aarch64 guest:
{ "execute": "query-blockstats" }
{
"return": [
{
"device": "",
"node-name": "drive0",
From: Coiby Xu
When the client is running in gdb and quit command is run in gdb,
QEMU will still dispatch the event which will cause segment fault in
the callback function.
Signed-off-by: Coiby Xu
Reviewed-by: Stefan Hajnoczi
Reviewed-by: Marc-André Lureau
Message-id: 20200918080912.321299-3-
From: Coiby Xu
By making use of libvhost-user, block device drive can be shared to
the connected vhost-user client. Only one client can connect to the
server one time.
Since vhost-user-server needs a block drive to be created first, delay
the creation of this object.
Suggested-by: Kevin Wolf
S
From: Coiby Xu
Allow vu_message_read to be replaced by one which will make use of the
QIOChannel functions. Thus reading vhost-user message won't stall the
guest. For slave channel, we still use the default vu_message_read.
Reviewed-by: Marc-André Lureau
Signed-off-by: Coiby Xu
Reviewed-by: St
From: Coiby Xu
Move the constants from hw/core/qdev-properties.c to
util/block-helpers.h so that knowledge of the min/max values is
Signed-off-by: Stefan Hajnoczi
Signed-off-by: Coiby Xu
Reviewed-by: Stefan Hajnoczi
Reviewed-by: Marc-André Lureau
Acked-by: Eduardo Habkost
Message-id: 202009
From: Coiby Xu
Sharing QEMU devices via vhost-user protocol.
Only one vhost-user client can connect to the server one time.
Suggested-by: Kevin Wolf
Signed-off-by: Stefan Hajnoczi
Signed-off-by: Coiby Xu
Reviewed-by: Stefan Hajnoczi
Reviewed-by: Marc-André Lureau
Message-id: 20200918080912
We already have access to the value with the correct type (ioc and sioc
are the same QIOChannel).
Signed-off-by: Stefan Hajnoczi
Message-id: 20200924151549.913737-4-stefa...@redhat.com
Signed-off-by: Stefan Hajnoczi
---
util/vhost-user-server.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion
From: Coiby Xu
Suggested-by: Stefano Garzarella
Signed-off-by: Coiby Xu
Reviewed-by: Stefan Hajnoczi
Reviewed-by: Marc-André Lureau
Message-id: 20200918080912.321299-8-coiby...@gmail.com
Signed-off-by: Stefan Hajnoczi
---
MAINTAINERS | 8
1 file changed, 8 insertions(+)
diff --git
Signed-off-by: Stefan Hajnoczi
Message-id: 20200924151549.913737-3-stefa...@redhat.com
Signed-off-by: Stefan Hajnoczi
---
util/vhost-user-server.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/util/vhost-user-server.c b/util/vhost-user-server.c
index 7b50a2b1fd..2cd0cf8277
201 - 300 of 475 matches
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