Re: [Virtio-fs] [PATCH v2 3/6] tools/virtiofsd: xattr name mappings: Add option

* Vivek Goyal (vgo...@redhat.com) wrote: > On Thu, Aug 27, 2020 at 04:36:54PM +0100, Dr. David Alan Gilbert (git) wrote: > > From: "Dr. David Alan Gilbert" > > > > Add an option to define mappings of xattr names so that > > the client and server filesystems see different views. > > This can be us

[RFC PATCH 2/6] hw/sd/sdcard: Introduce the INVALID_ADDRESS definition

'0' is used as a value to indicate an invalid (or unset) address. Use a definition instead of a magic value. Signed-off-by: Philippe Mathieu-Daudé --- hw/sd/sd.c | 13 - 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/hw/sd/sd.c b/hw/sd/sd.c index 2606b969e34..30ae435d6

[RFC PATCH 0/6] hw/sd/sdcard: Do not attempt to erase out of range addresses

Yet another bug in the sdcard model found by libfuzzer: https://bugs.launchpad.net/bugs/1895310 The bug is fixed, but there is a migration issue to be resolved... so posting as RFC. Philippe Mathieu-Daudé (6): hw/sd/sdcard: Add trace event for ERASE command (CMD38) hw/sd/sdcard: Introduce the

[RFC PATCH 1/6] hw/sd/sdcard: Add trace event for ERASE command (CMD38)

Trace addresses provided to the ERASE command. Signed-off-by: Philippe Mathieu-Daudé --- hw/sd/sd.c | 2 +- hw/sd/trace-events | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/sd/sd.c b/hw/sd/sd.c index 0012884..2606b969e34 100644 --- a/hw/sd/sd.c +++ b/hw/sd

[RFC PATCH 5/6] hw/sd/sdcard: Do not attempt to erase out of range addresses

While the Spec v3 is not very clear, v6 states: If the host provides an out of range address as an argument to CMD32 or CMD33, the card shall indicate OUT_OF_RANGE error in R1 (ERX) for CMD38. If an address is out of range, do not attempt to erase it: return R1 with the error bit set. Bugl

[RFC PATCH 3/6] hw/sd/sdcard: Do not use legal address '0' for INVALID_ADDRESS

As it is legal to WRITE/ERASE the address/block 0, change the value of this definition to an illegal address: UINT32_MAX. Signed-off-by: Philippe Mathieu-Daudé --- Cc: Dr. David Alan Gilbert Cc: Markus Armbruster Same problem I had with the pflash device last year... This break migration :( Wh

Re: [PATCH v2] tests/acceptance: Skip slow quanta-gsj U-boot+Linux test

On 9/18/20 4:33 PM, Philippe Mathieu-Daudé wrote: > The 'arm_quanta_gsj_initrd' test is timeouting on GitLab CI: > https://gitlab.com/philmd/qemu/-/jobs/745483978#L846 > and also sometimes on my workstation, so proceed as with > the other slow tests: do not run it by default. > The test can still b

[RFC PATCH 6/6] hw/sd/sdcard: Assert if accessing an illegal group

We can not have more group than 'wpgrps_size'. Assert if we are accessing a group above this limit. Signed-off-by: Philippe Mathieu-Daudé --- hw/sd/sd.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/hw/sd/sd.c b/hw/sd/sd.c index 4454d168e2f..c3febed2434 100644 --- a/hw/sd/sd.c +++ b/hw/s

[RFC PATCH 4/6] hw/sd/sdcard: Reset both start/end addresses on error

>From the Spec "4.3.5 Erase": The host should adhere to the following command sequence: ERASE_WR_BLK_START, ERASE_WR_BLK_END and ERASE (CMD38). If an erase (CMD38) or address setting (CMD32, 33) command is received out of sequence, the card shall set the ERASE_SEQ_ERROR bit in the sta

Re: [PATCH] tests/acceptance: Disable tests dependent of unreliable apt.armbian.com

On 9/17/20 6:39 PM, Philippe Mathieu-Daudé wrote: > Armbian servers are not very reliable and confused the GitLab CI > users a few times this month (path updated, archives moved, and > now the SSL: CERTIFICATE_VERIFY_FAILED "certificate has expired" > error). Time to disable these tests. > Users ca

Re: [PATCH v2] docs: simplify and clarify the platform support rules

On Fri, Sep 18, 2020 at 10:06:03AM +0100, Daniel P. Berrangé wrote: > The distinction between short life and long life Linux distributions > turned out to be redundant. They can both be covered in a simple way > by noting support will target the current release, and the previous > release for a per

Re: [PATCH v10 4/7] block: move logical block size check function to a common utility function

On Fri, Sep 18, 2020 at 04:09:09PM +0800, Coiby Xu wrote: > Move the constants from hw/core/qdev-properties.c to > util/block-helpers.h so that knowledge of the min/max values is > > Signed-off-by: Stefan Hajnoczi > Signed-off-by: Coiby Xu Acked-by: Eduardo Habkost -- Eduardo

Re: [PATCH v2 0/6] qom: Allow object to be aligned

On Tue, Sep 15, 2020 at 05:46:32PM -0700, Richard Henderson wrote: > I've seen some failures on arm and s390x hosts after > enabling host vector support. It turns out that the > malloc for these hosts does not provide 16-byte alignment. > > We already have a function that can alloc with alignment

[PULL 0/2] Python queue, 2020-09-18

Leftovers from pre-5.1.0 days. The following changes since commit 053a4177817db307ec854356e95b5b350800a216: Merge remote-tracking branch 'remotes/philmd-gitlab/tags/fw_cfg-20200918' into staging (2020-09-18 16:34:26 +0100) are available in the Git repository at: git://github.co

[PULL 1/2] scripts/simplebench: compare write request performance

From: Andrey Shinkevich The script 'bench_write_req.py' allows comparing performances of write request for two qemu-img binary files. An example with (qemu-img binary 1) and without (qemu-img binary 2) the applied patch "qcow2: skip writing zero buffers to empty COW areas" (git commit ID: c8bb23c

[PULL 2/2] analyze-migration.py: fix read_migration_debug_json() return type

From: Alexey Kirillov Since we use result of read_migration_debug_json() as JSON formatted string, we must provide proper type. Before Python 3.6 json.loads() method support only str typed input. Signed-off-by: Alexey Kirillov Message-Id: <20200715152135.20287-1-lekir...@yandex-team.ru> [ehabko

[Bug 1895310] Re: Heap-overflow (read) in sd_erase

Tentative fix: https://lists.gnu.org/archive/html/qemu-devel/2020-09/msg06828.html -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1895310 Title: Heap-overflow (read) in sd_erase Status in QEMU: N

Re: [PATCH 06/37] qapi: delint using flake8

On 9/18/20 6:33 AM, Markus Armbruster wrote: John Snow writes: On 9/17/20 3:54 AM, Markus Armbruster wrote: John Snow writes: On 9/16/20 8:12 AM, Markus Armbruster wrote: John Snow writes: Petty style guide fixes and line length enforcement. Not a big win, not a big loss, but flake8 p

Re: [PATCH 0/5] qom: Convert more declarations to OBJECT_DECLARE*

On Wed, Sep 16, 2020 at 02:25:14PM -0400, Eduardo Habkost wrote: > This converts many QOM types to use OBJECT_DECLARE* instead of > manually using DECLARE*_CHECKER*. > > Before doing that, I'm simplifying the OBJECT_DECLARE* API to > make it easier to use and more difficult to misuse. The > modul

[PATCH v6 02/15] block/io.c: drop assertion on double waiting for request serialisation

The comments states, that on misaligned request we should have already been waiting. But for bdrv_padding_rmw_read, we called bdrv_mark_request_serialising with align = request_alignment, and now we serialise with align = cluster_size. So we may have to wait again with larger alignment. Note, that

[PATCH v6 05/15] block: bdrv_mark_request_serialising: split non-waiting function

We'll need a separate function, which will only "mark" request serialising with specified align but not wait for conflicting requests. So, it will be like old bdrv_mark_request_serialising(), before merging bdrv_wait_serialising_requests_locked() into it. To reduce the possible mess, let's do the

[PATCH v6 06/15] block: introduce BDRV_REQ_NO_WAIT flag

Add flag to make serialising request no wait: if there are conflicting requests, just return error immediately. It's will be used in upcoming preallocate filter. Signed-off-by: Vladimir Sementsov-Ogievskiy Reviewed-by: Max Reitz --- include/block/block.h | 9 - block/io.c|

[PATCH v6 00/15] preallocate filter

Hi all! Here is a filter, which does preallocation on write. In Virtuozzo we have to deal with some custom distributed storage solution, where allocation is very-very expensive operation. We have to workaround it in Qemu, so here is a new filter. Still, the filter shows good results for me even

[PATCH v6 03/15] block/io: split out bdrv_find_conflicting_request

To be reused in separate. Signed-off-by: Vladimir Sementsov-Ogievskiy Reviewed-by: Stefan Hajnoczi --- block/io.c | 71 +++--- 1 file changed, 41 insertions(+), 30 deletions(-) diff --git a/block/io.c b/block/io.c index 67617bb9b2..c58fd36091 100

[PATCH v6 10/15] iotests: qemu_io_silent: support --image-opts

Signed-off-by: Vladimir Sementsov-Ogievskiy --- tests/qemu-iotests/iotests.py | 7 ++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/tests/qemu-iotests/iotests.py b/tests/qemu-iotests/iotests.py index 91e4a57126..3d48108f3a 100644 --- a/tests/qemu-iotests/iotests.py +++ b/tests

[PATCH v6 09/15] qemu-io: add preallocate mode parameter for truncate command

This will be used in further test. Signed-off-by: Vladimir Sementsov-Ogievskiy --- qemu-io-cmds.c | 46 -- 1 file changed, 32 insertions(+), 14 deletions(-) diff --git a/qemu-io-cmds.c b/qemu-io-cmds.c index baeae86d8c..64f0246a71 100644 --- a/qemu-io

[PATCH v6 04/15] block/io: bdrv_wait_serialising_requests_locked: drop extra bs arg

bs is linked in req, so no needs to pass it separately. Most of tracked-requests API doesn't have bs argument. Actually, after this patch only tracked_request_begin has it, but it's for purpose. While being here, also add a comment about what "_locked" is. Signed-off-by: Vladimir Sementsov-Ogievs

[PATCH v6 01/15] block: simplify comment to BDRV_REQ_SERIALISING

1. BDRV_REQ_NO_SERIALISING doesn't exist already, don't mention it. 2. We are going to add one more user of BDRV_REQ_SERIALISING, so comment about backup becomes a bit confusing here. The use case in backup is documented in block/backup.c, so let's just drop duplication here. 3. The fact

[PATCH v6 11/15] iotests: add 298 to test new preallocate filter driver

Signed-off-by: Vladimir Sementsov-Ogievskiy --- tests/qemu-iotests/298 | 186 + tests/qemu-iotests/298.out | 5 + tests/qemu-iotests/group | 1 + 3 files changed, 192 insertions(+) create mode 100644 tests/qemu-iotests/298 create mode 100644 tests/q

[PATCH v6 07/15] block: bdrv_check_perm(): process children anyway

Do generic processing even for drivers which define .bdrv_check_perm handler. It's needed for further preallocate filter: it will need to do additional action on bdrv_check_perm, but don't want to reimplement generic logic. The patch doesn't change existing behaviour: the only driver that implemen

[PATCH v6 12/15] scripts/simplebench: support iops

Support benchmarks returning not seconds but iops. We'll use it for further new test. Signed-off-by: Vladimir Sementsov-Ogievskiy --- scripts/simplebench/simplebench.py | 35 +++--- 1 file changed, 27 insertions(+), 8 deletions(-) diff --git a/scripts/simplebench/simpleb

[PATCH v6 08/15] block: introduce preallocate filter

It's intended to be inserted between format and protocol nodes to preallocate additional space (expanding protocol file) on writes crossing EOF. It improves performance for file-systems with slow allocation. Signed-off-by: Vladimir Sementsov-Ogievskiy --- docs/system/qemu-block-drivers.rst.inc |

[PATCH v6 15/15] scripts/simplebench: add bench_prealloc.py

Benchmark for new preallocate filter. Example usage: ./bench_prealloc.py ../../build/qemu-img \ ssd-ext4:/path/to/mount/point \ ssd-xfs:/path2 hdd-ext4:/path3 hdd-xfs:/path4 The benchmark shows performance improvement (or degradation) when use new preallocate filter with qcow2

[PATCH v6 13/15] scripts/simplebench: improve view of ascii table

Introduce dynamic float precision and use percentage to show delta. Signed-off-by: Vladimir Sementsov-Ogievskiy --- scripts/simplebench/simplebench.py | 26 +- 1 file changed, 25 insertions(+), 1 deletion(-) diff --git a/scripts/simplebench/simplebench.py b/scripts/simp

[PATCH v3 00/81] target/arm: Implement SVE2

This is the first revision that has been fully tested vs ArmIE, although only with 128-bit vectors. Since ArmIE does not produce an SVE signal frame, I have a small hack in RISU to pull the vector data from the FP frame. I may try an assembly wrapper to capture the larger vector data before it ge

[PATCH v6 14/15] scripts/simplebench: improve ascii table: add difference line

Performance improvements / degradations are usually discussed in percentage. Let's make the script calculate it for us. Signed-off-by: Vladimir Sementsov-Ogievskiy --- scripts/simplebench/simplebench.py | 46 +++--- 1 file changed, 42 insertions(+), 4 deletions(-) diff -

Re: [PATCH v7 0/2] Remove EPYC mode apicid decode and use generic decode

On Tue, Sep 01, 2020 at 10:57:20AM -0500, Babu Moger wrote: > To support some of the complex topology, we introduced EPYC mode apicid > decode. > But, EPYC mode decode is running into problems. Also it can become quite a > maintenance problem in the future. So, it was decided to remove that code a

[PATCH v3 02/81] target/arm: Fix sve_zip_p vs odd vector lengths

Wrote too much with low-half zip (zip1) with vl % 512 != 0. Adjust all of the x + (y << s) to x | (y << s) as a style fix. We only ever have exact overlap between D, M, and N. Therefore we only need a single temporary, and we do not need to check for partial overlap. Reported-by: Laurent Desnog

[PATCH v3 01/81] target/arm: Fix sve_uzp_p vs odd vector lengths

Missed out on compressing the second half of a predicate with length vl % 512 > 256. Adjust all of the x + (y << s) to x | (y << s) as a general style fix. Drop the extract64 because the input uint64_t are known to be already zero-extended from the current size of the predicate. Reported-by: Lau

[PATCH v3 03/81] target/arm: Fix sve_punpk_p vs odd vector lengths

Wrote too much with punpk1 with vl % 512 != 0. Reviewed-by: Peter Maydell Reported-by: Laurent Desnogues Signed-off-by: Richard Henderson --- target/arm/sve_helper.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c index

[PATCH v3 08/81] target/arm: Split out saturating/rounding shifts from neon

Split these operations out into a header that can be shared between neon and sve. The "sat" pointer acts both as a boolean for control of saturating behavior and controls the difference in behavior between neon and sve -- QC bit or no QC bit. Widen the shift operand in the new helpers, as the SVE

Re: [PATCH 0/3] qom: Replace INTERFACE_CHECK with OBJECT_CHECK

On Thu, Sep 17, 2020 at 11:25:30AM +0400, Marc-André Lureau wrote: > Hi > > On Thu, Sep 17, 2020 at 11:19 AM Philippe Mathieu-Daudé > wrote: > > > On 9/16/20 11:31 PM, Marc-André Lureau wrote: > > > Hi > > > > > > On Wed, Sep 16, 2020 at 11:35 PM Eduardo Habkost > >

[PATCH v3 15/81] target/arm: Implement SVE2 integer add/subtract wide

Signed-off-by: Richard Henderson --- v2: Fix select offsets (laurent desnogues). --- target/arm/helper-sve.h| 16 target/arm/sve.decode | 12 target/arm/sve_helper.c| 30 ++ target/arm/translate-sve.c | 20

[PATCH v3 14/81] target/arm: Implement SVE2 integer add/subtract interleaved long

Signed-off-by: Richard Henderson --- target/arm/sve.decode | 6 ++ target/arm/translate-sve.c | 4 2 files changed, 10 insertions(+) diff --git a/target/arm/sve.decode b/target/arm/sve.decode index 70712039e4..a28172c017 100644 --- a/target/arm/sve.decode +++ b/target/arm/sve.decod

[PATCH v3 04/81] target/arm: Add ID_AA64ZFR0 fields and isar_feature_aa64_sve2

Will be used for SVE2 isa subset enablement. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- v2: Do not read zfr0 from kvm unless sve is available. --- target/arm/cpu.h| 16 target/arm/helper.c | 3 +-- target/arm/kvm64.c | 11 +++ 3 files changed, 2

[PATCH v3 17/81] target/arm: Implement PMULLB and PMULLT

Signed-off-by: Richard Henderson --- target/arm/cpu.h | 10 ++ target/arm/helper-sve.h| 1 + target/arm/sve.decode | 2 ++ target/arm/translate-sve.c | 22 ++ target/arm/vec_helper.c| 24 5 files changed, 59 insertions(

[PATCH v3 07/81] target/arm: Implement SVE2 integer unary operations (predicated)

Signed-off-by: Richard Henderson --- v2: Fix sqabs, sqneg (laurent desnogues) --- target/arm/helper-sve.h| 13 +++ target/arm/sve.decode | 7 ++ target/arm/sve_helper.c| 29 +++ target/arm/translate-sve.c | 47 ++ 4

[PATCH v3 19/81] target/arm: Implement SVE2 bitwise exclusive-or interleaved

Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 5 + target/arm/sve.decode | 5 + target/arm/sve_helper.c| 20 target/arm/translate-sve.c | 19 +++ 4 files changed, 49 insertions(+) diff --git a/target/arm/helper-sve.h b/t

[PATCH v3 23/81] target/arm: Implement SVE2 integer add/subtract long with carry

Signed-off-by: Richard Henderson --- v2: Fix sel indexing and argument order (laurent desnogues). --- target/arm/helper-sve.h| 3 +++ target/arm/sve.decode | 6 ++ target/arm/sve_helper.c| 34 ++ target/arm/translate-sve.c | 23 ++

[PATCH v3 11/81] target/arm: Implement SVE2 integer pairwise arithmetic

Signed-off-by: Richard Henderson --- v2: Load all inputs before writing any output (laurent desnogues) --- target/arm/helper-sve.h| 45 ++ target/arm/sve.decode | 8 target/arm/sve_helper.c| 76 ++ target/arm/translate-sve

Re: [PATCH 0/4] nbd reconnect new fixes

ping 03.09.2020 22:02, Vladimir Sementsov-Ogievskiy wrote: Hi! Let's continue fixing nbd reconnect feature. These series is based on "[PULL 0/6] NBD patches for 2020-09-02" Based-on: <20200902215400.2673028-1-ebl...@redhat.com> Vladimir Sementsov-Ogievskiy (4): block/nbd: fix drain dead-loc

[PATCH v3 18/81] target/arm: Implement SVE2 bitwise shift left long

Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 8 ++ target/arm/sve.decode | 8 ++ target/arm/sve_helper.c| 26 ++ target/arm/translate-sve.c | 159 + 4 files changed, 201 insertions(+) diff --git a/target/arm/helper-sve.h

[PATCH v3 06/81] target/arm: Implement SVE2 integer pairwise add and accumulate long

Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 14 target/arm/sve.decode | 5 + target/arm/sve_helper.c| 44 ++ target/arm/translate-sve.c | 39 + 4 files changed, 102 insertions(+)

[PATCH v3 37/81] target/arm: Implement SVE2 saturating multiply-add long

Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 14 ++ target/arm/sve.decode | 14 ++ target/arm/sve_helper.c| 30 + target/arm/translate-sve.c | 54 ++ 4 files changed, 112 insertions(+) diff --gi

[PATCH v3 13/81] target/arm: Implement SVE2 integer add/subtract long

Signed-off-by: Richard Henderson --- v2: Fix select offsets (laurent desnogues). --- target/arm/helper-sve.h| 24 target/arm/sve.decode | 19 target/arm/sve_helper.c| 43 +++ target/arm/translate-sve.c | 46 +++

[PATCH v3 22/81] target/arm: Implement SVE2 integer absolute difference and accumulate long

Signed-off-by: Richard Henderson --- v2: Fix select offsetting and argument order (laurent desnogues). --- target/arm/helper-sve.h| 14 ++ target/arm/sve.decode | 12 + target/arm/sve_helper.c| 23 target/arm/translate-sve.c | 55 +

[PATCH v3 45/81] target/arm: Implement SVE2 HISTCNT, HISTSEG

From: Stephen Long Signed-off-by: Stephen Long Message-Id: <20200416173109.8856-1-stepl...@quicinc.com> Signed-off-by: Richard Henderson --- v2: Fix overlap between output and input vectors. --- target/arm/helper-sve.h| 7 +++ target/arm/sve.decode | 6 ++ target/arm/sve_helper.c

[PATCH v3 24/81] target/arm: Implement SVE2 bitwise shift right and accumulate

Signed-off-by: Richard Henderson --- target/arm/sve.decode | 8 target/arm/translate-sve.c | 34 ++ 2 files changed, 42 insertions(+) diff --git a/target/arm/sve.decode b/target/arm/sve.decode index f4f0c2ade6..7783e9f0d3 100644 --- a/target/arm/sve

[PATCH v3 05/81] target/arm: Implement SVE2 Integer Multiply - Unpredicated

For MUL, we can rely on generic support. For SMULH and UMULH, create some trivial helpers. For PMUL, back in a21bb78e5817, we organized helper_gvec_pmul_b in preparation for this use. Signed-off-by: Richard Henderson --- target/arm/helper.h| 10 target/arm/sve.decode | 10 +++

[PATCH v3 12/81] target/arm: Implement SVE2 saturating add/subtract (predicated)

Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 54 +++ target/arm/sve.decode | 11 +++ target/arm/sve_helper.c| 194 ++--- target/arm/translate-sve.c | 7 ++ 4 files changed, 210 insertions(+), 56 deletions(-) diff --git a/t

[PATCH v3 27/81] target/arm: Implement SVE2 saturating extract narrow

Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 24 target/arm/sve.decode | 12 ++ target/arm/sve_helper.c| 56 + target/arm/translate-sve.c | 248 - 4 files changed, 335 insertions(+), 5 deletions(-) diff --git a/tar

[PATCH v3 29/81] target/arm: Implement SVE2 SHRN, RSHRN

Signed-off-by: Richard Henderson --- v2: Fix typo in gen_shrnb_vec (laurent desnogues) v3: Replace DO_RSHR with an inline function --- target/arm/helper-sve.h| 16 target/arm/sve.decode | 8 ++ target/arm/sve_helper.c| 54 - target/arm/translate-sve.c | 160 +

[PATCH v3 50/81] target/arm: Implement SVE2 SPLICE, EXT

From: Stephen Long Signed-off-by: Stephen Long Message-Id: <20200423180347.9403-1-stepl...@quicinc.com> [rth: Rename the trans_* functions to *_sve2.] Signed-off-by: Richard Henderson --- target/arm/sve.decode | 11 +-- target/arm/translate-sve.c | 35 +

[PATCH v3 09/81] target/arm: Implement SVE2 saturating/rounding bitwise shift left (predicated)

Signed-off-by: Richard Henderson --- v2: Shift values are always signed (laurent desnogues). --- target/arm/helper-sve.h| 54 ++ target/arm/sve.decode | 17 + target/arm/sve_helper.c| 78 ++ target/arm/translate-sve.

[PATCH v3 10/81] target/arm: Implement SVE2 integer halving add/subtract (predicated)

Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 54 ++ target/arm/sve.decode | 11 target/arm/sve_helper.c| 39 +++ target/arm/translate-sve.c | 8 ++ 4 files changed, 112 insertions(+) diff --gi

[PATCH v3 33/81] target/arm: Implement SVE2 WHILEGT, WHILEGE, WHILEHI, WHILEHS

Rename the existing sve_while (less-than) helper to sve_whilel to make room for a new sve_whileg helper for greater-than. Signed-off-by: Richard Henderson --- v2: Use a new helper function to implement this. --- target/arm/helper-sve.h| 3 +- target/arm/sve.decode | 2 +- target/arm/s

[PATCH v3 56/81] target/arm: Implement SVE2 integer multiply-add (indexed)

Signed-off-by: Richard Henderson --- target/arm/sve.decode | 8 target/arm/translate-sve.c | 23 +++ 2 files changed, 31 insertions(+) diff --git a/target/arm/sve.decode b/target/arm/sve.decode index fa0a572da6..467a93052f 100644 --- a/target/arm/sve.decode +++

[PATCH v3 28/81] target/arm: Implement SVE2 floating-point pairwise

From: Stephen Long Signed-off-by: Stephen Long Reviewed-by: Richard Henderson Signed-off-by: Richard Henderson --- v2: Load all inputs before writing any output (laurent desnogues) --- target/arm/helper-sve.h| 35 + target/arm/sve.decode | 8 +++ targ

[PATCH v3 31/81] target/arm: Implement SVE2 UQSHRN, UQRSHRN

Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 16 +++ target/arm/sve.decode | 4 ++ target/arm/sve_helper.c| 24 ++ target/arm/translate-sve.c | 93 ++ 4 files changed, 137 insertions(+) diff --git a/target/arm/helper-

[PATCH v3 59/81] target/arm: Implement SVE2 integer multiply long (indexed)

Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 5 + target/arm/sve.decode | 16 target/arm/sve_helper.c| 23 +++ target/arm/translate-sve.c | 24 4 files changed, 64 insertions(+), 4 deletions(-) diff

[PATCH v3 39/81] target/arm: Implement SVE2 integer multiply-add long

Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 28 ++ target/arm/sve.decode | 11 ++ target/arm/sve_helper.c| 18 + target/arm/translate-sve.c | 76 ++ 4 files changed, 133 insertions(+) diff --git a/target/a

[PATCH v3 16/81] target/arm: Implement SVE2 integer multiply long

Exclude PMULL from this category for the moment. Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 15 +++ target/arm/sve.decode | 9 + target/arm/sve_helper.c| 31 +++ target/arm/translate-sve.c | 9 + 4 files ch

[PATCH v3 58/81] target/arm: Implement SVE2 saturating multiply-add (indexed)

Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 9 + target/arm/sve.decode | 18 ++ target/arm/sve_helper.c| 30 ++ target/arm/translate-sve.c | 32 4 files changed, 81 insertions(+),

[PATCH v3 32/81] target/arm: Implement SVE2 SQSHRN, SQRSHRN

This completes the section "SVE2 bitwise shift right narrow". Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 16 ++ target/arm/sve.decode | 4 ++ target/arm/sve_helper.c| 24 + target/arm/translate-sve.c | 105 + 4 f

[PATCH v3 43/81] target/arm: Implement SVE2 SUBHNB, SUBHNT

From: Stephen Long Signed-off-by: Stephen Long Message-Id: <20200417162231.10374-4-stepl...@quicinc.com> Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 8 target/arm/sve.decode | 2 ++ target/arm/sve_helper.c| 10 ++ target/arm/translate-sve.c |

[PATCH v3 20/81] target/arm: Implement SVE2 bitwise permute

Signed-off-by: Richard Henderson --- target/arm/cpu.h | 5 +++ target/arm/helper-sve.h| 15 target/arm/sve.decode | 6 target/arm/sve_helper.c| 73 ++ target/arm/translate-sve.c | 36 +++ 5 files changed, 1

[PATCH v3 47/81] target/arm: Implement SVE2 scatter store insns

From: Stephen Long Add decoding logic for SVE2 64-bit/32-bit scatter non-temporal store insns. 64-bit * STNT1B (vector plus scalar) * STNT1H (vector plus scalar) * STNT1W (vector plus scalar) * STNT1D (vector plus scalar) 32-bit * STNT1B (vector plus scalar) * STNT1H (vector plus scalar) * STNT

[PATCH v3 63/81] target/arm: Implement SVE2 multiply-add long (indexed)

Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 17 + target/arm/sve.decode | 18 ++ target/arm/sve_helper.c| 16 target/arm/translate-sve.c | 20 4 files changed, 71 insertions(+) diff --git a/targe

[PATCH v3 36/81] target/arm: Implement SVE2 MATCH, NMATCH

From: Stephen Long Reviewed-by: Richard Henderson Signed-off-by: Stephen Long Message-Id: <20200415145915.2859-1-stepl...@quicinc.com> [rth: Expanded comment for do_match2] Signed-off-by: Richard Henderson --- v2: Apply esz_mask to input pg to fix output flags. --- target/arm/helper-sve.h

[PATCH v3 21/81] target/arm: Implement SVE2 complex integer add

Signed-off-by: Richard Henderson --- v2: Fix subtraction ordering (laurent desnogues). --- target/arm/helper-sve.h| 10 + target/arm/sve.decode | 9 target/arm/sve_helper.c| 42 ++ target/arm/translate-sve.c | 31 +

[PATCH v3 25/81] target/arm: Implement SVE2 bitwise shift and insert

Signed-off-by: Richard Henderson --- target/arm/sve.decode | 5 + target/arm/translate-sve.c | 10 ++ 2 files changed, 15 insertions(+) diff --git a/target/arm/sve.decode b/target/arm/sve.decode index 7783e9f0d3..90a9d6552a 100644 --- a/target/arm/sve.decode +++ b/target/arm/sv

[PATCH v3 66/81] target/arm: Implement SVE mixed sign dot product

Signed-off-by: Richard Henderson --- target/arm/helper.h| 2 ++ target/arm/sve.decode | 4 target/arm/translate-sve.c | 16 target/arm/vec_helper.c| 18 ++ 4 files changed, 40 insertions(+) diff --git a/target/arm/helper.h b/target/arm/hel

[PATCH v3 49/81] target/arm: Implement SVE2 FMMLA

From: Stephen Long Signed-off-by: Stephen Long Message-Id: <20200422165503.13511-1-stepl...@quicinc.com> [rth: Fix indexing in helpers, expand macro to straight functions.] Signed-off-by: Richard Henderson --- target/arm/cpu.h | 10 ++ target/arm/helper-sve.h| 3 ++ target/a

[PATCH v3 40/81] target/arm: Implement SVE2 complex integer multiply-add

Signed-off-by: Richard Henderson --- v2: Fix do_sqrdmlah_d (laurent desnogues) --- target/arm/helper-sve.h| 18 target/arm/vec_internal.h | 5 + target/arm/sve.decode | 5 + target/arm/sve_helper.c| 42 ++ target/arm/tra

[PATCH v3 26/81] target/arm: Implement SVE2 integer absolute difference and accumulate

Signed-off-by: Richard Henderson --- target/arm/sve.decode | 6 ++ target/arm/translate-sve.c | 21 + 2 files changed, 27 insertions(+) diff --git a/target/arm/sve.decode b/target/arm/sve.decode index 90a9d6552a..b5450b1d4d 100644 --- a/target/arm/sve.decode +++ b/t

[PATCH v3 38/81] target/arm: Implement SVE2 saturating multiply-add high

SVE2 has two additional sizes of the operation and unlike NEON, there is no saturation flag. Create new entry points for SVE2 that do not set QC. Signed-off-by: Richard Henderson --- target/arm/helper.h| 17 target/arm/sve.decode | 5 ++ target/arm/translate-sve.c | 18 +++

[PATCH v3 69/81] target/arm: Implement SVE2 crypto constructive binary operations

Signed-off-by: Richard Henderson --- target/arm/cpu.h | 5 + target/arm/sve.decode | 4 target/arm/translate-sve.c | 16 3 files changed, 25 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index f5052a58a4..67b2834035 100644 --- a/target/

[PATCH v3 51/81] target/arm: Pass separate addend to {U, S}DOT helpers

For SVE, we potentially have a 4th argument coming from the movprfx instruction. Currently we do not optimize movprfx, so the problem is not visible. Signed-off-by: Richard Henderson --- target/arm/helper.h | 20 +++--- target/arm/sve.decode | 7 +- target/arm/translate

[PATCH v3 54/81] target/arm: Split out formats for 3 vectors + 1 index

Used by FMLA and DOT, but will shortly be used more. Split FMLA from FMLS to avoid an extra sub field; similarly for SDOT from UDOT. Signed-off-by: Richard Henderson --- target/arm/sve.decode | 29 +++-- target/arm/translate-sve.c | 38 ---

[PATCH v3 30/81] target/arm: Implement SVE2 SQSHRUN, SQRSHRUN

Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 16 +++ target/arm/sve.decode | 4 ++ target/arm/sve_helper.c| 35 ++ target/arm/translate-sve.c | 98 ++ 4 files changed, 153 insertions(+) diff --git a/target/arm/hel

[PATCH v3 77/81] target/arm: Implement 128-bit ZIP, UZP, TRN

Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 3 ++ target/arm/sve.decode | 8 ++ target/arm/sve_helper.c| 29 +-- target/arm/translate-sve.c | 58 ++ 4 files changed, 90 insertions(+), 8 deletions(-) diff --g

[PATCH v3 42/81] target/arm: Implement SVE2 RADDHNB, RADDHNT

From: Stephen Long Signed-off-by: Stephen Long Message-Id: <20200417162231.10374-3-stepl...@quicinc.com> Signed-off-by: Richard Henderson --- v2: Fix round bit type (laurent desnogues) --- target/arm/helper-sve.h| 8 target/arm/sve.decode | 2 ++ target/arm/sve_helper.c

[PATCH v3 57/81] target/arm: Implement SVE2 saturating multiply-add high (indexed)

Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 14 + target/arm/sve.decode | 8 target/arm/sve_helper.c| 40 ++ target/arm/translate-sve.c | 8 4 files changed, 70 insertions(+) diff --git a/target/ar

[PATCH v3 81/81] target/arm: Enable SVE2 and some extensions

Signed-off-by: Richard Henderson --- target/arm/cpu64.c | 11 +++ 1 file changed, 11 insertions(+) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 3c2b3d9599..46b8a3908c 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -667,6 +667,17 @@ static void aarch64_max_initf

[PATCH v3 34/81] target/arm: Implement SVE2 WHILERW, WHILEWR

Signed-off-by: Richard Henderson --- v2: Fix decodetree typo --- target/arm/sve.decode | 3 ++ target/arm/translate-sve.c | 62 ++ 2 files changed, 65 insertions(+) diff --git a/target/arm/sve.decode b/target/arm/sve.decode index b7038f9f57..19d503e2f4 1

[PATCH v3 46/81] target/arm: Implement SVE2 XAR

In addition, use the same vector generator interface for AdvSIMD. This fixes a bug in which the AdvSIMD insn failed to clear the high bits of the SVE register. Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 4 ++ target/arm/helper.h| 2 + target/arm/translate-a64.h

[PATCH v3 35/81] target/arm: Implement SVE2 bitwise ternary operations

Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 6 ++ target/arm/sve.decode | 12 +++ target/arm/sve_helper.c| 50 + target/arm/translate-sve.c | 213 + 4 files changed, 281 insertions(+) diff --git a/target/arm/helper-sv

[PATCH v3 48/81] target/arm: Implement SVE2 gather load insns

From: Stephen Long Add decoding logic for SVE2 64-bit/32-bit gather non-temporal load insns. 64-bit * LDNT1SB * LDNT1B (vector plus scalar) * LDNT1SH * LDNT1H (vector plus scalar) * LDNT1SW * LDNT1W (vector plus scalar) * LDNT1D (vector plus scalar) 32-bit * LDNT1SB * LDNT1B (vector plus scalar

[PATCH v3 62/81] target/arm: Implement SVE2 saturating multiply high (indexed)

Signed-off-by: Richard Henderson --- target/arm/helper.h| 14 ++ target/arm/sve.decode | 8 target/arm/translate-sve.c | 8 target/arm/vec_helper.c| 88 ++ 4 files changed, 118 insertions(+) diff --git a/target/arm/helper.h b/t

[PATCH v3 65/81] target/arm: Implement SVE mixed sign dot product (indexed)

Signed-off-by: Richard Henderson --- target/arm/cpu.h | 5 +++ target/arm/helper.h| 4 +++ target/arm/sve.decode | 4 +++ target/arm/translate-sve.c | 18 +++ target/arm/vec_helper.c| 66 ++ 5 files changed, 97 insertions(+

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