[PATCH v4 04/18] qom: DECLARE_*_CHECKERS macros

Sometimes the typedefs are buried inside another header, but we want to benefit from the automatic definition of type cast functions. Introduce macros that will let type checkers be defined when typedefs are already available. Reviewed-by: Daniel P. Berrangé Signed-off-by: Eduardo Habkost --- C

[PATCH v4 12/18] [automated] Use DECLARE_*CHECKER* macros (pass 2)

$ ./scripts/codeconverter/converter.py -i \ --pattern=TypeCheckMacro $(git grep -l '' -- '*.[ch]') Reviewed-by: Juan Quintela Signed-off-by: Eduardo Habkost --- Changes v3 -> v4: none Changes series v2 -> v3: this is a new patch added in series v3 The script was re-run after rebase and aft

[PATCH v4 06/18] codeconverter: script for automating QOM code cleanups

This started as a simple script that scanned for regular expressions, but became more and more complex when exceptions to the rules were found. I don't know if this should be maintained in the QEMU source tree long term (maybe it can be reused for other code transformations that Coccinelle can't h

[PATCH v4 13/18] [automated] Use DECLARE_*CHECKER* macros (pass 3)

$ ./scripts/codeconverter/converter.py -i \ --pattern=TypeCheckMacro $(git grep -l '' -- '*.[ch]') Signed-off-by: Eduardo Habkost --- Changes series v3 -> v4: this is a new patch added in series v4 The script was re-run after series rebase. This is being submitted as a separate patch to mak

Re: [PATCH v2 1/7] target: rename all *_do_interupt functions to _do_interrupt_locked

On 8/19/20 11:28 AM, Robert Foley wrote: > The rename of all *_do_interrupt functions to *_do_interrupt_locked > is preparation for pushing the BQL lock around these functions > down into the per-arch implementation of *_do_interrupt. > In a later patch which pushes down the lock, we will add > a n

[PATCH v4 10/18] [automated] Move QOM typedefs and add missing includes (pass 3)

Some typedefs and macros are defined after the type check macros. This makes it difficult to automatically replace their definitions with OBJECT_DECLARE_TYPE. Patch generated using: $ ./scripts/codeconverter/converter.py -i \ --pattern=QOMStructTypedefSplit $(git grep -l '' -- '*.[ch]') whic

Re: [PATCH 2/3] tcg: Eliminate one store for in-place 128-bit dup_mem

Le ven. 28 août 2020 20:04, Richard Henderson a écrit : > Do not store back to the exact memory from which we just loaded. > > Signed-off-by: Richard Henderson > Reviewed-by: Philippe Mathieu-Daudé --- > tcg/tcg-op-gvec.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff -

[PATCH v4 18/18] [automated] Use OBJECT_DECLARE_SIMPLE_TYPE when possible

Generated using: $ ./scripts/codeconverter/converter.py -i \ --pattern=ObjectDeclareType $(git grep -l '' -- '*.[ch]') Reviewed-by: Daniel P. Berrangé Signed-off-by: Eduardo Habkost --- Changes v3 -> v4: none Changes v2 -> v3: none Changes v1 -> v2: none --- Cc: "Marc-André Lureau" Cc:

Re: [PATCH 1/3] softmmu/cpus: Only set parallel_cpus for SMP

Le ven. 28 août 2020 20:04, Richard Henderson a écrit : > Do not set parallel_cpus if there is only one cpu instantiated. > This will allow tcg to use serial code to implement atomics. > > Signed-off-by: Richard Henderson > Reviewed-by: Philippe Mathieu-Daudé --- > softmmu/cpus.c | 11 ++

[PATCH v4 14/18] [semi-automated] Use DECLARE_*CHECKER* when possible (--force mode)

Separate run of the TypeCheckMacro converter using the --force flag, for the cases where typedefs weren't found in the same header nor in typedefs.h. Generated initially using: $ ./scripts/codeconverter/converter.py --force -i \ --pattern=TypeCheckMacro $(git grep -l '' -- '*.[ch]') Then eac

Re: [PATCH v2 01/76] tests/tcg: Add microblaze to arches filter

Le ven. 28 août 2020 16:20, Richard Henderson a écrit : > Not attempting to use a single cross-compiler for both > big-endian and little-endian at this time. > > Reviewed-by: Edgar E. Iglesias > Signed-off-by: Richard Henderson > Reviewed-by: Philippe Mathieu-Daudé --- > tests/tcg/configure

Re: [PATCH v2 03/76] tests/tcg: Do not require FE_* exception bits

Le ven. 28 août 2020 16:22, Richard Henderson a écrit : > Define anything that is missing as 0, so that flags & FE_FOO > is false for any missing FOO. > > Reviewed-by: Edgar E. Iglesias > Signed-off-by: Richard Henderson > Reviewed-by: Philippe Mathieu-Daudé --- > tests/tcg/multiarch/float_

Re: [PULL 00/18] Usb 20200831 patches

; > are available in the Git repository at: > > git://git.kraxel.org/qemu tags/usb-20200831-pull-request > > for you to fetch changes up to b946434f2659a182afc17e155be6791ebfb302eb: > > usb: fix setup_len

[PATCH v4 16/18] [automated] Use OBJECT_DECLARE_TYPE where possible (pass 2)

Replace DECLARE_OBJ_CHECKERS with OBJECT_DECLARE_TYPE where the typedefs can be safely removed. Generated running: $ ./scripts/codeconverter/converter.py -i \ --pattern=DeclareObjCheckers $(git grep -l '' -- '*.[ch]') Signed-off-by: Eduardo Habkost --- Changes v3 -> v4: none Changes series v

[PATCH v4 17/18] [automated] Use OBJECT_DECLARE_TYPE where possible (pass 3)

Replace DECLARE_OBJ_CHECKERS with OBJECT_DECLARE_TYPE where the typedefs can be safely removed. Generated running: $ ./scripts/codeconverter/converter.py -i \ --pattern=DeclareObjCheckers $(git grep -l '' -- '*.[ch]') Signed-off-by: Eduardo Habkost --- Changes series v3 -> v4: this is a new p

Re: [PATCH 2/4] hda-audio: Set instance_size at base class

Le mer. 26 août 2020 19:12, Eduardo Habkost a écrit : > Setting instance_size correctly at the base class will help us > avoid mistakes when declaring new subclasses. > > Signed-off-by: Eduardo Habkost > Reviewed-by: Philippe Mathieu-Daudé --- > Cc: Gerd Hoffmann > Cc: qemu-devel@nongnu.org

Re: [PATCH v2 02/76] tests/tcg: Do not require FE_TOWARDZERO

Le ven. 28 août 2020 16:22, Richard Henderson a écrit : > This is optional in ISO C, and not all cpus provide it. > > Reviewed-by: Edgar E. Iglesias > Signed-off-by: Richard Henderson > Reviewed-by: Philippe Mathieu-Daudé --- > tests/tcg/multiarch/float_convs.c | 2 ++ > tests/tcg/multiarch

Re: [PATCH v2 2/7] target/arm: add ARMCPUClass->do_interrupt_locked

On 8/19/20 11:28 AM, Robert Foley wrote: > Adding ->do_interrupt_locked to ARMCPUClass is preparation for > pushing the BQL down into the per-arch implementation of ->do_interrupt. > > This is needed since ARM's *_cpu_exec_interrupt calls to *_do_interrupt. > With the push down of the BQL into *_c

Re: [PATCH] main-loop: Fix comment

Le jeu. 27 août 2020 19:55, Stefan Weil a écrit : > Signed-off-by: Stefan Weil > Reviewed-by: Philippe Mathieu-Daudé --- > include/qemu/main-loop.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/include/qemu/main-loop.h b/include/qemu/main-loop.h > index 8e98613656.

[PATCH v4 15/18] [automated] Use OBJECT_DECLARE_TYPE where possible

Replace DECLARE_OBJ_CHECKERS with OBJECT_DECLARE_TYPE where the typedefs can be safely removed. Generated running: $ ./scripts/codeconverter/converter.py -i \ --pattern=DeclareObjCheckers $(git grep -l '' -- '*.[ch]') Reviewed-by: Daniel P. Berrangé Signed-off-by: Eduardo Habkost --- Changes

Re: [PATCH 12/16] tests: do not print benchmark output to stdout

Le ven. 28 août 2020 13:11, a écrit : > From: Marc-André Lureau > > As this makes the TAP output invalid. Use g_test_message(). > > Signed-off-by: Marc-André Lureau > Reviewed-by: Philippe Mathieu-Daudé --- > tests/benchmark-crypto-cipher.c | 8 > tests/benchmark-crypto-hash.c |

Re: [PATCH] Deprecate lm32 port

Le jeu. 27 août 2020 14:07, Michael Walle a écrit : > Am 27. August 2020 13:32:59 MESZ schrieb Peter Maydell < > peter.mayd...@linaro.org>: > >Deprecate our lm32 target support. Michael Walle (former lm32 > >maintainer) > >suggested that we do this in 2019: > > https://www.mail-archive.com/qemu-d

Re: [PATCH 3/3] tcg: Implement 256-bit dup for tcg_gen_gvec_dup_mem

Le ven. 28 août 2020 20:04, Richard Henderson a écrit : > We already support duplication of 128-bit blocks. This extends > that support to 256-bit blocks. This will be needed by SVE2. > > Signed-off-by: Richard Henderson > Reviewed-by: Philippe Mathieu-Daudé --- > tcg/tcg-op-gvec.c | 52 ++

Re: [PATCH 3/4] tracetool: add input filename and line number to Event

Le jeu. 27 août 2020 16:32, Stefan Hajnoczi a écrit : > Store the input filename and line number in Event. > > A later patch will use this to improve error messages. > > Signed-off-by: Stefan Hajnoczi > Reviewed-by: Philippe Mathieu-Daudé --- > scripts/tracetool/__init__.py | 27

Re: [PATCH] hw/ide: check null block pointer before blk_drain

Le jeu. 27 août 2020 13:47, P J P a écrit : > From: Prasad J Pandit > > While cancelling an i/o operation via ide_cancel_dma_sync(), > check for null block pointer before calling blk_drain(). Avoid > null pointer dereference. > > -> > https://ruhr-uni-bochum.sciebo.de/s/NNWP2GfwzYKeKwE?path=%2F

Re: [PATCH] docs/system: Fix grammar in documentation

Le jeu. 27 août 2020 19:31, Stefan Weil a écrit : > Signed-off-by: Stefan Weil > Reviewed-by: Philippe Mathieu-Daudé --- > docs/system/build-platforms.rst | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/docs/system/build-platforms.rst > b/docs/system/build-plat

Re: [PATCH v2 07/76] target/microblaze: Split out EAR from env->sregs

Le ven. 28 août 2020 16:23, Richard Henderson a écrit : > Continue eliminating the sregs array in favor of individual members. > > Signed-off-by: Richard Henderson > Reviewed-by: Philippe Mathieu-Daudé --- > target/microblaze/cpu.h | 1 + > target/microblaze/gdbstub.c | 4 ++-- > tar

Re: [PATCH] libvhost-user: Add GCC_FMT_ATTR and fix format string

Le jeu. 27 août 2020 23:09, Stefan Weil a écrit : > Signed-off-by: Stefan Weil > --- > contrib/libvhost-user/libvhost-user.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/contrib/libvhost-user/libvhost-user.c > b/contrib/libvhost-user/libvhost-user.c > index 53f16

Re: [PATCH v2] hw/arm/sbsa-ref: add "reg" property to DT cpu nodes

Le jeu. 27 août 2020 14:45, Leif Lindholm a écrit : > The sbsa-ref platform uses a minimal device tree to pass amount of memory > as well as number of cpus to the firmware. However, when dumping that > minimal dtb (with -M sbsa-virt,dumpdtb=), the resulting blob > generates a warning when decompi

Re: [PATCH v2 10/76] target/microblaze: Split out BTR from env->sregs

Le ven. 28 août 2020 16:26, Richard Henderson a écrit : > Continue eliminating the sregs array in favor of individual members. > Does not correct the width of BTR, yet. > > Signed-off-by: Richard Henderson > Reviewed-by: Philippe Mathieu-Daudé --- > target/microblaze/cpu.h | 1 + > tar

Re: [PATCH] Deprecate lm32 port

Le jeu. 27 août 2020 16:51, Thomas Huth a écrit : > On 27/08/2020 16.19, Peter Maydell wrote: > > On Thu, 27 Aug 2020 at 14:52, Thomas Huth wrote: > >> What's next? moxie? ... apart from the tree-wide clean-ups and trivial > >> fixes, moxie did not have any major updates since 2013 when it has b

Re: [PATCH 1/4] tracetool: add output filename command-line argument

Le jeu. 27 août 2020 16:30, Stefan Hajnoczi a écrit : > The tracetool.py script writes to stdout. This means the output filename > is not available to the script. Add the output filename to the > command-line so that the script has access to the filename. > > This also simplifies the tracetool.py

Re: [PATCH v2 62/76] target/microblaze: Tidy mb_cpu_dump_state

Hi Richard, Le ven. 28 août 2020 16:46, Richard Henderson a écrit : > Using lookup_symbol is quite slow; remove that. Decode the > Can we add some runtime option to enable its use instead? various bits of iflags; only show imm, btaken, btarget when > they are relevant to iflags. Improve form

Re: [PATCH v2 3/7] target/cris: add CRISCPUClass->do_interrupt_locked

On 8/19/20 11:28 AM, Robert Foley wrote: > Adding ->do_interrupt_locked to CRISCPUClass is preparation for > pushing the BQL down into the per-arch implementation of ->do_interrupt. > > This is needed since Cris's *_cpu_exec_interrupt calls to *_do_interrupt. > With the push down of the BQL into *

Re: [PATCH v2 09/76] target/microblaze: Split out FSR from env->sregs

Le ven. 28 août 2020 16:25, Richard Henderson a écrit : > Continue eliminating the sregs array in favor of individual members. > Does not correct the width of FSR, yet. > > Signed-off-by: Richard Henderson > Reviewed-by: Philippe Mathieu-Daudé --- > target/microblaze/cpu.h | 1 + >

Re: [PATCH 00/20] RX target update

Hello Yoshinori, Le jeu. 27 août 2020 14:43, Yoshinori Sato a écrit : > Hello. > This series Renesas RX updates. > > It consists of the following contents. > * Update firmware loader. > * Rewrite peripheal modules (Timer and SCI). > - Unified SH4 module. > - Using clock API > * New peripheal

Re: [PATCH v2 50/76] target/microblaze: Replace MSR_EE_FLAG with MSR_EE

Le ven. 28 août 2020 16:42, Richard Henderson a écrit : > There's no reason to define MSR_EE_FLAG; we can just use the > original MSR_EE define. Document the other flags copied into > tb_flags with iflag to reserve those bits. > > Signed-off-by: Richard Henderson > Reviewed-by: Philippe Mathie

Re: [PATCH v2 23/76] target/microblaze: Rename env_* tcg variables to cpu_*

Le ven. 28 août 2020 16:36, Richard Henderson a écrit : > This is cpu_imm, cpu_btaken, cpu_iflags, cpu_res_addr and cpu_res_val. > It is standard for these file-scope globals to begin with cpu_*. > > Signed-off-by: Richard Henderson > Reviewed-by: Philippe Mathieu-Daudé --- > target/microbla

Re: [PATCH v2 32/76] target/microblaze: Remove empty D macros

Le ven. 28 août 2020 16:32, Richard Henderson a écrit : > This is never used in op_helper.c and translate.c. There are > two trivial uses in helper.c which can be improved by always > logging MMU_EXCP to CPU_LOG_INT. > > Signed-off-by: Richard Henderson > Reviewed-by: Philippe Mathieu-Daudé

Re: [PATCH v2 4/7] target: Push BQL on ->do_interrupt down into per-arch implementation

On 8/19/20 11:28 AM, Robert Foley wrote: > avr is another exception. avr, arm and cris all had a similar > case where their *_cpu_exec_interrupt was calling to > the CPUClass ->do_interrupt. This causes an issue when we push > the lock down since ->do_interrupt will try to acquire the BQL, but >

Re: [PATCH] gitlab-ci.yml: Run check-qtest and check-unit at the end of the fuzzer job

Hi Thomas, Le lun. 31 août 2020 17:33, Thomas Huth a écrit : > The fuzzer job finishes quite early, so we can run the unit tests and > qtests with -fsanitize=address here without extending the total test time. > > Signed-off-by: Thomas Huth > --- > .gitlab-ci.yml | 5 +++-- > 1 file changed, 3

Re: [PATCH v2 5/7] accel/tcg: Change BQL critical section in cpu_handle_interrupt

On 8/19/20 11:28 AM, Robert Foley wrote: > @@ -625,7 +624,6 @@ static inline bool cpu_handle_interrupt(CPUState *cpu, > } > > /* If we exit via cpu_loop_exit/longjmp it is reset in cpu_exec */ > -qemu_mutex_unlock_iothread(); The comment no longer has an "it" to referen

Re: [PATCH v2 6/7] target: rename all *_cpu_exec_interrupt functions to *_cpu_exec_interrupt_locked

On 8/19/20 11:28 AM, Robert Foley wrote: > The rename of all *_cpu_exec_interrupt functions to > *_cpu_exec_interrupt_locked is preparation for pushing the BQL lock > around these functions down into the per-arch implementation of > *_cpu_exec_interrupt. In a later patch, which pushes down the loc

Re: [PATCH v2 2/7] target/arm: add ARMCPUClass->do_interrupt_locked

On 8/31/20 2:18 PM, Richard Henderson wrote: > On 8/19/20 11:28 AM, Robert Foley wrote: >> Adding ->do_interrupt_locked to ARMCPUClass is preparation for >> pushing the BQL down into the per-arch implementation of ->do_interrupt. >> >> This is needed since ARM's *_cpu_exec_interrupt calls to *_do_i

Re: [PATCH] libvhost-user: Add GCC_FMT_ATTR and fix format string

On Thu, Aug 27, 2020 at 5:09 PM Stefan Weil wrote: > > Signed-off-by: Stefan Weil Reviewed-by: Raphael Norwitz > --- > contrib/libvhost-user/libvhost-user.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/contrib/libvhost-user/libvhost-user.c > b/contrib/libvhost

[REPORT] Nightly Performance Tests - Monday, August 31, 2020

Host CPU : Intel(R) Core(TM) i7-8750H CPU @ 2.20GHz Host Memory : 15.49 GB Start Time (UTC) : 2020-08-31 21:30:01 End Time (UTC) : 2020-08-31 22:03:18 Execution Time : 0:33:17.321826 Status : SUCCESS Note: Changes denoted by '-' are less than 0.01%. -

Re: [PATCH v2 7/7] target: Push BQL on ->cpu_exec_interrupt down into per-arch implementation

On 8/19/20 11:28 AM, Robert Foley wrote: > diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c > index 499a8bdc5e..c4e54baa6f 100644 > --- a/accel/tcg/cpu-exec.c > +++ b/accel/tcg/cpu-exec.c > @@ -599,7 +599,6 @@ static inline bool cpu_handle_interrupt(CPUState *cpu, > True when it

Re: [PATCH v2 62/76] target/microblaze: Tidy mb_cpu_dump_state

On 8/31/20 2:08 PM, Philippe Mathieu-Daudé wrote: > Hi Richard,  > > Le ven. 28 août 2020 16:46, Richard Henderson > a écrit : > > Using lookup_symbol is quite slow; remove that.  Decode the > > > Can we add some runtime option to enable its use instead

Re: [PATCH v2 62/76] target/microblaze: Tidy mb_cpu_dump_state

Le mar. 1 sept. 2020 00:16, Richard Henderson a écrit : > On 8/31/20 2:08 PM, Philippe Mathieu-Daudé wrote: > > Hi Richard, > > > > Le ven. 28 août 2020 16:46, Richard Henderson < > richard.hender...@linaro.org > > > a écrit : > > > > Using lookup_symbol i

[PATCH 1/1] tcg: Adjust simd_desc size encoding

With larger vector sizes, it turns out oprsz == maxsz, and we only need to represent mismatch for oprsz <= 32. We do, however, need to represent larger oprsz and do so without reducing SIMD_DATA_BITS. Reduce the size of the oprsz field and increase the maxsz field. Steal the oprsz value of 24 to

[PATCH 0/1] tcg: Adjust simd_desc size encoding

Frank, this is intended to address the vector size limitation that you encountered with the risc-v rvv patch set, as per https://lists.gnu.org/archive/html/qemu-devel/2020-08/msg07924.html although not exactly like that email says. This will allow vectors up to 2k bytes in length. Please test, i

QEMU | Pipeline #184069766 has failed for master | 2f4c51c0

Your pipeline has failed. Project: QEMU ( https://gitlab.com/qemu-project/qemu ) Branch: master ( https://gitlab.com/qemu-project/qemu/-/commits/master ) Commit: 2f4c51c0 ( https://gitlab.com/qemu-project/qemu/-/commit/2f4c51c0f384d7888a04b4815861e6d5fd244d75 ) Commit Message: Merge remote-tr

RE: [RFC PATCH v3 30/34] Hexagon (target/hexagon) TCG for instructions with multiple definitions

> -Original Message- > From: Richard Henderson > Sent: Monday, August 31, 2020 1:20 PM > To: Taylor Simpson ; qemu-devel@nongnu.org > Cc: phi...@redhat.com; laur...@vivier.eu; riku.voi...@iki.fi; > aleksandar.m.m...@gmail.com; a...@rev.ng > Subject: Re: [RFC PATCH v3 30/34] Hexagon (targ

Re: [PATCH 1/1] tcg: Adjust simd_desc size encoding

Le mar. 1 sept. 2020 00:31, Richard Henderson a écrit : > With larger vector sizes, it turns out oprsz == maxsz, and we only > need to represent mismatch for oprsz <= 32. We do, however, need > to represent larger oprsz and do so without reducing SIMD_DATA_BITS. > > Reduce the size of the oprsz

RE: [PATCH] WHPX: vmware cpuid leaf for tsc and apic frequency

Can I please get some eyes on this? > -Original Message- > From: Sunil Muthuswamy > Sent: Thursday, July 30, 2020 3:11 PM > To: Paolo Bonzini ; Richard Henderson > ; Eduardo Habkost > Cc: qemu-devel@nongnu.org; Stefan Weil > Subject: [PATCH] WHPX: vmware cpuid leaf for tsc and apic freq

Re: [PATCH v2 2/7] target/arm: add ARMCPUClass->do_interrupt_locked

Le mar. 1 sept. 2020 00:02, Richard Henderson a écrit : > On 8/31/20 2:18 PM, Richard Henderson wrote: > > On 8/19/20 11:28 AM, Robert Foley wrote: > >> Adding ->do_interrupt_locked to ARMCPUClass is preparation for > >> pushing the BQL down into the per-arch implementation of ->do_interrupt. > >

RE: [RFC PATCH v3 00/34] Hexagon patch series

> -Original Message- > From: Richard Henderson > Sent: Monday, August 31, 2020 2:44 PM > To: Taylor Simpson ; qemu-devel@nongnu.org > Cc: phi...@redhat.com; laur...@vivier.eu; riku.voi...@iki.fi; > aleksandar.m.m...@gmail.com; a...@rev.ng > Subject: Re: [RFC PATCH v3 00/34] Hexagon patch

[PATCH v2 3/3] spapr: Remove unnecessary DRC type-checker macros

spapr_drc.h includes typechecker macro boilerplate for the many different DRC subclasses. However, most of these types don't actually have different data in their class and/or instance, making these unneeded, unused, and in fact a bad idea. Remove them. Signed-off-by: David Gibson --- include/

[PATCH v2 0/3] ppc: Fixes for class and instance size problems

As requested, some fixes for the ppc things found by Eduardo's scripts. Changes since v1: * Rewrote 3/3 to make a more sensible fix Cédric Le Goater (1): ppc/pnv: Fix TypeInfo of PnvLpcController abstract class David Gibson (2): adb: Correct class size on TYPE_ADB_DEVICE spapr: Remove unn

Re: [PATCH 3/3] spapr: Correct type for SPAPR_DRC_PCI

On Wed, Aug 26, 2020 at 12:21:37PM -0400, Eduardo Habkost wrote: > On Tue, Aug 25, 2020 at 09:16:27PM +1000, David Gibson wrote: > > TYPE_SPAPR_DRC_PCI inherits from TYPE_SPAPR_DRC_PHYSICAL, so its checker > > macro should use the corresponding instance type. We got away with it > > because we nev

[PATCH v2 2/3] ppc/pnv: Fix TypeInfo of PnvLpcController abstract class

From: Cédric Le Goater It was missing the instance_size field. Cc: Eduardo Habkost Signed-off-by: Cédric Le Goater Message-Id: <20200822083920.2668930-1-...@kaod.org> Signed-off-by: David Gibson --- hw/ppc/pnv_lpc.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/hw/ppc

[PATCH v2 1/3] adb: Correct class size on TYPE_ADB_DEVICE

The TypeInfo incorrectly just lets the class size be inherited. It won't actually break things, since the class is abstract, but we should get it right. Signed-off-by: David Gibson --- hw/input/adb.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/input/adb.c b/hw/input/adb.c index 013fc

Re: [PULL 00/76] target/microblaze improvements

Patchew URL: https://patchew.org/QEMU/20200831160601.833692-1-richard.hender...@linaro.org/ Hi, This series seems to have some coding style problems. See output below for more information: Type: series Message-id: 20200831160601.833692-1-richard.hender...@linaro.org Subject: [PULL 00/76] targ

Re: [PULL 00/76] target/microblaze improvements

Patchew URL: https://patchew.org/QEMU/20200831160601.833692-1-richard.hender...@linaro.org/ Hi, This series failed the docker-mingw@fedora build test. Please find the testing commands and their output below. If you have Docker installed, you can probably reproduce it locally. === TEST SCRIPT

Re: [PATCH v7 0/8] Generalize start-powered-off property from ARM

David Gibson writes: > On Wed, Aug 26, 2020 at 02:55:27AM -0300, Thiago Jung Bauermann wrote: >> This version fixes `make check` failures in ppc/e500.c, mips/cps.c and >> sparc/sun4m.c. This was done by moving the qdev_realize_and_unref() call as >> close as possible to the object_new() call, i

[PATCH v3 00/16] hw/riscv: Add Microchip PolarFire SoC Icicle Kit board support

From: Bin Meng This adds support for Microchip PolarFire SoC Icicle Kit board. The Icicle Kit board integrates a PolarFire SoC, with one SiFive's E51 plus four U54 cores and many on-chip peripherals and an FPGA. For more details about Microchip PolarFire SoC, please see: https://www.microsemi.co

[PATCH v3 01/16] target/riscv: cpu: Add a new 'resetvec' property

From: Bin Meng Currently the reset vector address is hard-coded in a RISC-V CPU's instance_init() routine. In a real world we can have 2 exact same CPUs except for the reset vector address, which is pretty common in the RISC-V core IP licensing business. Normally reset vector address is a config

[PATCH v3 11/16] hw/net: cadence_gem: Add a new 'phy-addr' property

From: Bin Meng At present the PHY address of the PHY connected to GEM is hard-coded to either 23 (BOARD_PHY_ADDRESS) or 0. This might not be the case for all boards. Add a new 'phy-addr' property so that board can specify the PHY address for each GEM instance. Signed-off-by: Bin Meng --- (no

[PATCH v3 04/16] hw/riscv: Initial support for Microchip PolarFire SoC Icicle Kit board

From: Bin Meng This is an initial support for Microchip PolarFire SoC Icicle Kit. The Icicle Kit board integrates a PolarFire SoC, with one SiFive's E51 plus four U54 cores and many on-chip peripherals and an FPGA. For more details about Microchip PolarFire Soc, please see: https://www.microsemi

[PATCH v3 02/16] hw/riscv: hart: Add a new 'resetvec' property

From: Bin Meng RISC-V machines do not instantiate RISC-V CPUs directly, instead they do that via the hart array. Add a new property for the reset vector address to allow the value to be passed to the CPU, before CPU is realized. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis --- (no ch

[PATCH v3 05/16] hw/char: Add Microchip PolarFire SoC MMUART emulation

From: Bin Meng Microchip PolarFire SoC MMUART is ns16550 compatible, with some additional registers. Create a simple MMUART model built on top of the existing ns16550 model. Signed-off-by: Bin Meng --- (no changes since v2) Changes in v2: - change to update hw/char/meson.build - add impl.min

[PATCH v3 13/16] hw/riscv: microchip_pfsoc: Connect 2 Cadence GEMs

From: Bin Meng Microchip PolarFire SoC integrates 2 Candence GEMs to provide IEEE 802.3 standard-compliant 10/100/1000 Mbps ethernet interface. On the Icicle Kit board, GEM0 connects to a PHY at address 8 while GEM1 connects to a PHY at address 9. The 2nd stage bootloader (U-Boot) is using GEM1

[PATCH v3 03/16] target/riscv: cpu: Set reset vector based on the configured property value

From: Bin Meng Now that we have the newly introduced 'resetvec' property in the RISC-V CPU and HART, instead of hard-coding the reset vector addr in the CPU's instance_init(), move that to riscv_cpu_realize() based on the configured property value from the RISC-V machines. Signed-off-by: Bin Men

[PATCH v3 06/16] hw/riscv: microchip_pfsoc: Connect 5 MMUARTs

From: Bin Meng Microchip PolarFire SoC has 5 MMUARTs, and the Icicle Kit board wires 4 of them out. Let's connect all 5 MMUARTs. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis --- (no changes since v1) include/hw/riscv/microchip_pfsoc.h | 20 hw/riscv/microchip_p

[PATCH v3 14/16] hw/riscv: microchip_pfsoc: Hook GPIO controllers

From: Bin Meng Microchip PolarFire SoC integrates 3 GPIOs controllers. It seems enough to create unimplemented devices to cover their register spaces at this point. With this commit, QEMU can boot to U-Boot (2nd stage bootloader) all the way to the Linux shell login prompt, with a modified HSS (

[PATCH v3 07/16] hw/sd: Add Cadence SDHCI emulation

From: Bin Meng Cadence SD/SDIO/eMMC Host Controller (SD4HC) is an SDHCI compatible controller. The SDHCI compatible registers start from offset 0x200, which are called Slot Register Set (SRS) in its datasheet. This creates a Cadence SDHCI model built on top of the existing generic SDHCI model. C

[PATCH v3 16/16] hw/riscv: sifive_u: Connect a DMA controller

From: Bin Meng SiFive FU540 SoC integrates a platform DMA controller with 4 DMA channels. This connects the exsiting SiFive PDMA model to the SoC, and adds its device tree data as well. Signed-off-by: Bin Meng --- (no changes since v1) include/hw/riscv/sifive_u.h | 11 +++ hw/riscv/s

[PATCH v3 08/16] hw/riscv: microchip_pfsoc: Connect a Cadence SDHCI controller and an SD card

From: Bin Meng Microchip PolarFire SoC integrates one Cadence SDHCI controller. On the Icicle Kit board, one eMMC chip and an external SD card connect to this controller depending on different configuration. As QEMU does not support eMMC yet, we just emulate the SD card configuration. To test th

[PATCH v3 09/16] hw/dma: Add SiFive platform DMA controller emulation

From: Bin Meng Microchip PolarFire SoC integrates a DMA engine that supports: * Independent concurrent DMA transfers using 4 DMA channels * Generation of interrupts on various conditions during execution which is actually an IP reused from the SiFive FU540 chip. This creates a model to support b

[PATCH v3 10/16] hw/riscv: microchip_pfsoc: Connect a DMA controller

From: Bin Meng On the Icicle Kit board, the HSS firmware utilizes the on-chip DMA controller to move the 2nd stage bootloader in the system memory. Let's connect a DMA controller to Microchip PolarFire SoC. Signed-off-by: Bin Meng --- (no changes since v2) Changes in v2: - connect 8 IRQs to

[PATCH v3 12/16] hw/arm: xlnx: Set all boards' GEM 'phy-addr' property value to 23

From: Bin Meng When cadence_gem model was created for Xilinx boards, the PHY address was hard-coded to 23 in the GEM model. Now that we have introduced a property we can use that to tell GEM model what our PHY address is. Change all boards' GEM 'phy-addr' property value to 23, and set the PHY add

[PATCH v3 15/16] hw/riscv: clint: Avoid using hard-coded timebase frequency

From: Bin Meng At present the CLINT timestamp is using a hard-coded timebase frequency value SIFIVE_CLINT_TIMEBASE_FREQ. This might not be true for all boards. Add a new 'timebase-freq' property to the CLINT device, and update various functions to accept this as a parameter. Signed-off-by: Bin

Re: [PATCH 0/7] target/arm: Add vSPE support to KVM guest

On Mon, 31 Aug 2020 at 15:56, Auger Eric wrote: > > Hi Haibo, > > On 8/7/20 10:10 AM, Haibo Xu wrote: > > This series add support for SPE(Statistical Profiling Extension)[1] > > in KVM guest. It's based on Andrew Murray's kernel KVM patches V2[2], > > and has been tested to ensure that guest can u

Re: [PATCH 0/1] tcg: Adjust simd_desc size encoding

On Tue, Sep 1, 2020 at 6:29 AM Richard Henderson < richard.hender...@linaro.org> wrote: > Frank, this is intended to address the vector size limitation > that you encountered with the risc-v rvv patch set, as per > > https://lists.gnu.org/archive/html/qemu-devel/2020-08/msg07924.html > > although

Re: [RFC PATCH v3 30/34] Hexagon (target/hexagon) TCG for instructions with multiple definitions

On 8/31/20 4:10 PM, Taylor Simpson wrote: > > >> -Original Message- >> From: Richard Henderson >> Sent: Monday, August 31, 2020 1:20 PM >> To: Taylor Simpson ; qemu-devel@nongnu.org >> Cc: phi...@redhat.com; laur...@vivier.eu; riku.voi...@iki.fi; >> aleksandar.m.m...@gmail.com; a...@rev.

Re: [RFC v3 1/1] memory: Skip bad range assertion if notifier supports arbitrary masks

On 2020/8/21 下午10:12, Peter Xu wrote: On Thu, Aug 20, 2020 at 10:28:00AM +0800, Jason Wang wrote: On 2020/8/19 下午11:50, Peter Xu wrote: On Wed, Aug 19, 2020 at 03:15:26PM +0800, Jason Wang wrote: Yes, actually, I feel confused after reading the codes. Is notifier->start IOVA or GPA? In vfio

Re: [PATCH v2 0/2] util/hexdump: Cleanup qemu_hexdump()

On 2020/8/23 上午2:09, Philippe Mathieu-Daudé wrote: - Pass const void* buffer - Reorder arguments Supersedes: <20200822150457.1322519-1-f4...@amsat.org> Philippe Mathieu-Daudé (2): util/hexdump: Convert to take a void pointer argument util/hexdump: Reorder qemu_hexdump() arguments inc

Re: [PATCH v2 2/7] vhost: check queue state in the vhost_dev_set_log routine

On Mon, Aug 31, 2020 at 4:37 AM Dima Stepanov wrote: > > On Thu, Aug 27, 2020 at 09:46:03PM -0400, Raphael Norwitz wrote: > > On Mon, Aug 24, 2020 at 4:41 AM Dima Stepanov > > wrote: > > > > > > If the vhost-user-blk daemon provides only one virtqueue, but device was > > > added with several que

Re: [PATCH v3 1/7] vhost: recheck dev state in the vhost_migration_log routine

On Mon, Aug 31, 2020 at 5:28 AM Dima Stepanov wrote: > > vhost-user devices can get a disconnect in the middle of the VHOST-USER > handshake on the migration start. If disconnect event happened right > before sending next VHOST-USER command, then the vhost_dev_set_log() > call in the vhost_migrati

Contributing to x86 device emulationi

Hello everyone, I am a software engineer working as an SDE in the industry and I have been wanting to contribute to QEMU. I mailed earlier introducing myself to the mailing list and I was told to talk to specific people who work with the subsystem I want to contribute to. I am interested in contr

RE: [RFC PATCH v3 30/34] Hexagon (target/hexagon) TCG for instructions with multiple definitions

> -Original Message- > From: Richard Henderson > Sent: Monday, August 31, 2020 8:41 PM > To: Taylor Simpson ; qemu-devel@nongnu.org > Cc: phi...@redhat.com; laur...@vivier.eu; riku.voi...@iki.fi; > aleksandar.m.m...@gmail.com; a...@rev.ng > Subject: Re: [RFC PATCH v3 30/34] Hexagon (targ

Re: [PATCH] xhci: check return value from usb_packet_map

+-- On Sun, 30 Aug 2020, Alexander Bulekov wrote --+ | I think there is already a fix queued for this one: | https://www.mail-archive.com/qemu-devel@nongnu.org/msg734424.html Yes, it looks similar. | > @@ -1615,7 +1615,14 @@ static int xhci_setup_packet(XHCITransfer *xfer) | > xhci_xfer_cr

Re: [PATCH] cirrus: handle wraparound in cirrus_invalidate_region

Gerd Hoffmann 于2020年8月31日周一 下午7:23写道： > > > > for (y = 0; y < lines; y++) { > > > -off_cur = off_begin; > > > +off_cur = off_begin & s->cirrus_addr_mask; > > > off_cur_end = ((off_cur + bytesperline - 1) & > > > s->cirrus_addr_mask) + 1; > > > -assert(off_cur

Re: [PATCH] usb: fix setup_len init (CVE-2020-14364)

Hello Li, +-- On Tue, 25 Aug 2020, Li Qiang wrote --+ | Just see the page. | -->https://access.redhat.com/security/cve/CVE-2020-14364 | | The 'Attack Vector' of the CVSS score here is 'local'. | | I think this should be 'network' as the guest user can touch this in cloud | environment? What's

Re: [PATCH] meson: use pkg-config method to find dependencies

On Mon, Aug 31, 2020 at 02:15:23PM +0200, Paolo Bonzini wrote: > On 31/08/20 13:06, Gerd Hoffmann wrote: > > > >> Keep "auto" for SDL so that it tries using > >> sdl-config too. > >> - sdl = dependency('sdl2', > >> - required: get_option('sdl'), > >> + sdl = dependency('sdl2',

Re: [PATCH] cirrus: handle wraparound in cirrus_invalidate_region

Hi, > > > > off_cur_end = ((off_cur + bytesperline - 1) & > > > > s->cirrus_addr_mask) + 1; [ ... ] > > > > +memory_region_set_dirty(&s->vga.vram, 0, off_cur_end); > > > > > > And here be 'off_cur_end -1' > > > > --verbose please. I think this one is correct. > > Here the

Re: [PATCH] xhci: check return value from usb_packet_map

On Tue, Sep 01, 2020 at 10:19:26AM +0530, P J P wrote: > +-- On Sun, 30 Aug 2020, Alexander Bulekov wrote --+ > | I think there is already a fix queued for this one: > | https://www.mail-archive.com/qemu-devel@nongnu.org/msg734424.html > > Yes, it looks similar. > > | > @@ -1615,7 +1615,14 @@ s

[PATCH] usb: call usb_packet_cleanup on usb_packet_map failure

Signed-off-by: Gerd Hoffmann --- hw/usb/hcd-ehci.c | 2 ++ hw/usb/hcd-xhci.c | 1 + 2 files changed, 3 insertions(+) diff --git a/hw/usb/hcd-ehci.c b/hw/usb/hcd-ehci.c index 2b995443fbfd..67847a9cf5f1 100644 --- a/hw/usb/hcd-ehci.c +++ b/hw/usb/hcd-ehci.c @@ -1373,6 +1373,7 @@ static int ehci_ex

Re: [PATCH] docs/system: Fix grammar in documentation

On 31/08/20 22:01, Philippe Mathieu-Daudé wrote: > > > Le jeu. 27 août 2020 19:31, Stefan Weil > a écrit : > > Signed-off-by: Stefan Weil mailto:s...@weilnetz.de>> > > > Reviewed-by: Philippe Mathieu-Daudé > > > --- >  docs/system

[PATCH] riscv: sifive_test: Allow 16-bit writes to memory region

When shutting down the machine running a mainline Linux kernel, the following error happens: $ build/riscv64-softmmu/qemu-system-riscv64 -bios default -M virt \ -display none -initrd rootfs.cpio -kernel Image -m 512m \ -nodefaults -serial mon:stdio ... Requesting system poweroff [4.999

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