[PULL 29/76] target/microblaze: Convert to translator_loop

Finish the conversion to the generic translator_loop. Tested-by: Edgar E. Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/translate.c | 289 ++ 1 file changed, 149 insertions(+), 140 deletions(-) diff --git a/targe

[PULL 43/76] target/microblaze: Unwind properly when raising divide-by-zero

Restore the correct pc when raising divide-by-zero. Also, the MSR[DZO] bit is sticky -- it is not cleared with a successful divide. Tested-by: Edgar E. Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/helper.h| 4 ++-- target/microblaze/op_he

[PULL 31/76] target/microblaze: Remove DISAS_GNU

This is never used. Tested-by: Edgar E. Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/translate.c | 1 - 1 file changed, 1 deletion(-) diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index a90e56a17f..6757720776 10064

[PULL 32/76] target/microblaze: Remove empty D macros

This is never used in op_helper.c and translate.c. There are two trivial uses in helper.c which can be improved by always logging MMU_EXCP to CPU_LOG_INT. Tested-by: Edgar E. Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/helper.c| 11 --

[PULL 39/76] target/microblaze: Convert dec_pattern to decodetree

Tested-by: Edgar E. Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/insns.decode | 4 ++ target/microblaze/translate.c | 67 +- 2 files changed, 22 insertions(+), 49 deletions(-) diff --git a/target/microblaze/ins

[PULL 50/76] target/microblaze: Replace MSR_EE_FLAG with MSR_EE

There's no reason to define MSR_EE_FLAG; we can just use the original MSR_EE define. Document the other flags copied into tb_flags with iflag to reserve those bits. Tested-by: Edgar E. Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/cpu.h |

[PULL 41/76] target/microblaze: Convert dec_mul to decodetree

Tested-by: Edgar E. Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/insns.decode | 6 +++ target/microblaze/translate.c | 77 ++ 2 files changed, 37 insertions(+), 46 deletions(-) diff --git a/target/microblaze/in

[PULL 35/76] target/microblaze: Add decodetree infrastructure

The new interface is a stub that recognizes no instructions. It falls back to the old decoder for all instructions. Tested-by: Edgar E. Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/insns.decode | 18 ++ target/microblaze/transla

[PULL 34/76] target/microblaze: Ensure imm constant is always available

Include the env->imm value in the TB values when IMM_FLAG is set. This means that we can always reconstruct the complete 32-bit imm. Discard env_imm when its contents can no longer be accessed. Fix user-mode checks for BRK/BRKI, which depend on IMM. Tested-by: Edgar E. Iglesias Reviewed-by: Edga

[PULL 56/76] target/microblaze: Fix no-op mb_cpu_transaction_failed

Do not call cpu_restore_state when no exception will be delivered. This can lead to inconsistent cpu state. Tested-by: Edgar E. Iglesias Reviewed-by: Edgar E. Iglesias Reported-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/op_helper.c | 25 +

[PULL 40/76] target/microblaze: Convert dec_and, dec_or, dec_xor to decodetree

Tested-by: Edgar E. Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/insns.decode | 12 + target/microblaze/translate.c | 46 -- 2 files changed, 28 insertions(+), 30 deletions(-) diff --git a/target/microbl

[PULL 65/76] target/microblaze: Reorganize branching

Remove the btaken variable, and simplify things by always computing the full branch destination into btarget. This avoids all need for sync_jmpstate(). Retain the direct branch behaviour by remembering the jump destination in jmp_dest, discarding btarget. In the normal case, where the branch del

[PULL 42/76] target/microblaze: Convert dec_div to decodetree

Tested-by: Edgar E. Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/insns.decode | 3 +++ target/microblaze/translate.c | 35 +- 2 files changed, 16 insertions(+), 22 deletions(-) diff --git a/target/microblaze/in

[PULL 38/76] target/microblaze: Implement cmp and cmpu inline

These are simple enough operations; we do not need to call an out-of-line helper. Tested-by: Edgar E. Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/helper.h| 2 -- target/microblaze/op_helper.c | 20 target/microblaze/t

[PULL 46/76] target/microblaze: Convert dec_imm to decodetree

Tested-by: Edgar E. Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/insns.decode | 2 ++ target/microblaze/translate.c | 18 +- 2 files changed, 11 insertions(+), 9 deletions(-) diff --git a/target/microblaze/insns.decode b/targe

[PULL 45/76] target/microblaze: Convert dec_barrel to decodetree

Tested-by: Edgar E. Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/insns.decode | 20 ++ target/microblaze/translate.c | 125 + 2 files changed, 86 insertions(+), 59 deletions(-) diff --git a/target/microblaz

[PULL 44/76] target/microblaze: Convert dec_bit to decodetree

Tested-by: Edgar E. Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/insns.decode | 20 + target/microblaze/translate.c | 148 + 2 files changed, 95 insertions(+), 73 deletions(-) diff --git a/target/microblaze

[PULL 52/76] target/microblaze: Fix cpu unwind for stackprot

Restore the correct PC when an exception must be raised. Tested-by: Edgar E. Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/helper.h| 2 +- target/microblaze/op_helper.c | 6 +- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git

[PULL 47/76] target/microblaze: Convert dec_fpu to decodetree

The current dec_check_fpuv2 test, raising an FPU exception for an unimplemented instruction, appears to be contradictory to the manual. Drop that and merely check use_fpu == 2. Tested-by: Edgar E. Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/i

[PULL 69/76] target/microblaze: Tidy do_rti, do_rtb, do_rte

Since cpu_msr is no longer a 64-bit quantity, we can simplify the arithmetic in these functions. Tested-by: Edgar E. Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/translate.c | 65 ++- 1 file changed, 25 insertion

[PULL 49/76] target/microblaze: Mark fpu helpers TCG_CALL_NO_WG

Now that FSR is no longer a tcg global temp, we can say that the fpu helpers do not write to tcg temps. All temps are read implicitly by the fpu exception path. Tested-by: Edgar E. Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/helper.h | 28 +++

[PULL 54/76] target/microblaze: Assert no overlap in flags making up tb_flags

Create MSR_TB_MASK. Use it in cpu_get_tb_cpu_state, and check that IFLAGS_TB_MASK does not overlap. Tested-by: Edgar E. Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 9 +++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --g

[PULL 63/76] target/microblaze: Convert brk and brki to decodetree

Split these out of the normal branch instructions, as they require special handling. Perform the entire operation inline, instead of raising EXCP_BREAK to do the work in mb_cpu_do_interrupt. This fixes a bug in that brki rd, imm, for imm != 0x18 is not supposed to set MSR_BIP. This fixes a bug i

[PULL 48/76] target/microblaze: Fix cpu unwind for fpu exceptions

Restore the correct PC when an exception must be raised. Tested-by: Edgar E. Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/op_helper.c | 37 +++ 1 file changed, 20 insertions(+), 17 deletions(-) diff --git a/targ

[PULL 55/76] target/microblaze: Move bimm to BIMM_FLAG

It makes sense to keep BIMM with D_FLAG, as they can be written back to iflags at the same time. BIMM_FLAG does not need to be added to IFLAGS_TB_MASK because it does not affect the next TB, only the exception path out of the current TB. Renumber IMM_FLAG, as the value 4 holds no particular signi

Re: [PATCH] memory: Revert "memory: accept mismatching sizes in memory_region_access_valid"

On Sun, Aug 30, 2020 at 12:43 AM Nathan Chancellor wrote: > > On Sun, Aug 30, 2020 at 08:24:15AM +0100, Mark Cave-Ayland wrote: > > On 30/08/2020 07:49, Nathan Chancellor wrote: > > > > > Unfortunately, it does not. I applied it on top of latest > > > git (ac8b279f13865d1a4f1958d3bf34240c1c3af90d)

[PULL 51/76] target/microblaze: Cache mem_index in DisasContext

Ideally, nothing outside the top-level of translation even has access to env. Cache the value in init_disas_context. Tested-by: Edgar E. Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/translate.c | 9 + 1 file changed, 5 insertions(+), 4

[PULL 64/76] target/microblaze: Convert mbar to decodetree

Split this out of the normal branch instructions, as it requires special handling. Tested-by: Edgar E. Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/insns.decode | 2 + target/microblaze/translate.c | 85 +++--- 2 f

[PULL 53/76] target/microblaze: Convert dec_load and dec_store to decodetree

Tested-by: Edgar E. Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/insns.decode | 32 ++ target/microblaze/translate.c | 723 +++-- 2 files changed, 456 insertions(+), 299 deletions(-) diff --git a/target/microblaze/

[PULL 57/76] target/microblaze: Store "current" iflags in insn_start

This data is available during exception unwinding, thus we can restore it from there directly, rather than saving it during the TB. Thus we may remove the t_sync_flags() calls in the load/store operations. Note that these calls were missing from the other places where runtime exceptions may be ra

[PULL 67/76] target/microblaze: Convert dec_bcc to decodetree

Tested-by: Edgar E. Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/insns.decode | 36 + target/microblaze/translate.c | 99 ++ 2 files changed, 88 insertions(+), 47 deletions(-) diff --git a/target/mic

[PULL 70/76] target/microblaze: Convert msrclr, msrset to decodetree

Split this out of dec_msr. Tested-by: Edgar E. Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/insns.decode | 6 +++ target/microblaze/translate.c | 85 +++--- 2 files changed, 54 insertions(+), 37 deletions(-) diff

[PULL 68/76] target/microblaze: Convert dec_rts to decodetree

Tested-by: Edgar E. Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/insns.decode | 5 target/microblaze/translate.c | 51 +++--- 2 files changed, 28 insertions(+), 28 deletions(-) diff --git a/target/microblaze/i

[PULL 58/76] tcg: Add tcg_get_insn_start_param

MicroBlaze will shortly need to update a parameter in place. Add an interface to read to match that for write. Tested-by: Edgar E. Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- include/tcg/tcg.h | 15 +++ 1 file changed, 15 insertions(+) diff --git a

[PULL 59/76] target/microblaze: Use cc->do_unaligned_access

This fixes the problem in which unaligned stores succeeded, but then we raised the exception after modifying memory. Store the ESS for the unaligned data access in the iflags for the insn, so that it can be found during unwind. Tested-by: Edgar E. Iglesias Reviewed-by: Edgar E. Iglesias Signed-o

[PULL 74/76] target/microblaze: Remove cpu_R[0]

Do not initialize cpu_R[0], as this should be totally unused. The cpu_for_read and cpu_for_write functions use a local temp. Tested-by: Edgar E. Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/translate.c | 8 +++- 1 file changed, 7 insertions

[PULL 72/76] target/microblaze: Convert dec_stream to decodetree

Tested-by: Edgar E. Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/insns.decode | 6 target/microblaze/translate.c | 64 ++ 2 files changed, 55 insertions(+), 15 deletions(-) diff --git a/target/microblaze/i

[PULL 60/76] target/microblaze: Replace clear_imm with tb_flags_to_set

This more general update variable will be able to handle delay slots as well. Tested-by: Edgar E. Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/translate.c | 15 +-- 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/targe

[PULL 76/76] target/microblaze: Reduce linux-user address space to 32-bit

User-space programs cannot use the 64-bit lwea/swea instructions. We can improve code generation and runtime by restricting the user-only address space to 32-bit. Tested-by: Edgar E. Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/cpu-param.h | 15

[PULL 61/76] target/microblaze: Replace delayed_branch with tb_flags_to_set

The multi-stage counter can be replaced by clearing D_FLAG, the or'ing in tb_flags_to_set. The jump then happens when D_FLAG is finally cleared. Tested-by: Edgar E. Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/translate.c | 17 +---

[PULL 73/76] target/microblaze: Remove last of old decoder

All instructions have been convered. Issue sigill if decodetree does not match. Remove argument decode from DisasContext. Remove microblaze-decode.h. Tested-by: Edgar E. Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/microblaze-decode.h | 59 --

Re: [PATCH] memory: Revert "memory: accept mismatching sizes in memory_region_access_valid"

On Sun, Aug 30, 2020 at 12:24 AM Mark Cave-Ayland wrote: > > On 30/08/2020 07:49, Nathan Chancellor wrote: > > > Unfortunately, it does not. I applied it on top of latest > > git (ac8b279f13865d1a4f1958d3bf34240c1c3af90d) and I can still > > reproduce my failure. Is it possible that type of fix is

[PULL 62/76] target/microblaze: Tidy mb_cpu_dump_state

Using lookup_symbol is quite slow; remove that. Decode the various bits of iflags; only show imm, btaken, btarget when they are relevant to iflags. Improve formatting. Tested-by: Edgar E. Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/translate

[PULL 66/76] target/microblaze: Convert dec_br to decodetree

Tested-by: Edgar E. Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/insns.decode | 14 ++ target/microblaze/translate.c | 87 +++--- 2 files changed, 63 insertions(+), 38 deletions(-) diff --git a/target/microblaze

[PULL 71/76] target/microblaze: Convert dec_msr to decodetree

Tested-by: Edgar E. Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/insns.decode | 3 + target/microblaze/translate.c | 270 + 2 files changed, 139 insertions(+), 134 deletions(-) diff --git a/target/microblaze/i

Re: [PATCH] gitlab-ci.yml: Run check-qtest and check-unit at the end of the fuzzer job

On 200831 1732, Thomas Huth wrote: > The fuzzer job finishes quite early, so we can run the unit tests and > qtests with -fsanitize=address here without extending the total test time. > Sounds good to me, though its too bad that this is limited to i386 and we aren't using the --enable-sanitizers

[PULL 75/76] target/microblaze: Add flags markup to some helpers

The mmu_read, mmu_write, get, and put helpers do not touch the general registers, or any of the other variables managed by tcg. Tested-by: Edgar E. Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/helper.h | 8 1 file changed, 4 insertions

RE: [RFC PATCH v3 30/34] Hexagon (target/hexagon) TCG for instructions with multiple definitions

> >> -Original Message- > >> From: Richard Henderson > >> Sent: Sunday, August 30, 2020 3:13 PM > >> To: Taylor Simpson ; qemu-devel@nongnu.org > >> Cc: phi...@redhat.com; laur...@vivier.eu; riku.voi...@iki.fi; > >> aleksandar.m.m...@gmail.com; a...@rev.ng > >> Subject: Re: [RFC PATCH v3

Re: [PATCH v3 00/74] qom: Automated conversion of type checking boilerplate

On Tue, Aug 25, 2020 at 03:19:56PM -0400, Eduardo Habkost wrote: > git tree for this series: > https://github.com/ehabkost/qemu-hacks/tree/work/qom-macros-autoconvert > > This is an extension of the series previously submitted by > Daniel[1], including a script that will convert existing type > ch

Re: [RFC PATCH v3 30/34] Hexagon (target/hexagon) TCG for instructions with multiple definitions

On 8/31/20 10:08 AM, Taylor Simpson wrote: > There are some assumptions here I'd like to clarify. When I started this > discussion, there seemed to be general resistance to the concept of a > generator. Because of this, I made the generator as simple as possible and > pushed the complexity and op

[Bug 1893667] Re: Btrfs commands don't work when using user-space emulation of other architectures

** Changed in: qemu Status: New => In Progress ** Tags added: linux-user -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1893667 Title: Btrfs commands don't work when using user-space emulati

Re: [PATCH] hw/register: Document register_init_block @memory_size

Le 07/07/2020 à 08:23, Philippe Mathieu-Daudé a écrit : > Document the 'memory_size' argument of register_init_block(). > > Fixes: a74229597e ("register: Add block initialise helper") > Signed-off-by: Philippe Mathieu-Daudé > --- > include/hw/register.h | 1 + > 1 file changed, 1 insertion(+) >

RE: [RFC PATCH v3 00/34] Hexagon patch series

> -Original Message- > From: Richard Henderson > Sent: Sunday, August 30, 2020 5:33 PM > To: Taylor Simpson ; qemu-devel@nongnu.org > Cc: phi...@redhat.com; laur...@vivier.eu; riku.voi...@iki.fi; > aleksandar.m.m...@gmail.com; a...@rev.ng > Subject: Re: [RFC PATCH v3 00/34] Hexagon patch

RE: [RFC PATCH v3 30/34] Hexagon (target/hexagon) TCG for instructions with multiple definitions

> -Original Message- > From: Richard Henderson > Sent: Monday, August 31, 2020 11:29 AM > To: Taylor Simpson ; qemu-devel@nongnu.org > Cc: phi...@redhat.com; laur...@vivier.eu; riku.voi...@iki.fi; > aleksandar.m.m...@gmail.com; a...@rev.ng > Subject: Re: [RFC PATCH v3 30/34] Hexagon (tar

[PATCH v6 00/10] Remove EPYC mode apicid decode and use generic decode

To support some of the complex topology, we introduced EPYC mode apicid decode. But, EPYC mode decode is running into problems. Also it can become quite a maintenance problem in the future. So, it was decided to remove that code and use the generic decode which works for majority of the topology. M

Re: [PATCH v3 0/5] pc-bios: s390x: Cleanup part 2

Patchew URL: https://patchew.org/QEMU/20200831150910.317171-1-fran...@linux.ibm.com/ Hi, This series seems to have some coding style problems. See output below for more information: Type: series Message-id: 20200831150910.317171-1-fran...@linux.ibm.com Subject: [PATCH v3 0/5] pc-bios: s390x:

Re: [PULL 0/7] softfloat patch queue

On Sun, 30 Aug 2020 at 03:32, Richard Henderson wrote: > > The following changes since commit ea1bb830cb021cca2e361091cf728aaabc8c0654: > > Merge remote-tracking branch > 'remotes/pmaydell/tags/pull-target-arm-20200828' into staging (2020-08-28 > 15:14:40 +0100) > > are available in the Git re

[PATCH 0/6] target/microblaze: Use tcg_gen_lookup_and_goto_ptr

Based-on: <20200831160601.833692-1-richard.hender...@linaro.org> ("[PULL 00/76] target/microblaze improvements") Hello again, Edgar. I had dropped the tcg_gen_lookup_and_goto_ptr patch from the previous omnibus patch set, as you had reported lockups. I have identified, by inspection, two cases i

[PATCH 5/6] target/microblaze: Force rtid, rted, rtbd to exit

These return-from-exception type instructions have modified MSR to re-enable various forms of interrupt. Force a return to the main loop. Consolidate the cleanup of tb_flags into mb_tr_translate_insn. Signed-off-by: Richard Henderson --- target/microblaze/translate.c | 27 -

[PATCH 1/6] target/microblaze: Rename DISAS_UPDATE to DISAS_EXIT

The name "update" suggests that something needs updating, but this is not the case. Use "exit" to emphasize that nothing needs doing except to exit. Signed-off-by: Richard Henderson --- target/microblaze/translate.c | 10 +- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/

[PATCH 3/6] target/microblaze: Replace cpustate_changed with DISAS_EXIT_NEXT

Rather than look for the combination of DISAS_NEXT with a separate variable, go ahead and set is_jmp to the desired state. Signed-off-by: Richard Henderson --- target/microblaze/translate.c | 34 ++ 1 file changed, 10 insertions(+), 24 deletions(-) diff --git a/t

[PATCH v6 01/10] Revert "i386: Fix pkg_id offset for EPYC cpu models"

This reverts commit 7b225762c8c05fd31d4c2be116aedfbc00383f8b. Remove the EPYC specific apicid decoding and use the generic default decoding. Also fix all the references of pkg_offset. Signed-off-by: Babu Moger --- hw/i386/pc.c |1 - target/i386/cpu.c |9 - target/i386/cpu.

[PATCH 2/6] target/microblaze: Introduce DISAS_EXIT_NEXT, DISAS_EXIT_JUMP

Like DISAS_EXIT, except we need to update cpu_pc, either to pc_next or to btarget respectively. Signed-off-by: Richard Henderson --- target/microblaze/translate.c | 29 + 1 file changed, 21 insertions(+), 8 deletions(-) diff --git a/target/microblaze/translate.c b/ta

[PATCH 4/6] target/microblaze: Handle DISAS_EXIT_NEXT in delay slot

It is legal to put an mts instruction into a delay slot. We should continue to return to the main loop in that case so that we recognize any pending interrupts. Signed-off-by: Richard Henderson --- target/microblaze/translate.c | 34 +- 1 file changed, 33 insertio

[PATCH v6 07/10] Revert "hw/386: Add EPYC mode topology decoding functions"

This reverts commit 7568b20a6405042f62c64af3268f4330aed5. Remove the EPYC specific apicid decoding and use the generic default decoding. Signed-off-by: Babu Moger --- include/hw/i386/topology.h | 100 1 file changed, 100 deletions(-) diff --git

[PATCH v6 00/10] Remove EPYC mode apicid decode and use generic decode

To support some of the complex topology, we introduced EPYC mode apicid decode. But, EPYC mode decode is running into problems. Also it can become quite a maintenance problem in the future. So, it was decided to remove that code and use the generic decode which works for majority of the topology. M

[PATCH 6/6] target/microblaze: Use tcg_gen_lookup_and_goto_ptr

Normal indirect jumps, or page-crossing direct jumps, can use tcg_gen_lookup_and_goto_ptr to avoid returning to the main loop simply to find an existing TB for the next pc. Signed-off-by: Richard Henderson --- target/microblaze/translate.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-

[PATCH v6 04/10] Revert "i386: Introduce use_epyc_apic_id_encoding in X86CPUDefinition"

This reverts commit 0c1538cb1a26287c072645f4759b9872b1596d79. Remove the EPYC specific apicid decoding and use the generic default decoding. Signed-off-by: Babu Moger --- target/i386/cpu.c | 16 target/i386/cpu.h |1 - 2 files changed, 17 deletions(-) diff --git a/target

[PATCH v6 08/10] Revert "hw/i386: Update structures to save the number of nodes per package"

This reverts commit c24a41bb53c0854d22c96b30d57cfcaa543c409d. Remove the EPYC specific apicid decoding and use the generic default decoding. Signed-off-by: Babu Moger --- hw/i386/pc.c |1 - hw/i386/x86.c |1 - include/hw/i386/topology.h |1 - target/i386/c

[PATCH v6 02/10] Revert "target/i386: Enable new apic id encoding for EPYC based cpus models"

This reverts commit 247b18c593ec298446645af8d5d28911daf653b1. Remove the EPYC specific apicid decoding and use the generic default decoding. Signed-off-by: Babu Moger --- target/i386/cpu.c |2 -- 1 file changed, 2 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 173e6f

[PATCH v6 06/10] Revert "target/i386: Cleanup and use the EPYC mode topology functions"

This reverts commit dd08ef0318e2b61d14bc069590d174913f7f437a. Remove the EPYC specific apicid decoding and use the generic default decoding. Signed-off-by: Babu Moger --- target/i386/cpu.c | 161 ++--- 1 file changed, 127 insertions(+), 34 deleti

[PATCH v6 05/10] Revert "hw/i386: Introduce apicid functions inside X86MachineState"

This reverts commit 6121c7fbfd98dbc3af1b00b56ff2eef66df87828. Remove the EPYC specific apicid decoding and use the generic default decoding. Signed-off-by: Babu Moger --- hw/i386/x86.c |5 - include/hw/i386/x86.h |9 - 2 files changed, 14 deletions(-) diff --git a/h

Re: [PATCH v3 51/74] arm: Fix typo in AARCH64_CPU_GET_CLASS definition

On Tue, 25 Aug 2020 at 20:23, Eduardo Habkost wrote: > > There's a typo in the type name of AARCH64_CPU_GET_CLASS. This > was never detected because the macro is not used by any code. > > Signed-off-by: Eduardo Habkost > --- > Changes series v2 -> v3: new patch added to series v3 Reviewed-by: P

[PATCH v6 03/10] Revert "hw/i386: Move arch_id decode inside x86_cpus_init"

This reverts commit 2e26f4ab3bf8390a2677d3afd9b1a04f015d7721. Remove the EPYC specific apicid decoding and use the generic default decoding. Signed-off-by: Babu Moger --- hw/i386/pc.c |6 +++--- hw/i386/x86.c | 37 +++-- 2 files changed, 10 insertions(+),

[PATCH v6 10/10] i386: Simplify CPUID_8000_001E for AMD

apic_id contains all the information required to build CPUID_8000_001E. core_id and node_id is already part of apic_id generated by x86_topo_ids_from_apicid. Also remove the restriction on number bits on core_id and node_id. Remove all the hardcoded values and replace with generalized fields. Re

[PATCH v6 09/10] i386: Simplify CPUID_8000_001E for AMD

Remove all the hardcoded values and replace with generalized fields. Signed-off-by: Babu Moger --- target/i386/cpu.c | 31 +-- 1 file changed, 17 insertions(+), 14 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index ba4667b33c..d434c8545a 100644 -

Re: [RFC v4 55/70] target/riscv: rvv-1.0: single-width floating-point reduction

On Sun, Aug 30, 2020 at 7:58 AM Richard Henderson < richard.hender...@linaro.org> wrote: > On 8/29/20 4:50 PM, Richard Henderson wrote: > > It doesn't actually say anything about the way in which we've > implemented the > > *_noprop functions. > > Ho hum. It seems v2.2 has changed fmin/fmax for t

Re: [PATCH v3 53/74] rx: Move typedef RXCPU to cpu-qom.h

On Tue, 25 Aug 2020 at 20:46, Eduardo Habkost wrote: > > Move the typedef closer to the QOM type checking macros. > This will make future conversion to OBJECT_DECLARE* easier. > > Signed-off-by: Eduardo Habkost > --- > Changes series v2 -> v3: new patch added to series v3 > > --- > Cc: Yoshinori

Re: [PATCH v3 44/74] imx_ccm: Rename IMX_GET_CLASS macro

On Tue, 25 Aug 2020 at 20:22, Eduardo Habkost wrote: > > Rename it to IMX_CCM_GET_CLASS to be consistent with the existing > IMX_CCM and IXM_CCM_CLASS macro. > > This will make future conversion to OBJECT_DECLARE* easier. > > Signed-off-by: Eduardo Habkost > --- > Changes series v2 -> v3: new pat

Re: [PATCH v3 45/74] mos6522: Rename QOM macros

On Tue, 25 Aug 2020 at 20:42, Eduardo Habkost wrote: > > Rename the MOS6522_DEVICE_CLASS and MOS6522_DEVICE_GET_CLASS > macros to be consistent with the TYPE_MOS6522 and MOS6522 macros. > > This will make future conversion to OBJECT_DECLARE* easier. > > Signed-off-by: Eduardo Habkost > --- > Chan

Re: [PATCH v3 00/74] qom: Automated conversion of type checking boilerplate

On Mon, 31 Aug 2020 at 18:23, Eduardo Habkost wrote: > > On Tue, Aug 25, 2020 at 03:19:56PM -0400, Eduardo Habkost wrote: > > git tree for this series: > > https://github.com/ehabkost/qemu-hacks/tree/work/qom-macros-autoconvert > > > > This is an extension of the series previously submitted by > >

Re: [PATCH v3 52/74] rx: Rename QOM type check macros

On Tue, 25 Aug 2020 at 20:46, Eduardo Habkost wrote: > > Currently we have a RXCPU typedef and a RXCPU type checking > macro, but OBJECT_DECLARE* would transform the RXCPU macro into a > function, and the function name would conflict with the typedef > name. > > Rename the RXCPU* QOM type check ma

Re: [PATCH v3 46/74] x86-iommu: Rename QOM type macros

On Tue, Aug 25, 2020 at 03:20:42PM -0400, Eduardo Habkost wrote: > Some QOM macros were using a X86_IOMMU_DEVICE prefix, and others > were using a X86_IOMMU prefix. Rename all of them to use the > same X86_IOMMU_DEVICE prefix. > > This will make future conversion to OBJECT_DECLARE* easier. > > S

Re: [PATCH v3 00/74] qom: Automated conversion of type checking boilerplate

On Mon, Aug 31, 2020 at 07:52:39PM +0100, Peter Maydell wrote: > On Mon, 31 Aug 2020 at 18:23, Eduardo Habkost wrote: > > > > On Tue, Aug 25, 2020 at 03:19:56PM -0400, Eduardo Habkost wrote: > > > git tree for this series: > > > https://github.com/ehabkost/qemu-hacks/tree/work/qom-macros-autoconve

Re: [RFC PATCH v3 30/34] Hexagon (target/hexagon) TCG for instructions with multiple definitions

On 8/31/20 11:14 AM, Taylor Simpson wrote: > Just to be explicit, the code that generates code is generated as > #ifdef fGEN_TCG_A2_add > fGEN_TCG_A2_add({ RdV=RsV+RtV;}); > #else > do { > gen_helper_A2_add(RdV, cpu_env, RsV, RtV); > } while (0); > #endif > If we're goin

[kvm-unit-tests RFC 0/4] KVM: arm64: Statistical Profiling Extension Tests

This series implements tests exercising the Statistical Profiling Extensions. This was tested with associated unmerged kernel [1] and QEMU [2] series. Depending on the comments, I can easily add other tests checking more configs, additional events and testing migration too. I hope this can be use

[kvm-unit-tests RFC 2/4] spe: Probing and Introspection Test

Test whether Statistical Profiling Extensions (SPE) are supported and in the positive collect dimensioning data from the IDR registers. The First test only validates those. Signed-off-by: Eric Auger --- arm/Makefile.common | 1 + arm/spe.c | 163 ++

[kvm-unit-tests RFC 1/4] arm64: Move get_id_aa64dfr0() in processor.h

We plan to use get_id_aa64dfr0() for SPE tests. So let's move this latter in processor.h header. Signed-off-by: Eric Auger --- arm/pmu.c | 1 - lib/arm64/asm/processor.h | 5 + 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/arm/pmu.c b/arm/pmu.c index cece53e..

[kvm-unit-tests RFC 4/4] spe: Test Profiling Buffer Events

Setup the infrastructure to check the occurence of events. The test checks the Buffer Full event occurs when no space is available. The PPI is handled and we check the syndrome register against the expected event. Signed-off-by: Eric Auger --- arm/spe.c | 141

[kvm-unit-tests RFC 3/4] spe: Add profiling buffer test

Add the code to prepare for profiling at EL1. The code under profiling is a simple loop doing memory addresses. We simply check the profiling buffer write position increases, ie. the buffer gets filled. No event is expected. Signed-off-by: Eric Auger --- To make sure no buffer full events is li

[Bug 1893691] [NEW] Chardev logfile is not written (regression between 5.0 and 5.1)

Public bug reported: After update from version 5.0 to 5.1, logfile stopped being populated with console output. The file is being created, but remains empty. Relevant command line options: -mon chardev=char0 -serial chardev:char0 -chardev socket,host=127.0.0.10,port=2323,server,nowait,telnet,mu

QEMU | Pipeline #184026826 has failed for master | 4bc08c61

Your pipeline has failed. Project: QEMU ( https://gitlab.com/qemu-project/qemu ) Branch: master ( https://gitlab.com/qemu-project/qemu/-/commits/master ) Commit: 4bc08c61 ( https://gitlab.com/qemu-project/qemu/-/commit/4bc08c61416cf9244175807b8752caf739f7681f ) Commit Message: Merge remote-tr

Re: [RFC PATCH v3 00/34] Hexagon patch series

On 8/31/20 10:57 AM, Taylor Simpson wrote: > OK, here's the list of items. Let me know if I missed anything. I'll > indicate which ones can be done quickly and which ones would take more time. > I added a column for blocker if you or anyone else has input on that. > > PatchItemEffortBlocker > U

[PATCH v4 01/18] qom: make object_ref/unref use a void * instead of Object *.

From: Daniel P. Berrangé The object_ref/unref methods are intended for use with any subclass of the base Object. Using "Object *" in the signature is not adding any meaningful level of type safety, since callers simply use "OBJECT(ptr)" and this expands to an unchecked cast "(Object *)". By usin

[PATCH v4 03/18] qom: Allow class type name to be specified in OBJECT_DECLARE*

Many QOM types don't follow the Type/TypeClass pattern on the instance/struct names. Let the class struct name be specified in the OBJECT_DECLARE* macros. Reviewed-by: Daniel P. Berrangé Signed-off-by: Eduardo Habkost --- Changes v3 -> v4: none Changes v2 -> v3: none Changes v1 -> v2: none --

[PATCH v4 07/18] [automated] Delete duplicate QOM typedefs

Generated using: $ ./scripts/codeconverter/converter.py -i \ --pattern=QOMDuplicatedTypedefs $(git grep -l '' -- '*.[ch]') Reviewed-by: Daniel P. Berrangé Signed-off-by: Eduardo Habkost --- Changes v3 -> v4: none Changes v2 -> v3: none Changes v1 -> v2: none --- Cc: "Daniel P. Berrangé"

[PATCH v4 00/18] qom: Automated conversion of type checking boilerplate

Latest version of this series can be found at the branch: https://github.com/ehabkost/qemu-hacks/tree/work/qom-macros-autoconvert This is an extension of the series previously submitted by Daniel[1], including a script that will convert existing type checker macros automatically. [1] https://lore

[PATCH v4 02/18] qom: provide convenient macros for declaring and defining types

From: Daniel P. Berrangé When creating new QOM types, there is a lot of boilerplate code that must be repeated using a standard pattern. This is tedious to write and liable to suffer from subtle inconsistencies. Thus it would benefit from some simple automation. QOM was loosely inspired by GLib'

[PATCH v4 05/18] qom: Make type checker functions accept const pointers

The existing type check macros all unconditionally drop const qualifiers from their arguments. Keep this behavior in the macros generated by DECLARE_*CHECKER* by now. Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Daniel P. Berrangé Signed-off-by: Eduardo Habkost --- Changes v3 -> v4: none

[PATCH v4 09/18] [automated] Move QOM typedefs and add missing includes (pass 2)

Some typedefs and macros are defined after the type check macros. This makes it difficult to automatically replace their definitions with OBJECT_DECLARE_TYPE. Patch generated using: $ ./scripts/codeconverter/converter.py -i \ --pattern=QOMStructTypedefSplit $(git grep -l '' -- '*.[ch]') whic

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