[PULL v3 11/20] roms/opensbi: Upgrade from v0.7 to v0.8

2020-08-21 Thread Alistair Francis
From: Bin Meng Upgrade OpenSBI from v0.7 to v0.8. The v0.8 release includes the following commits: 1bb00ab lib: No need to provide default PMP region using platform callbacks a9eac67 include: sbi_platform: Combine reboot and shutdown into one callback 6585fab lib: utils: Add SiFive test device

[PULL v3 03/20] target/riscv: Generate nanboxed results from trans_rvf.inc.c

2020-08-21 Thread Alistair Francis
From: Richard Henderson Make sure that all results from inline single-precision scalar operations are properly nan-boxed to 64-bits. Signed-off-by: Richard Henderson Reviewed-by: LIU Zhiwei Message-Id: <20200724002807.441147-4-richard.hender...@linaro.org> Signed-off-by: Alistair Francis ---

[PULL v3 01/20] target/riscv: Generate nanboxed results from fp helpers

2020-08-21 Thread Alistair Francis
From: Richard Henderson Make sure that all results from single-precision scalar helpers are properly nan-boxed to 64-bits. Signed-off-by: Richard Henderson Reviewed-by: LIU Zhiwei Message-Id: <20200724002807.441147-2-richard.hender...@linaro.org> Signed-off-by: Alistair Francis --- target/ri

[PULL v3 15/20] gitlab-ci/opensbi: Update GitLab CI to build generic platform

2020-08-21 Thread Alistair Francis
From: Bin Meng This updates the GitLab CI opensbi job to build opensbi bios images for the generic platform. Signed-off-by: Bin Meng Reviewed-by: Anup Patel Reviewed-by: Alistair Francis Message-Id: <1596439832-29238-7-git-send-email-bmeng...@gmail.com> Signed-off-by: Alistair Francis --- .

[PULL v3 04/20] target/riscv: Check nanboxed inputs to fp helpers

2020-08-21 Thread Alistair Francis
From: Richard Henderson If a 32-bit input is not properly nanboxed, then the input is replaced with the default qnan. Signed-off-by: Richard Henderson Reviewed-by: LIU Zhiwei Message-Id: <20200724002807.441147-5-richard.hender...@linaro.org> Signed-off-by: Alistair Francis --- target/riscv/i

[PULL v3 08/20] hw/riscv: sifive_u: Add a dummy L2 cache controller device

2020-08-21 Thread Alistair Francis
From: Bin Meng It is enough to simply map the SiFive FU540 L2 cache controller into the MMIO space using create_unimplemented_device(), with an FDT fragment generated, to make the latest upstream U-Boot happy. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Message-Id: <1595227748-24720-

[PULL v3 10/20] configure: Create symbolic links for pc-bios/*.elf files

2020-08-21 Thread Alistair Francis
From: Bin Meng Now we need to ship the OpenSBI fw_dynamic.elf image for the RISC-V Spike machine, it requires us to create symbolic links for pc-bios/*.elf files. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Message-Id: <1596439832-29238-2-git-send-email-bmeng...@gmail.com> Signed-off

[PULL v3 17/20] target/riscv: Change the TLB page size depends on PMP entries.

2020-08-21 Thread Alistair Francis
From: Zong Li The minimum granularity of PMP is 4 bytes, it is small than 4KB page size, therefore, the pmp checking would be ignored if its range doesn't start from the alignment of one page. This patch detects the pmp entries and sets the small page size to TLB if there is a PMP entry which cov

[PULL v3 09/20] riscv: Fix bug in setting pmpcfg CSR for RISCV64

2020-08-21 Thread Alistair Francis
From: Hou Weiying First, sizeof(target_ulong) equals to 4 on riscv32, so this change does not change the function on riscv32. Second, sizeof(target_ulong) equals to 8 on riscv64, and 'reg_index * 8 + i' is not a legal pmp_index (we will explain later), which should be 'reg_index * 4 + i'. If the

[PULL v3 16/20] target/riscv: Fix the translation of physical address

2020-08-21 Thread Alistair Francis
From: Zong Li The real physical address should add the 12 bits page offset. It also causes the PMP wrong checking due to the minimum granularity of PMP is 4 byte, but we always get the physical address which is 4KB alignment, that means, we always use the start address of the page to check PMP fo

[PULL v3 18/20] hw/intc: ibex_plic: Update the pending irqs

2020-08-21 Thread Alistair Francis
After a claim or a priority change we need to update the pending interrupts. This is based on the same patch for the SiFive PLIC: 55765822804f5a58594e "riscv: plic: Add a couple of mising sifive_plic_update calls" Signed-off-by: Alistair Francis Cc: Jessica Clarke Reviewed-by: Philippe Mathieu-D

[PULL v3 19/20] hw/intc: ibex_plic: Don't allow repeat interrupts on claimed lines

2020-08-21 Thread Alistair Francis
Once an interrupt has been claimed, but before it has been compelted we shouldn't receive any more pending interrupts. This patche keeps track of this to ensure that we don't see any more interrupts until it is completed. Signed-off-by: Alistair Francis Message-Id: <394c3f070615ff2b4fab61a1cf9cb

[PULL v3 20/20] hw/intc: ibex_plic: Honour source priorities

2020-08-21 Thread Alistair Francis
This patch follows what commit aa4d30f6618dc "riscv: plic: Honour source priorities" does and ensures that the highest priority interrupt will be serviced first. Signed-off-by: Alistair Francis Cc: Jessica Clarke Reviewed-by: Philippe Mathieu-Daudé Message-Id: --- hw/intc/ibex_plic.c | 15 ++

Re: [PATCH v3 05/10] migration/dirtyrate: Record hash results for each sampled page

2020-08-21 Thread Zheng Chuan
On 2020/8/21 20:39, Dr. David Alan Gilbert wrote: > * Daniel P. Berrangé (berra...@redhat.com) wrote: >> On Fri, Aug 21, 2020 at 08:22:06PM +0800, Zheng Chuan wrote: >>> >>> >>> On 2020/8/21 1:55, Dr. David Alan Gilbert wrote: * Daniel P. Berrangé (berra...@redhat.com) wrote: > On Thu,

Re: [PATCH v8 1/1] audio/jack: fix use after free segfault

2020-08-21 Thread Christian Schoenebeck
On Samstag, 22. August 2020 02:16:23 CEST Geoffrey McRae wrote: > On 2020-08-22 03:47, Paolo Bonzini wrote: > > On 21/08/20 19:34, Christian Schoenebeck wrote: > >>> static void qjack_fini_out(HWVoiceOut *hw) > >>> { > >>> > >>> QJackOut *jo = (QJackOut *)hw; > >>> qjack_client_fini(&

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