[PATCH 08/12] migration/colo: Plug memleaks in colo_process_incoming_thread

'local_err' forgot to free in colo_process_incoming_thread error path. Fix that. Reported-by: Euler Robot Signed-off-by: Pan Nengyuan --- Cc: Hailiang Zhang Cc: Juan Quintela Cc: "Dr. David Alan Gilbert" --- migration/colo.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/migration/col

[PATCH 09/12] blockdev: Fix a memleak in drive_backup_prepare()

'local_err' seems forgot to propagate in error path, it'll cause a memleak. Fix it. Reported-by: Euler Robot Signed-off-by: Pan Nengyuan --- Cc: Kevin Wolf Cc: Max Reitz Cc: Markus Armbruster Cc: qemu-bl...@nongnu.org --- blockdev.c | 1 + 1 file changed, 1 insertion(+) diff --git a/blockde

Re: [PATCH 02/12] hw/vfio/ap: Plug memleak in vfio_ap_get_group()

On 2020-08-14 18:02, Pan Nengyuan wrote: Missing g_error_free() in vfio_ap_get_group() error path. Fix that. Reported-by: Euler Robot Signed-off-by: Pan Nengyuan --- Cc: Cornelia Huck Cc: Thomas Huth Cc: Christian Borntraeger Cc: Tony Krowiak Cc: Halil Pasic Cc: Pierre Morel Cc: Alex

Re: [PATCH v2 000/150] Meson integration for 5.2

Patchew URL: https://patchew.org/QEMU/20200814091326.16173-1-pbonz...@redhat.com/ Hi, This series failed the docker-mingw@fedora build test. Please find the testing commands and their output below. If you have Docker installed, you can probably reproduce it locally. === TEST SCRIPT BEGIN ===

Re: [PATCH v2 000/150] Meson integration for 5.2

Patchew URL: https://patchew.org/QEMU/20200814091326.16173-1-pbonz...@redhat.com/ Hi, This series failed the docker-quick@centos7 build test. Please find the testing commands and their output below. If you have Docker installed, you can probably reproduce it locally. === TEST SCRIPT BEGIN ==

Re: [PATCH v2 000/150] Meson integration for 5.2

Patchew URL: https://patchew.org/QEMU/20200814091326.16173-1-pbonz...@redhat.com/ Hi, This series seems to have some coding style problems. See output below for more information: Type: series Message-id: 20200814091326.16173-1-pbonz...@redhat.com Subject: [PATCH v2 000/150] Meson integration

[PATCH] hw/sd/allwinner-sdhost: Use AddressSpace for DMA transfers

Allow the device to execute the DMA transfers in a different AddressSpace. The A10 and H3 SoC keep using the system_memory address space, but via the proper dma_memory_access() API. Signed-off-by: Philippe Mathieu-Daudé --- Based-on: <20200814092346.21825-1-f4...@amsat.org> "hw/sd: Use sdbus_rea

Re: [PATCH v13 00/11] iotests: Dump QCOW2 dirty bitmaps metadata

Dear Eric! Vladimir has compeated reviewing this series. I have not received any other responses to it so far. So, is it good for pull request now? Would you please consider taking this series as you did it with the Vladimir's related one? Kindly, Andrey On 06.08.2020 22:35, Andrey Shinke

Re: [PATCH] hw/sd/allwinner-sdhost: Use AddressSpace for DMA transfers

Patchew URL: https://patchew.org/QEMU/20200814110057.307-1-f4...@amsat.org/ Hi, This series failed the docker-mingw@fedora build test. Please find the testing commands and their output below. If you have Docker installed, you can probably reproduce it locally. === TEST SCRIPT BEGIN === #! /bi

Re: [PATCH] hw/sd/allwinner-sdhost: Use AddressSpace for DMA transfers

Patchew URL: https://patchew.org/QEMU/20200814110057.307-1-f4...@amsat.org/ Hi, This series failed the docker-quick@centos7 build test. Please find the testing commands and their output below. If you have Docker installed, you can probably reproduce it locally. === TEST SCRIPT BEGIN === #!/bi

[PATCH] hw/net/allwinner-sun8i-emac: Use AddressSpace for DMA transfers

Allow the device to execute the DMA transfers in a different AddressSpace. The H3 SoC keeps using the system_memory address space, but via the proper dma_memory_access() API. Signed-off-by: Philippe Mathieu-Daudé --- Tested with: AVOCADO_ALLOW_LARGE_STORAGE=1 avocado run -t machine:orangepi-pc

Re: device compatibility interface for live migration with assigned devices

On Fri, 2020-08-14 at 13:16 +0800, Yan Zhao wrote: > On Thu, Aug 13, 2020 at 12:24:50PM +0800, Jason Wang wrote: > > > > On 2020/8/10 下午3:46, Yan Zhao wrote: > > > > driver is it handled by? > > > > > > It looks that the devlink is for network device specific, and in > > > devlink.h, it says > >

[PATCH] hw/arm/musicpal: Use AddressSpace for DMA transfers

Allow the device to execute the DMA transfers in a different AddressSpace. We keep using the system_memory address space, but via the proper dma_memory_access() API. Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/musicpal.c | 45 +++-- 1 file changed, 3

[PATCH v2 2/9] block/io.c: drop assertion on double waiting for request serialisation

The comments states, that on misaligned request we should have already been waiting. But for bdrv_padding_rmw_read, we called bdrv_mark_request_serialising with align = request_alignment, and now we serialise with align = cluster_size. So we may have to wait again with larger alignment. Note, that

[PATCH v2 3/9] block/io: split out bdrv_find_conflicting_request

To be reused in separate. Signed-off-by: Vladimir Sementsov-Ogievskiy --- block/io.c | 71 +++--- 1 file changed, 41 insertions(+), 30 deletions(-) diff --git a/block/io.c b/block/io.c index b18680a842..5b96715058 100644 --- a/block/io.c +++ b/blo

[PATCH v2 4/9] block/io: bdrv_wait_serialising_requests_locked: drop extra bs arg

bs is linked in req, so no needs to pass it separately. Most of tracked-requests API doesn't have bs argument. Actually, after this patch only tracked_request_begin has it, but it's for purpose. While being here, also add a comment about what "_locked" is. Signed-off-by: Vladimir Sementsov-Ogievs

[PATCH v2 6/9] block: introduce BDRV_REQ_NO_WAIT flag

Add flag to make serialising request no wait: if there are conflicting requests, just return error immediately. It's will be used in upcoming preallocate filter. Signed-off-by: Vladimir Sementsov-Ogievskiy --- include/block/block.h | 9 - block/io.c| 13 - 2 file

[PATCH v2 0/9] preallocate filter

Hi all! Here is a filter, which does preallocation on write. In Virtuozzo we have to deal with some custom distributed storage solution, where allocation is relatively expensive operation. We have to workaround it in Qemu, so here is a new filter. For the details refer to original cover-letter "

[PATCH v2 9/9] iotests: add 298 to test new preallocate filter driver

Signed-off-by: Vladimir Sementsov-Ogievskiy --- tests/qemu-iotests/298 | 46 ++ tests/qemu-iotests/298.out | 5 + tests/qemu-iotests/group | 1 + 3 files changed, 52 insertions(+) create mode 100644 tests/qemu-iotests/298 create mode 100644 tests/

[PATCH v2 5/9] block: bdrv_mark_request_serialising: split non-waiting function

We'll need a separate function, which will only "mark" request serialising with specified align but not wait for conflicting requests. So, it will be like old bdrv_mark_request_serialising(), before merging bdrv_wait_serialising_requests_locked() into it. To reduce the possible mess, let's do the

[PATCH v2 7/9] block: introduce preallocate filter

It's intended to be inserted between format and protocol nodes to preallocate additional space (expanding protocol file) on writes crossing EOF. It improves performance for file-systems with slow allocation. Signed-off-by: Vladimir Sementsov-Ogievskiy --- docs/system/qemu-block-drivers.rst.inc |

[PATCH v2 1/9] block: simplify comment to BDRV_REQ_SERIALISING

1. BDRV_REQ_NO_SERIALISING doesn't exist already, don't mention it. 2. We are going to add one more user of BDRV_REQ_SERIALISING, so comment about backup becomes a bit confusing here. The use case in backup is documented in block/backup.c, so let's just drop duplication here. 3. The fact

[PATCH v2 8/9] iotests.py: add verify_o_direct helper

Add python notrun-helper similar to _check_o_direct for bash tests. To be used in the following commit. Signed-off-by: Vladimir Sementsov-Ogievskiy --- tests/qemu-iotests/iotests.py | 6 ++ 1 file changed, 6 insertions(+) diff --git a/tests/qemu-iotests/iotests.py b/tests/qemu-iotests/iotes

[PATCH] loader.c: Add support Motrola S-record format.

Since the Renesas development environment may use the S-Record format, it is convenient to handle this as well as the HEX format. Signed-off-by: Yoshinori Sato --- include/hw/loader.h | 14 +++ hw/core/loader.c| 212 2 files changed, 226 insertio

[PATCH 1/1] include/elf.h: Add EM_RX.

RX's ELF machine not defined elf.h. Added it. Signed-off-by: Yoshinori Sato --- include/elf.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/elf.h b/include/elf.h index 5b06b55f28..b14ecade48 100644 --- a/include/elf.h +++ b/include/elf.h @@ -172,6 +172,8 @@ typedef struct mips_el

[PATCH] hw/block/nand: Decommission the NAND museum

This is the QEMU equivalent of this Linux commit (but 7 years later): https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=f7025a43a9da2 The MTD subsystem has its own small museum of ancient NANDs in a form of the CONFIG_MTD_NAND_MUSEUM_IDS configuration option.

Re: [PATCH] hw/block/nand: Decommission the NAND museum

I forgot to Cc qemu-arm@, doing it now since most of the users of this are ARM machines. On 8/14/20 3:21 PM, Philippe Mathieu-Daudé wrote: > This is the QEMU equivalent of this Linux commit (but 7 years later): > https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=f7025a4

[PATCH] hw/net/xilinx_axienet: Remove unused code

Most of the MDIOBus fields are unused. The ADVERTISE_10HALF definition is unused. Remove unused code. Signed-off-by: Philippe Mathieu-Daudé --- hw/net/xilinx_axienet.c | 23 --- 1 file changed, 23 deletions(-) diff --git a/hw/net/xilinx_axienet.c b/hw/net/xilinx_axienet.c

[PATCH] ide:do nothing for identify cmd if no any device attached

From: "zhaoxin\\rockcuioc" This patch is for avoiding win7 IDE driver polling 0x1f7 when no any device attached. During Win7 VM boot procedure, if use virtio for disk and there is no any device be attached on hda & hdb, the win7 IDE driver would poll 0x1f7 for a while. This action may be stop win

Re: QEMU latest release riscv32-softmmu not working

Hi QEMU Team -bios none worked. It fixed the issue. Thank you! Thanks, Arman On Fri, Aug 14, 2020 at 12:45 PM Chih-Min Chao wrote: > > > > On Fri, Aug 14, 2020 at 3:31 PM Philippe Mathieu-Daudé > wrote: > >> Hi Arman, >> >> On 8/13/20 10:20 PM, arman avetisyan wrote: >> > Hi QEMU Team, having

Re: [PATCH] hw/block/nand: Decommission the NAND museum

Patchew URL: https://patchew.org/QEMU/20200814132118.12450-1-f4...@amsat.org/ Hi, This series failed the docker-quick@centos7 build test. Please find the testing commands and their output below. If you have Docker installed, you can probably reproduce it locally. === TEST SCRIPT BEGIN === #!/

Re: [PATCH 12/12] test-util-sockets: Fix a memleak in test_socket_unix_abstract_good

Pan Nengyuan 于2020年8月14日周五 下午6:18写道： > > Fix a memleak in test_socket_unix_abstract_good(). > > Reported-by: Euler Robot > Signed-off-by: Pan Nengyuan > --- Hi Nengyuan, I have sent this two month ago: -->https://lists.gnu.org/archive/html/qemu-devel/2020-06/msg00809.html seems the maintainer

[PATCH 0/1] qcow2: Skip copy-on-write when allocating a zero cluster

Hi, the patch is self-explanatory, but I'm using the cover letter to raise a couple of related questions. Since commit c8bb23cbdbe / QEMU 4.1.0 (and if the storage backend allows it) writing to an image created with preallocation=metadata can be slower (20% in my tests) than writing to an image w

[PATCH 1/1] qcow2: Skip copy-on-write when allocating a zero cluster

Since commit c8bb23cbdbe32f5c326365e0a82e1b0e68cdcd8a when a write request results in a new allocation QEMU first tries to see if the rest of the cluster outside the written area contains only zeroes. In that case, instead of doing a normal copy-on-write operation and writing explicit zero buffers

[PATCH] spapr/xive: Allocate IPIs from the vCPU contexts

When QEMU switches to the XIVE interrupt mode, it performs a kvmppc_xive_source_reset() which creates all the guest interrupts at the level of the KVM device. These interrupts are backed by real HW interrupts from the IPI interrupt pool of the XIVE controller. Currently, this is done from the QEMU

Re: [PATCH] spapr/xive: Allocate IPIs from the vCPU contexts

This works as expected with a 128 vCPUs guest with pinned vcpus. The first 64 IPIs are allocated on the first chip and the remaining 64 on the second chip. Still, this is more an RFC. We have time before the end of the merge window. Thanks, C. On 8/14/20 5:03 PM, Cédric Le Goater wrote: >

[PULL v2 00/20] riscv-to-apply queue

The following changes since commit d0ed6a69d399ae193959225cdeaa9382746c91cc: Update version for v5.1.0 release (2020-08-11 17:07:03 +0100) are available in the Git repository at: g...@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20200814 for you to fetch changes up to

[PULL v2 07/20] target/riscv: check before allocating TCG temps

From: LIU Zhiwei Signed-off-by: LIU Zhiwei Signed-off-by: Richard Henderson Message-Id: <20200626205917.4545-5-zhiwei_...@c-sky.com> Signed-off-by: Richard Henderson Message-Id: <20200724002807.441147-8-richard.hender...@linaro.org> Signed-off-by: Alistair Francis --- target/riscv/insn_trans

[PULL v2 02/20] target/riscv: Generalize gen_nanbox_fpr to gen_nanbox_s

From: Richard Henderson Do not depend on the RVD extension, take input and output via TCGv_i64 instead of fpu regno. Move the function to translate.c so that it can be used in multiple trans_*.inc.c files. Signed-off-by: Richard Henderson Reviewed-by: LIU Zhiwei Message-Id: <20200724002807.44

[PULL v2 03/20] target/riscv: Generate nanboxed results from trans_rvf.inc.c

From: Richard Henderson Make sure that all results from inline single-precision scalar operations are properly nan-boxed to 64-bits. Signed-off-by: Richard Henderson Reviewed-by: LIU Zhiwei Message-Id: <20200724002807.441147-4-richard.hender...@linaro.org> Signed-off-by: Alistair Francis ---

[PULL v2 15/20] gitlab-ci/opensbi: Update GitLab CI to build generic platform

From: Bin Meng This updates the GitLab CI opensbi job to build opensbi bios images for the generic platform. Signed-off-by: Bin Meng Reviewed-by: Anup Patel Reviewed-by: Alistair Francis Message-Id: <1596439832-29238-7-git-send-email-bmeng...@gmail.com> Signed-off-by: Alistair Francis --- .

[PULL v2 16/20] target/riscv: Fix the translation of physical address

From: Zong Li The real physical address should add the 12 bits page offset. It also causes the PMP wrong checking due to the minimum granularity of PMP is 4 byte, but we always get the physical address which is 4KB alignment, that means, we always use the start address of the page to check PMP fo

[PULL v2 04/20] target/riscv: Check nanboxed inputs to fp helpers

From: Richard Henderson If a 32-bit input is not properly nanboxed, then the input is replaced with the default qnan. Signed-off-by: Richard Henderson Reviewed-by: LIU Zhiwei Message-Id: <20200724002807.441147-5-richard.hender...@linaro.org> Signed-off-by: Alistair Francis --- target/riscv/i

[PULL v2 01/20] target/riscv: Generate nanboxed results from fp helpers

From: Richard Henderson Make sure that all results from single-precision scalar helpers are properly nan-boxed to 64-bits. Signed-off-by: Richard Henderson Reviewed-by: LIU Zhiwei Message-Id: <20200724002807.441147-2-richard.hender...@linaro.org> Signed-off-by: Alistair Francis --- target/ri

[PULL v2 05/20] target/riscv: Check nanboxed inputs in trans_rvf.inc.c

From: Richard Henderson If a 32-bit input is not properly nanboxed, then the input is replaced with the default qnan. The only inline expansion is for the sign-changing set of instructions: FSGNJ.S, FSGNJX.S, FSGNJN.S. Signed-off-by: Richard Henderson Reviewed-by: LIU Zhiwei Message-Id: <2020

[PULL v2 17/20] target/riscv: Change the TLB page size depends on PMP entries.

From: Zong Li The minimum granularity of PMP is 4 bytes, it is small than 4KB page size, therefore, the pmp checking would be ignored if its range doesn't start from the alignment of one page. This patch detects the pmp entries and sets the small page size to TLB if there is a PMP entry which cov

[PULL v2 20/20] hw/intc: ibex_plic: Honour source priorities

This patch follows what commit aa4d30f6618dc "riscv: plic: Honour source priorities" does and ensures that the highest priority interrupt will be serviced first. Signed-off-by: Alistair Francis Cc: Jessica Clarke Reviewed-by: Philippe Mathieu-Daudé Message-Id: --- hw/intc/ibex_plic.c | 15 ++

Re: [PATCH] hw/net/xilinx_axienet: Remove unused code

On Fri, Aug 14, 2020 at 6:30 AM Philippe Mathieu-Daudé wrote: > > Most of the MDIOBus fields are unused. The ADVERTISE_10HALF > definition is unused. Remove unused code. > > Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis Alistair > --- > hw/net/xilinx_axienet.c | 23 --

[PULL v2 06/20] target/riscv: Clean up fmv.w.x

From: LIU Zhiwei Use tcg_gen_extu_tl_i64 to avoid the ifdef. Signed-off-by: LIU Zhiwei Signed-off-by: Richard Henderson Message-Id: <20200626205917.4545-7-zhiwei_...@c-sky.com> Signed-off-by: Richard Henderson Message-Id: <20200724002807.441147-7-richard.hender...@linaro.org> Signed-off-by: A

[PULL v2 08/20] hw/riscv: sifive_u: Add a dummy L2 cache controller device

From: Bin Meng It is enough to simply map the SiFive FU540 L2 cache controller into the MMIO space using create_unimplemented_device(), with an FDT fragment generated, to make the latest upstream U-Boot happy. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Message-Id: <1595227748-24720-

[PULL v2 09/20] riscv: Fix bug in setting pmpcfg CSR for RISCV64

From: Hou Weiying First, sizeof(target_ulong) equals to 4 on riscv32, so this change does not change the function on riscv32. Second, sizeof(target_ulong) equals to 8 on riscv64, and 'reg_index * 8 + i' is not a legal pmp_index (we will explain later), which should be 'reg_index * 4 + i'. If the

Re: [PATCH 08/41] opentitan: Rename memmap enum constants

On Thu, Aug 13, 2020 at 3:29 PM Eduardo Habkost wrote: > > Some of the enum constant names conflict with the QOM type check > macros. This needs to be addressed to allow us to transform the > QOM type check macros into functions generated by > OBJECT_DECLARE_TYPE(). > > Rename all the constants t

[PULL v2 12/20] roms/Makefile: Build the generic platform for RISC-V OpenSBI firmware

From: Bin Meng The RISC-V generic platform is a flattened device tree (FDT) based platform where all platform specific functionality is provided based on FDT passed by previous booting stage. The support was added in the upstream OpenSBI v0.8 release recently. Update our Makefile to build the ge

[PULL v2 18/20] hw/intc: ibex_plic: Update the pending irqs

After a claim or a priority change we need to update the pending interrupts. This is based on the same patch for the SiFive PLIC: 55765822804f5a58594e "riscv: plic: Add a couple of mising sifive_plic_update calls" Signed-off-by: Alistair Francis Cc: Jessica Clarke Reviewed-by: Philippe Mathieu-D

Re: [PATCH] ide:do nothing for identify cmd if no any device attached

Patchew URL: https://patchew.org/QEMU/20200814043657.5815-1-rockcui...@zhaoxin.com/ Hi, This series seems to have some coding style problems. See output below for more information: Type: series Message-id: 20200814043657.5815-1-rockcui...@zhaoxin.com Subject: [PATCH] ide:do nothing for identi

[PULL v2 10/20] configure: Create symbolic links for pc-bios/*.elf files

From: Bin Meng Now we need to ship the OpenSBI fw_dynamic.elf image for the RISC-V Spike machine, it requires us to create symbolic links for pc-bios/*.elf files. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Message-Id: <1596439832-29238-2-git-send-email-bmeng...@gmail.com> Signed-off

[PULL v2 19/20] hw/intc: ibex_plic: Don't allow repeat interrupts on claimed lines

Once an interrupt has been claimed, but before it has been compelted we shouldn't receive any more pending interrupts. This patche keeps track of this to ensure that we don't see any more interrupts until it is completed. Signed-off-by: Alistair Francis Message-Id: <394c3f070615ff2b4fab61a1cf9cb

[PULL v2 11/20] roms/opensbi: Upgrade from v0.7 to v0.8

From: Bin Meng Upgrade OpenSBI from v0.7 to v0.8. The v0.8 release includes the following commits: 1bb00ab lib: No need to provide default PMP region using platform callbacks a9eac67 include: sbi_platform: Combine reboot and shutdown into one callback 6585fab lib: utils: Add SiFive test device

Re: [PATCH v9 1/4] hw/net/can: Introduce Xilinx ZynqMP CAN controller

On Wed, Aug 12, 2020 at 05:31:05PM -0700, Vikram Garhwal wrote: > The Xilinx ZynqMP CAN controller is developed based on SocketCAN, QEMU CAN bus > implementation. Bus connection and socketCAN connection for each CAN module > can be set through command lines. > > Example for using single CAN: >

Re: [PATCH 10/41] sifive_u: Rename memmap enum constants

On Thu, Aug 13, 2020 at 3:37 PM Eduardo Habkost wrote: > > Some of the enum constant names conflict with the QOM type check > macros. This needs to be addressed to allow us to transform the > QOM type check macros into functions generated by > OBJECT_DECLARE_TYPE(). > > Rename all the constants t

Re: [PATCH 09/41] sifive_e: Rename memmap enum constants

On Thu, Aug 13, 2020 at 3:28 PM Eduardo Habkost wrote: > > Some of the enum constant names conflict with the QOM type check > macros. This needs to be addressed to allow us to transform the > QOM type check macros into functions generated by > OBJECT_DECLARE_TYPE(). > > Rename all the constants t

Re: [PATCH v7 14/47] stream: Deal with filters

On 10.08.2020 14:04, Vladimir Sementsov-Ogievskiy wrote: 10.08.2020 11:12, Max Reitz wrote: On 07.08.20 12:29, Vladimir Sementsov-Ogievskiy wrote: 16.07.2020 17:59, Max Reitz wrote: On 10.07.20 19:41, Andrey Shinkevich wrote: On 10.07.2020 18:24, Max Reitz wrote: On 09.07.20 16:52, Andrey Sh

Re: [PATCH] ide:do nothing for identify cmd if no any device attached

Patchew URL: https://patchew.org/QEMU/20200814043657.5815-1-rockcui...@zhaoxin.com/ Hi, This series failed the docker-quick@centos7 build test. Please find the testing commands and their output below. If you have Docker installed, you can probably reproduce it locally. === TEST SCRIPT BEGIN

Re: [PATCH v2 2/3] target/arm: Implement an IMPDEF pauth algorithm

On 8/14/20 2:26 AM, Andrew Jones wrote: >> +static uint64_t __attribute__((noinline)) >> +pauth_computepac_impdef(uint64_t data, uint64_t modifier, ARMPACKey key) > > Out of curiosity, why do we need to make these computepac functions > noinline? Oh, heh. Left over from profiling. Will remove.

Re: [PATCH 2/3] softfloat: add APIs to handle alternative sNaN propagation

On 8/14/20 1:59 AM, Chih-Min Chao wrote: > By the way,  the other patches have been queued in softfloat-next.  > Do I need to resend the other two patches in the next version or just this > one ? Just this one. Thanks. r~

Re: [PATCH v2 0/9] preallocate filter

Patchew URL: https://patchew.org/QEMU/20200814130348.20625-1-vsement...@virtuozzo.com/ Hi, This series failed the docker-mingw@fedora build test. Please find the testing commands and their output below. If you have Docker installed, you can probably reproduce it locally. === TEST SCRIPT BEGI

Re: [PATCH v2 0/9] preallocate filter

Patchew URL: https://patchew.org/QEMU/20200814130348.20625-1-vsement...@virtuozzo.com/ Hi, This series failed the docker-quick@centos7 build test. Please find the testing commands and their output below. If you have Docker installed, you can probably reproduce it locally. === TEST SCRIPT BEG

[PATCH 0/5] hw/avr: Start using the Clock API

In this series we slowly start to use the recently added Clock API in the AVR ATmega MCU. As the Clock Control Unit is not yet modelled, we simply connect the XTAL sink to the UART and Timer sources. Philippe Mathieu-Daudé (5): hw/avr/atmega: Introduce the I/O clock hw/timer/avr_timer16: Use

[PATCH 5/5] hw/char/avr_usart: Trace baudrate changes

Add a trace event to track baudrate changes. Example when running the FreeRTOS acceptance test [1]: $ qemu-system-avr -machine arduino-mega-2560-v3 -bios demo.elf -trace avr\* 2546@1597415281.399619:avr_usart_update_baudrate baudrate 0x0019 (38461 bauds) 2546@1597415281.400029:avr_usart_upd

[PATCH 1/5] hw/avr/atmega: Introduce the I/O clock

Use the Clock API to model the I/O clock. As we don't model the Clock Control Unit, the XTAL is its unique clock source. Signed-off-by: Philippe Mathieu-Daudé --- hw/avr/atmega.h | 2 ++ hw/avr/atmega.c | 4 2 files changed, 6 insertions(+) diff --git a/hw/avr/atmega.h b/hw/avr/atmega.h in

[PATCH 00/18] hw/riscv: Add Microchip PolarFire SoC Icicle Kit board support

From: Bin Meng This adds support for Microchip PolarFire SoC Icicle Kit board. The Icicle Kit board integrates a PolarFire SoC, with one SiFive's E51 plus four U54 cores and many on-chip peripherals and an FPGA. For more details about Microchip PolarFire Soc, please see: https://www.microsemi.co

[PATCH 3/5] hw/char/avr_usart: Restrict register definitions to source

Nothing out of our model implementation is supposed to access its registers. Keep the definitions local. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/char/avr_usart.h | 30 -- hw/char/avr_usart.c | 30 ++ 2 files changed, 30

[PATCH 2/5] hw/timer/avr_timer16: Use the Clock API

Expose the 'clkt' clock source. Connect the MCU I/O clock to it. Drop the now unused 'cpu-frequency-hz' static property. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/timer/avr_timer16.h | 3 ++- hw/avr/atmega.c| 3 +-- hw/timer/avr_timer16.c | 12 3

[PATCH 02/18] hw/riscv: hart: Add a new 'resetvec' property

From: Bin Meng RISC-V machines do not instantiate RISC-V CPUs directly, instead they do that via the hart array. Add a new property for the reset vector address to allow the value to be passed to the CPU, before CPU is realized. Signed-off-by: Bin Meng --- hw/riscv/riscv_hart.c | 3 ++

[PATCH 04/18] hw/riscv: Initial support for Microchip PolarFire SoC Icicle Kit board

From: Bin Meng This is an initial support for Microchip PolarFire SoC Icicle Kit. The Icicle Kit board integrates a PolarFire SoC, with one SiFive's E51 plus four U54 cores and many on-chip peripherals and an FPGA. For more details about Microchip PolarFire Soc, please see: https://www.microsemi

[PATCH 4/5] hw/char/avr_usart: Use the Clock API

Expose the 'xck' clock source. Connect the MCU I/O clock to it. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/char/avr_usart.h | 2 ++ hw/avr/atmega.c | 1 + hw/char/avr_usart.c | 3 +++ 3 files changed, 6 insertions(+) diff --git a/include/hw/char/avr_usart.h b/inclu

[PATCH 01/18] target/riscv: cpu: Add a new 'resetvec' property

From: Bin Meng Currently the reset vector address is hard-coded in a RISC-V CPU's instance_init() routine. In a real world we can have 2 exact same CPUs except for the reset vector address, which is pretty common in the RISC-V core IP licensing business. Normally reset vector address is a config

[PATCH 10/18] hw/sd: Add Cadence SDHCI emulation

From: Bin Meng Cadence SD/SDIO/eMMC Host Controller (SD4HC) is an SDHCI compatible controller. The SDHCI compatible registers start from offset 0x200, which are called Slot Register Set (SRS) in its datasheet. This creates a Cadence SDHCI model built on top of the existing generic SDHCI model. C

[PATCH 08/18] hw/sd: sd: Correctly set the high capacity bit

From: Bin Meng Per the SD spec, Standard Capacity SD Memory Card (SDSC) supports capacity up to and including 2 GiB. Signed-off-by: Bin Meng --- hw/sd/sd.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/sd/sd.c b/hw/sd/sd.c index 51f5900..5e7fc3f 100644 --- a/hw/sd/sd.

[PATCH 03/18] target/riscv: cpu: Set reset vector based on the configured property value

From: Bin Meng Now that we have the newly introduced 'resetvec' property in the RISC-V CPU and HART, instead of hard-coding the reset vector addr in the CPU's instance_init(), move that to riscv_cpu_realize() based on the configured property value from the RISC-V machines. Signed-off-by: Bin Men

[PATCH 05/18] hw/char: Add Microchip PolarFire SoC MMUART emulation

From: Bin Meng Microchip PolarFire SoC MMUART is ns16550 compatible, with some additional registers. Create a simple MMUART model built on top of the existing ns16550 model. Signed-off-by: Bin Meng --- MAINTAINERS | 2 + hw/char/Kconfig | 3 ++ hw

[PATCH 11/18] hw/riscv: microchip_pfsoc: Connect a Cadence SDHCI controller and an SD card

From: Bin Meng Microchip PolarFire SoC integrates one Cadence SDHCI controller. On the Icicle Kit board, one eMMC chip and an external SD card connect to this controller depending on different configuration. As QEMU does not support eMMC yet, we just emulate the SD card configuration. To test th

Re: [PATCH] hw/block/nand: Decommission the NAND museum

On 8/14/20 4:22 PM, no-re...@patchew.org wrote: > Patchew URL: https://patchew.org/QEMU/20200814132118.12450-1-f4...@amsat.org/ > Hi, > > This series failed the docker-quick@centos7 build test. Please find the > testing commands and > their output below. If you have Docker installed, you can prob

[PATCH 09/18] hw/sd: sdhci: Make sdhci_poweron_reset() internal visible

From: Bin Meng sdhci_poweron_reset() might be needed for any SDHCI compatible device that is built on top of the generic SDHCI device. Signed-off-by: Bin Meng --- hw/sd/sdhci-internal.h | 1 + hw/sd/sdhci.c | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/hw/sd/s

[PATCH 13/18] hw/riscv: microchip_pfsoc: Connect a DMA controller

From: Bin Meng Connect a DMA controller to Microchip PolarFire SoC. Note interrupt has not been connected due to missing information in the manual how interrupts are routed to PLIC. On the Icicle Kit board, the HSS firmware utilizes the on-chip DMA controller to move the 2nd stage bootloader in

[PATCH 06/18] hw/riscv: microchip_pfsoc: Connect 5 MMUARTs

From: Bin Meng Microchip PolarFire SoC has 5 MMUARTs, and the Icicle Kit board wires 4 of them out. Let's connect all 5 MMUARTs. Signed-off-by: Bin Meng --- hw/riscv/Kconfig | 1 + hw/riscv/microchip_pfsoc.c | 30 ++ include/hw/riscv/micr

[PATCH 18/18] hw/riscv: microchip_pfsoc: Document the software used for testing

From: Bin Meng Add some useful comments to document the software used for testing. including how to patch HSS to bypass the DDR memory initialization, HSS and Yocto BSP build instructions, etc. To launch this machine for testing: $ qemu-system-riscv64 -M microchip-icicle-kit -smp 5 \ -bios p

[PATCH 14/18] hw/net: cadence_gem: Add a new 'phy-addr' property

From: Bin Meng At present the PHY address of the PHY connected to GEM is hard-coded to either 23 (BOARD_PHY_ADDRESS) or 0. This might not be the case for all boards. Add a new 'phy-addr' property so that board can specify the PHY address for each GEM instance. Signed-off-by: Bin Meng --- hw/n

[PATCH 07/18] hw/sd: sd: Fix incorrect populated function switch status data structure

From: Bin Meng At present the function switch status data structure bit [399:376] are wrongly pupulated. These 3 bytes encode function switch status for the 6 function groups, with 4 bits per group, starting from function group 6 at bit 399, then followed by function group 5 at bit 395, and so on

[PATCH 15/18] hw/riscv: microchip_pfsoc: Connect 2 Cadence GEMs

From: Bin Meng Microchip PolarFire SoC integrates 2 Candence GEMs to provide IEEE 802.3 standard-compliant 10/100/1000 Mbps ethernet interface. On the Icicle Kit board, GEM0 connects to a PHY at address 8 while GEM1 connects to a PHY at address 9. The 2nd stage bootloader (U-Boot) is using GEM1

[PATCH 12/18] hw/dma: Add Microchip PolarFire Soc DMA controller emulation

From: Bin Meng Microchip PolarFire SoC integrates a DMA engine that supports: * Independent concurrent DMA transfers using 4 DMA channels * Generation of interrupts on various conditions during execution This creates a simple model to support polling mode which is enough for firmware usage. Whil

[PATCH 16/18] hw/riscv: microchip_pfsoc: Hook GPIO controllers

From: Bin Meng Microchip PolarFire SoC integrates 3 GPIOs controllers. It seems enough to create unimplemented devices to cover their register spaces at this point. With this commit, QEMU can boot to U-Boot (2nd stage bootloader) all the way to the Linux shell login prompt, with a modified HSS (

[PATCH 17/18] hw/riscv: clint: Avoid using hard-coded timebase frequency

From: Bin Meng At present the CLINT timestamp is using a hard-coded timebase frequency value SIFIVE_CLINT_TIMEBASE_FREQ. This might not be true for all boards. Add a new 'timebase-freq' property to the CLINT device, and update various functions to accept this as a parameter. Signed-off-by: Bin

Re: [PATCH 1/7] block/null: Make more explicit the driver default size is 1GiB

On 8/14/20 1:28 AM, Philippe Mathieu-Daudé wrote: > As it is not obvious the default size for the null block driver > is 1 GiB, replace the obfuscated '1 << 30' magic value by a > definition using IEC binary prefixes. > > Signed-off-by: Philippe Mathieu-Daudé > --- > block/null.c | 4 +++- > 1 f

Re: [PATCH 2/7] hw/ide/core: Trivial typo fix

On 8/14/20 1:28 AM, Philippe Mathieu-Daudé wrote: > Signed-off-by: Philippe Mathieu-Daudé > --- > hw/ide/core.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) Reviewed-by: Richard Henderson r~

Re: [PATCH 3/7] hw/ide/core: Replace magic '512' value by BDRV_SECTOR_SIZE

On 8/14/20 1:28 AM, Philippe Mathieu-Daudé wrote: > Use self-explicit definitions instead of magic '512' value. > > Signed-off-by: Philippe Mathieu-Daudé > --- > hw/ide/core.c | 23 --- > 1 file changed, 12 insertions(+), 11 deletions(-) Reviewed-by: Richard Henderson r~

Re: [PATCH 5/7] hw/ide/atapi: Replace magic '512' value by BDRV_SECTOR_SIZE

On 8/14/20 1:28 AM, Philippe Mathieu-Daudé wrote: > Use self-explicit definitions instead of magic '512' value. > > Signed-off-by: Philippe Mathieu-Daudé > --- > hw/ide/atapi.c | 8 > 1 file changed, 4 insertions(+), 4 deletions(-) Reviewed-by: Richard Henderson > diff --git a/hw/i

Re: [PATCH 4/7] hw/ide/ahci: Replace magic '512' value by BDRV_SECTOR_SIZE

On 8/14/20 1:28 AM, Philippe Mathieu-Daudé wrote: > Use self-explicit definitions instead of magic '512' value. > > Signed-off-by: Philippe Mathieu-Daudé > --- > hw/ide/ahci.c | 5 +++-- > 1 file changed, 3 insertions(+), 2 deletions(-) Reviewed-by: Richard Henderson r~

Re: [PATCH 6/7] hw/ide/pci: Replace magic '512' value by BDRV_SECTOR_SIZE

On 8/14/20 1:28 AM, Philippe Mathieu-Daudé wrote: > Use self-explicit definitions instead of magic '512' value. > > Signed-off-by: Philippe Mathieu-Daudé > --- > hw/ide/pci.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) Reviewed-by: Richard Henderson r~

Re: [PATCH] spapr/xive: Use xive_source_esb_len()

> I found out recently that XIVE support was > merged into FreeBSD and with that it also came some good comments > about xive... cool ! Does it run in a QEMU PowerNV machine ? C.

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